1 /* $NetBSD: cpu.h,v 1.50 2006/06/30 17:54:51 freza Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #ifdef _KERNEL 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #include <machine/frame.h> 53 #include <machine/psl.h> 54 #include <machine/intr.h> 55 #include <sys/device.h> 56 57 #include <sys/cpu_data.h> 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct device *ci_dev; /* device of corresponding cpu */ 62 struct lwp *ci_curlwp; /* current owner of the processor */ 63 64 struct pcb *ci_curpcb; 65 struct pmap *ci_curpm; 66 struct lwp *ci_fpulwp; 67 struct lwp *ci_veclwp; 68 struct pcb *ci_idle_pcb; /* PA of our idle pcb */ 69 int ci_cpuid; 70 71 volatile int ci_astpending; 72 int ci_want_resched; 73 volatile u_long ci_lasttb; 74 volatile int ci_tickspending; 75 volatile int ci_cpl; 76 volatile int ci_iactive; 77 volatile int ci_ipending; 78 int ci_intrdepth; 79 char *ci_intstk; 80 #define CPUSAVE_LEN 8 81 register_t ci_tempsave[CPUSAVE_LEN]; 82 register_t ci_ddbsave[CPUSAVE_LEN]; 83 register_t ci_ipkdbsave[CPUSAVE_LEN]; 84 #define CPUSAVE_R28 0 /* where r28 gets saved */ 85 #define CPUSAVE_R29 1 /* where r29 gets saved */ 86 #define CPUSAVE_R30 2 /* where r30 gets saved */ 87 #define CPUSAVE_R31 3 /* where r31 gets saved */ 88 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 89 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 90 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 91 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 92 #define DISISAVE_LEN 4 93 register_t ci_disisave[DISISAVE_LEN]; 94 struct cache_info ci_ci; 95 void *ci_sysmon_cookie; 96 void (*ci_idlespin)(void); 97 uint32_t ci_khz; 98 struct evcnt ci_ev_clock; /* clock intrs */ 99 struct evcnt ci_ev_statclock; /* stat clock */ 100 struct evcnt ci_ev_softclock; /* softclock intrs */ 101 struct evcnt ci_ev_softnet; /* softnet intrs */ 102 struct evcnt ci_ev_softserial; /* softserial intrs */ 103 struct evcnt ci_ev_traps; /* calls to trap() */ 104 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 105 struct evcnt ci_ev_udsi; /* user DSI traps */ 106 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 107 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 108 struct evcnt ci_ev_isi; /* user ISI traps */ 109 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 110 struct evcnt ci_ev_pgm; /* user PGM traps */ 111 struct evcnt ci_ev_fpu; /* FPU traps */ 112 struct evcnt ci_ev_fpusw; /* FPU context switch */ 113 struct evcnt ci_ev_ali; /* Alignment traps */ 114 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 115 struct evcnt ci_ev_scalls; /* system call traps */ 116 struct evcnt ci_ev_vec; /* Altivec traps */ 117 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 118 struct evcnt ci_ev_umchk; /* user MCHK events */ 119 }; 120 121 #ifdef MULTIPROCESSOR 122 static __inline int 123 cpu_number(void) 124 { 125 int pir; 126 127 __asm ("mfspr %0,1023" : "=r"(pir)); 128 return pir; 129 } 130 131 void cpu_boot_secondary_processors(void); 132 133 134 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 135 #define CPU_INFO_ITERATOR int 136 #define CPU_INFO_FOREACH(cii, ci) \ 137 cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++ 138 139 #else 140 141 #define cpu_number() 0 142 143 #define CPU_INFO_ITERATOR int 144 #define CPU_INFO_FOREACH(cii, ci) \ 145 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 146 147 #endif /* MULTIPROCESSOR */ 148 149 extern struct cpu_info cpu_info[]; 150 151 static __inline struct cpu_info * 152 curcpu(void) 153 { 154 struct cpu_info *ci; 155 156 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 157 return ci; 158 } 159 160 #define curlwp (curcpu()->ci_curlwp) 161 #define curpcb (curcpu()->ci_curpcb) 162 #define curpm (curcpu()->ci_curpm) 163 164 static __inline register_t 165 mfmsr(void) 166 { 167 register_t msr; 168 169 __asm volatile ("mfmsr %0" : "=r"(msr)); 170 return msr; 171 } 172 173 static __inline void 174 mtmsr(register_t msr) 175 { 176 177 __asm volatile ("mtmsr %0" : : "r"(msr)); 178 } 179 180 static __inline uint32_t 181 mftbl(void) 182 { 183 uint32_t tbl; 184 185 __asm volatile ( 186 #ifdef PPC_IBM403 187 " mftblo %0 \n" 188 #else 189 " mftbl %0 \n" 190 #endif 191 : "=r" (tbl)); 192 193 return tbl; 194 } 195 196 static __inline uint64_t 197 mftb(void) 198 { 199 uint64_t tb; 200 201 #ifdef _LP64 202 __asm volatile ("mftb %0" : "=r"(tb)); 203 #else 204 int tmp; 205 206 __asm volatile ( 207 #ifdef PPC_IBM403 208 "1: mftbhi %0 \n" 209 " mftblo %0+1 \n" 210 " mftbhi %1 \n" 211 #else 212 "1: mftbu %0 \n" 213 " mftb %0+1 \n" 214 " mftbu %1 \n" 215 #endif 216 " cmplw %0,%1 \n" 217 " bne- 1b \n" 218 : "=r" (tb), "=r"(tmp) :: "cr0"); 219 #endif 220 221 return tb; 222 } 223 224 static __inline uint32_t 225 mfrtcl(void) 226 { 227 uint32_t rtcl; 228 229 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 230 return rtcl; 231 } 232 233 static __inline void 234 mfrtc(uint32_t *rtcp) 235 { 236 uint32_t tmp; 237 238 __asm volatile ( 239 "1: mfrtcu %0 \n" 240 " mfrtcl %1 \n" 241 " mfrtcu %2 \n" 242 " cmplw %0,%2 \n" 243 " bne- 1b" 244 : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0"); 245 } 246 247 static __inline uint32_t 248 mfpvr(void) 249 { 250 uint32_t pvr; 251 252 __asm volatile ("mfpvr %0" : "=r"(pvr)); 253 return (pvr); 254 } 255 256 static __inline int 257 cntlzw(uint32_t val) 258 { 259 int cnt; 260 261 __asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val)); 262 return (cnt); 263 } 264 265 #if defined(PPC_IBM4XX) || defined(PPC_IBM403) 266 /* 267 * DCR (Device Control Register) access. These have to be 268 * macros because register address is encoded as immediate 269 * operand. 270 */ 271 #define mtdcr(reg, val) \ 272 __asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val)) 273 274 #define mfdcr(reg) \ 275 ({ \ 276 uint32_t __val; \ 277 \ 278 __asm volatile("mfdcr %0,%1" : "=r"(__val) : "K"(reg)); \ 279 __val; \ 280 }) 281 #endif /* PPC_IBM4XX || PPC_IBM403 */ 282 283 /* 284 * CLKF_BASEPRI is dependent on the underlying interrupt code 285 * and can not be defined here. It should be defined in 286 * <machine/intr.h> 287 */ 288 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 289 #define CLKF_PC(frame) ((frame)->srr0) 290 #define CLKF_INTR(frame) ((frame)->depth > 0) 291 292 #define LWP_PC(l) (trapframe(l)->srr0) 293 294 #define cpu_swapout(p) 295 #define cpu_proc_fork(p1, p2) 296 297 extern int powersave; 298 extern int cpu_timebase; 299 extern int cpu_printfataltraps; 300 extern char cpu_model[]; 301 302 struct cpu_info *cpu_attach_common(struct device *, int); 303 void cpu_setup(struct device *, struct cpu_info *); 304 void cpu_identify(char *, size_t); 305 void delay (unsigned int); 306 void cpu_probe_cache(void); 307 void dcache_flush_page(vaddr_t); 308 void icache_flush_page(vaddr_t); 309 void dcache_flush(vaddr_t, vsize_t); 310 void icache_flush(vaddr_t, vsize_t); 311 void *mapiodev(paddr_t, psize_t); 312 313 #define DELAY(n) delay(n) 314 315 #define need_resched(ci) (ci->ci_want_resched = 1, ci->ci_astpending = 1) 316 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, curcpu()->ci_astpending = 1) 317 #define signotify(p) (curcpu()->ci_astpending = 1) 318 319 #ifdef PPC_OEA 320 void oea_init(void (*)(void)); 321 void oea_startup(const char *); 322 void oea_dumpsys(void); 323 void oea_install_extint(void (*)(void)); 324 paddr_t kvtop(caddr_t); 325 void softnet(int); 326 327 extern paddr_t msgbuf_paddr; 328 extern int cpu_altivec; 329 #endif 330 331 #endif /* _KERNEL */ 332 333 #if defined(_KERNEL) || defined(_STANDALONE) 334 #if !defined(CACHELINESIZE) 335 #ifdef PPC_IBM403 336 #define CACHELINESIZE 16 337 #else 338 #define CACHELINESIZE 32 339 #endif 340 #endif 341 #endif 342 343 void __syncicache(void *, size_t); 344 345 /* 346 * CTL_MACHDEP definitions. 347 */ 348 #define CPU_CACHELINE 1 349 #define CPU_TIMEBASE 2 350 #define CPU_CPUTEMP 3 351 #define CPU_PRINTFATALTRAPS 4 352 #define CPU_CACHEINFO 5 353 #define CPU_ALTIVEC 6 354 #define CPU_MODEL 7 355 #define CPU_POWERSAVE 8 356 #define CPU_MAXID 9 357 358 #define CTL_MACHDEP_NAMES { \ 359 { 0, 0 }, \ 360 { "cachelinesize", CTLTYPE_INT }, \ 361 { "timebase", CTLTYPE_INT }, \ 362 { "cputempature", CTLTYPE_INT }, \ 363 { "printfataltraps", CTLTYPE_INT }, \ 364 { "cacheinfo", CTLTYPE_STRUCT }, \ 365 { "altivec", CTLTYPE_INT }, \ 366 { "model", CTLTYPE_STRING }, \ 367 { "powersave", CTLTYPE_INT }, \ 368 } 369 370 #endif /* _POWERPC_CPU_H_ */ 371