1 /* $NetBSD: cpu.h,v 1.26 2003/02/03 17:10:01 matt Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 #if defined(_KERNEL_OPT) 39 #include "opt_lockdebug.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_ppcarch.h" 42 #endif 43 44 #include <machine/frame.h> 45 #include <machine/psl.h> 46 #include <machine/intr.h> 47 #include <sys/device.h> 48 49 50 struct cache_info { 51 int dcache_size; 52 int dcache_line_size; 53 int icache_size; 54 int icache_line_size; 55 }; 56 57 58 #ifdef _KERNEL 59 #include <sys/sched.h> 60 #include <dev/sysmon/sysmonvar.h> 61 62 struct cpu_info { 63 struct schedstate_percpu ci_schedstate; /* scheduler state */ 64 struct device *ci_dev; /* device of corresponding cpu */ 65 struct lwp *ci_curlwp; /* current owner of the processor */ 66 67 struct pcb *ci_curpcb; 68 struct pmap *ci_curpm; 69 struct lwp *ci_fpulwp; 70 struct lwp *ci_veclwp; 71 struct pcb *ci_idle_pcb; /* PA of our idle pcb */ 72 int ci_cpuid; 73 74 int ci_astpending; 75 int ci_want_resched; 76 u_long ci_lasttb; 77 int ci_tickspending; 78 int ci_cpl; 79 int ci_iactive; 80 int ci_ipending; 81 int ci_intrdepth; 82 char *ci_intstk; 83 char *ci_spillstk; 84 register_t ci_tempsave[8]; 85 register_t ci_ddbsave[8]; 86 register_t ci_ipkdbsave[8]; 87 register_t ci_disisave[4]; 88 struct cache_info ci_ci; 89 struct sysmon_envsys ci_sysmon; 90 struct envsys_tre_data ci_tau_info; 91 struct evcnt ci_ev_clock; /* clock intrs */ 92 struct evcnt ci_ev_softclock; /* softclock intrs */ 93 struct evcnt ci_ev_softnet; /* softnet intrs */ 94 struct evcnt ci_ev_softserial; /* softserial intrs */ 95 struct evcnt ci_ev_traps; /* calls to trap() */ 96 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 97 struct evcnt ci_ev_udsi; /* user DSI traps */ 98 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 99 struct evcnt ci_ev_isi; /* user ISI traps */ 100 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 101 struct evcnt ci_ev_pgm; /* user PGM traps */ 102 struct evcnt ci_ev_fpu; /* FPU traps */ 103 struct evcnt ci_ev_fpusw; /* FPU context switch */ 104 struct evcnt ci_ev_ali; /* Alignment traps */ 105 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 106 struct evcnt ci_ev_scalls; /* system call traps */ 107 struct evcnt ci_ev_vec; /* Altivec traps */ 108 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 109 struct evcnt ci_ev_umchk; /* user MCHK events */ 110 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 111 u_long ci_spin_locks; /* # of spin locks held */ 112 u_long ci_simple_locks; /* # of simple locks held */ 113 #endif 114 }; 115 116 #ifdef MULTIPROCESSOR 117 static __inline int 118 cpu_number(void) 119 { 120 int pir; 121 122 asm ("mfspr %0,1023" : "=r"(pir)); 123 return pir; 124 } 125 126 void cpu_boot_secondary_processors(void); 127 128 129 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 130 #define CPU_INFO_ITERATOR int 131 #define CPU_INFO_FOREACH(cii, ci) \ 132 cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++ 133 134 #else 135 136 #define cpu_number() 0 137 138 #define CPU_INFO_ITERATOR int 139 #define CPU_INFO_FOREACH(cii, ci) \ 140 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 141 142 #endif /* MULTIPROCESSOR */ 143 144 extern struct cpu_info cpu_info[]; 145 146 static __inline struct cpu_info * 147 curcpu(void) 148 { 149 struct cpu_info *ci; 150 151 asm volatile ("mfsprg %0,0" : "=r"(ci)); 152 return ci; 153 } 154 155 #define curlwp (curcpu()->ci_curlwp) 156 #define curpcb (curcpu()->ci_curpcb) 157 #define curpm (curcpu()->ci_curpm) 158 159 static __inline register_t 160 mfmsr(void) 161 { 162 register_t msr; 163 164 asm volatile ("mfmsr %0" : "=r"(msr)); 165 return msr; 166 } 167 168 static __inline void 169 mtmsr(register_t msr) 170 { 171 172 asm volatile ("mtmsr %0" : : "r"(msr)); 173 } 174 175 static __inline uint32_t 176 mftbl(void) 177 { 178 uint32_t tbl; 179 180 asm volatile ("mftbl %0" : "=r"(tbl)); 181 return tbl; 182 } 183 184 static __inline uint64_t 185 mftb(void) 186 { 187 uint64_t tb; 188 int tmp; 189 190 asm volatile ( 191 "1: mftbu %0 \n" 192 " mftb %0+1 \n" 193 " mftbu %1 \n" 194 " cmplw %0,%1 \n" 195 " bne- 1b" 196 : "=r"(tb), "=r"(tmp) :: "cr0"); 197 return tb; 198 } 199 200 static __inline uint32_t 201 mfrtcl(void) 202 { 203 uint32_t rtcl; 204 205 asm volatile ("mfrtcl %0" : "=r"(rtcl)); 206 return rtcl; 207 } 208 209 static __inline void 210 mfrtc(uint32_t *rtcp) 211 { 212 uint32_t tmp; 213 214 asm volatile ( 215 "1: mfrtcu %0 \n" 216 " mfrtcl %1 \n" 217 " mfrtcu %2 \n" 218 " cmplw %0,%2 \n" 219 " bne- 1b" 220 : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp)); 221 } 222 223 static __inline uint32_t 224 mfpvr(void) 225 { 226 uint32_t pvr; 227 228 asm volatile ("mfpvr %0" : "=r"(pvr)); 229 return (pvr); 230 } 231 232 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 233 #define CLKF_BASEPRI(frame) ((frame)->pri == 0) 234 #define CLKF_PC(frame) ((frame)->srr0) 235 #define CLKF_INTR(frame) ((frame)->depth > 0) 236 237 #define LWP_PC(l) (trapframe(l)->srr0) 238 239 #define cpu_swapout(p) 240 #define cpu_wait(p) 241 #define cpu_proc_fork(p1, p2) 242 243 extern int powersave; 244 extern int cpu_timebase; 245 extern int cpu_printfataltraps; 246 extern char cpu_model[]; 247 248 struct cpu_info *cpu_attach_common(struct device *, int); 249 void cpu_setup(struct device *, struct cpu_info *); 250 void cpu_identify(char *, size_t); 251 void delay (unsigned int); 252 void cpu_probe_cache(void); 253 void dcache_flush_page(vaddr_t); 254 void icache_flush_page(vaddr_t); 255 void dcache_flush(vaddr_t, vsize_t); 256 void icache_flush(vaddr_t, vsize_t); 257 258 #define DELAY(n) delay(n) 259 260 #define need_resched(ci) (ci->ci_want_resched = 1, ci->ci_astpending = 1) 261 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, curcpu()->ci_astpending = 1) 262 #define signotify(p) (curcpu()->ci_astpending = 1) 263 264 #ifdef PPC_OEA 265 void oea_init(void (*)(void)); 266 void oea_startup(const char *); 267 void oea_dumpsys(void); 268 void oea_install_extint(void (*)(void)); 269 void *mapiodev(paddr_t, psize_t); 270 paddr_t kvtop(caddr_t); 271 void softnet(int); 272 273 extern paddr_t msgbuf_paddr; 274 extern int cpu_altivec; 275 #endif 276 277 #endif /* _KERNEL */ 278 279 #if defined(_KERNEL) || defined(_STANDALONE) 280 #if !defined(CACHELINESIZE) 281 #define CACHELINESIZE 32 282 #endif 283 #endif 284 285 void __syncicache(void *, size_t); 286 287 /* 288 * CTL_MACHDEP definitions. 289 */ 290 #define CPU_CACHELINE 1 291 #define CPU_TIMEBASE 2 292 #define CPU_CPUTEMP 3 293 #define CPU_PRINTFATALTRAPS 4 294 #define CPU_CACHEINFO 5 295 #define CPU_ALTIVEC 6 296 #define CPU_MODEL 7 297 #define CPU_POWERSAVE 8 298 #define CPU_MAXID 9 299 300 #define CTL_MACHDEP_NAMES { \ 301 { 0, 0 }, \ 302 { "cachelinesize", CTLTYPE_INT }, \ 303 { "timebase", CTLTYPE_INT }, \ 304 { "cputempature", CTLTYPE_INT }, \ 305 { "printfataltraps", CTLTYPE_INT }, \ 306 { "cacheinfo", CTLTYPE_STRUCT }, \ 307 { "altivec", CTLTYPE_INT }, \ 308 { "model", CTLTYPE_STRING }, \ 309 { "powersave", CTLTYPE_INT }, \ 310 } 311 312 #endif /* _POWERPC_CPU_H_ */ 313