xref: /netbsd-src/sys/arch/powerpc/include/cpu.h (revision 76dfffe33547c37f8bdd446e3e4ab0f3c16cea4b)
1 /*	$NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $	*/
2 
3 /*
4  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5  * Copyright (C) 1995, 1996 TooLs GmbH.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by TooLs GmbH.
19  * 4. The name of TooLs GmbH may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 #ifndef	_MACHINE_CPU_H_
34 #define	_MACHINE_CPU_H_
35 
36 #include <machine/frame.h>
37 
38 struct machvec {
39 	void (*splx) __P((int));
40 	void (*irq_establish) __P((int, int, void (*)(void *), void *));
41 };
42 extern struct machvec machine_interface;
43 
44 #include <machine/psl.h>
45 
46 #define	irq_establish(irq, level, handler, arg)	\
47 	((*machine_interface.irq_establish)((irq), (level), (handler), (arg)))
48 
49 #define	CLKF_USERMODE(frame)	(((frame)->srr1 & PSL_PR) != 0)
50 #define	CLKF_BASEPRI(frame)	((frame)->pri == 0)
51 #define	CLKF_PC(frame)		((frame)->srr0)
52 #define	CLKF_INTR(frame)	((frame)->depth != 0)
53 
54 #define	cpu_swapout(p)
55 #define cpu_wait(p)
56 
57 extern void delay __P((unsigned));
58 #define	DELAY(n)		delay(n)
59 
60 extern volatile int want_resched;
61 extern volatile int astpending;
62 
63 #define	need_resched()		(want_resched = 1, astpending = 1)
64 #define	need_proftick(p)	((p)->p_flag |= P_OWEUPC, astpending = 1)
65 #define	signotify(p)		(astpending = 1)
66 
67 #define	CACHELINESIZE	32			/* For now		XXX */
68 
69 extern __inline void
70 syncicache(from, len)
71 	void *from;
72 	int len;
73 {
74 	int l = len;
75 	void *p = from;
76 
77 	do {
78 		asm volatile ("dcbst 0,%0" :: "r"(p));
79 		p += CACHELINESIZE;
80 	} while ((l -= CACHELINESIZE) > 0);
81 	asm volatile ("sync");
82 	do {
83 		asm volatile ("icbi 0,%0" :: "r"(from));
84 		from += CACHELINESIZE;
85 	} while ((len -= CACHELINESIZE) > 0);
86 	asm volatile ("isync");
87 }
88 
89 extern char *bootpath;
90 
91 #endif	/* _MACHINE_CPU_H_ */
92