1 /* $NetBSD: cpu.h,v 1.42 2004/09/22 11:32:03 yamt Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #ifdef _KERNEL 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #include <machine/frame.h> 53 #include <machine/psl.h> 54 #include <machine/intr.h> 55 #include <sys/device.h> 56 57 #include <sys/cpu_data.h> 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct device *ci_dev; /* device of corresponding cpu */ 62 struct lwp *ci_curlwp; /* current owner of the processor */ 63 64 struct pcb *ci_curpcb; 65 struct pmap *ci_curpm; 66 struct lwp *ci_fpulwp; 67 struct lwp *ci_veclwp; 68 struct pcb *ci_idle_pcb; /* PA of our idle pcb */ 69 int ci_cpuid; 70 71 volatile int ci_astpending; 72 int ci_want_resched; 73 volatile u_long ci_lasttb; 74 volatile int ci_tickspending; 75 int ci_cpl; 76 int ci_iactive; 77 int ci_ipending; 78 int ci_intrdepth; 79 char *ci_intstk; 80 #define CPUSAVE_LEN 8 81 register_t ci_tempsave[CPUSAVE_LEN]; 82 register_t ci_ddbsave[CPUSAVE_LEN]; 83 register_t ci_ipkdbsave[CPUSAVE_LEN]; 84 #define CPUSAVE_R28 0 /* where r28 gets saved */ 85 #define CPUSAVE_R29 1 /* where r29 gets saved */ 86 #define CPUSAVE_R30 2 /* where r30 gets saved */ 87 #define CPUSAVE_R31 3 /* where r31 gets saved */ 88 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 89 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 90 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 91 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 92 #define DISISAVE_LEN 4 93 register_t ci_disisave[DISISAVE_LEN]; 94 struct cache_info ci_ci; 95 void *ci_sysmon_cookie; 96 struct evcnt ci_ev_clock; /* clock intrs */ 97 struct evcnt ci_ev_softclock; /* softclock intrs */ 98 struct evcnt ci_ev_softnet; /* softnet intrs */ 99 struct evcnt ci_ev_softserial; /* softserial intrs */ 100 struct evcnt ci_ev_traps; /* calls to trap() */ 101 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 102 struct evcnt ci_ev_udsi; /* user DSI traps */ 103 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 104 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 105 struct evcnt ci_ev_isi; /* user ISI traps */ 106 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 107 struct evcnt ci_ev_pgm; /* user PGM traps */ 108 struct evcnt ci_ev_fpu; /* FPU traps */ 109 struct evcnt ci_ev_fpusw; /* FPU context switch */ 110 struct evcnt ci_ev_ali; /* Alignment traps */ 111 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 112 struct evcnt ci_ev_scalls; /* system call traps */ 113 struct evcnt ci_ev_vec; /* Altivec traps */ 114 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 115 struct evcnt ci_ev_umchk; /* user MCHK events */ 116 }; 117 118 #ifdef MULTIPROCESSOR 119 static __inline int 120 cpu_number(void) 121 { 122 int pir; 123 124 __asm ("mfspr %0,1023" : "=r"(pir)); 125 return pir; 126 } 127 128 void cpu_boot_secondary_processors(void); 129 130 131 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 132 #define CPU_INFO_ITERATOR int 133 #define CPU_INFO_FOREACH(cii, ci) \ 134 cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++ 135 136 #else 137 138 #define cpu_number() 0 139 140 #define CPU_INFO_ITERATOR int 141 #define CPU_INFO_FOREACH(cii, ci) \ 142 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 143 144 #endif /* MULTIPROCESSOR */ 145 146 extern struct cpu_info cpu_info[]; 147 148 static __inline struct cpu_info * 149 curcpu(void) 150 { 151 struct cpu_info *ci; 152 153 __asm __volatile ("mfsprg %0,0" : "=r"(ci)); 154 return ci; 155 } 156 157 #define curlwp (curcpu()->ci_curlwp) 158 #define curpcb (curcpu()->ci_curpcb) 159 #define curpm (curcpu()->ci_curpm) 160 161 static __inline register_t 162 mfmsr(void) 163 { 164 register_t msr; 165 166 __asm __volatile ("mfmsr %0" : "=r"(msr)); 167 return msr; 168 } 169 170 static __inline void 171 mtmsr(register_t msr) 172 { 173 174 __asm __volatile ("mtmsr %0" : : "r"(msr)); 175 } 176 177 static __inline uint32_t 178 mftbl(void) 179 { 180 uint32_t tbl; 181 182 __asm __volatile ( 183 #ifdef PPC_IBM403 184 " mftblo %0 \n" 185 #else 186 " mftbl %0 \n" 187 #endif 188 : "=r" (tbl)); 189 190 return tbl; 191 } 192 193 static __inline uint64_t 194 mftb(void) 195 { 196 uint64_t tb; 197 198 #ifdef _LP64 199 __asm __volatile ("mftb %0" : "=r"(tb)); 200 #else 201 int tmp; 202 203 __asm __volatile ( 204 #ifdef PPC_IBM403 205 "1: mftbhi %0 \n" 206 " mftblo %0+1 \n" 207 " mftbhi %1 \n" 208 #else 209 "1: mftbu %0 \n" 210 " mftb %0+1 \n" 211 " mftbu %1 \n" 212 #endif 213 " cmplw %0,%1 \n" 214 " bne- 1b \n" 215 : "=r" (tb), "=r"(tmp) :: "cr0"); 216 #endif 217 218 return tb; 219 } 220 221 static __inline uint32_t 222 mfrtcl(void) 223 { 224 uint32_t rtcl; 225 226 __asm __volatile ("mfrtcl %0" : "=r"(rtcl)); 227 return rtcl; 228 } 229 230 static __inline void 231 mfrtc(uint32_t *rtcp) 232 { 233 uint32_t tmp; 234 235 __asm __volatile ( 236 "1: mfrtcu %0 \n" 237 " mfrtcl %1 \n" 238 " mfrtcu %2 \n" 239 " cmplw %0,%2 \n" 240 " bne- 1b" 241 : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0"); 242 } 243 244 static __inline uint32_t 245 mfpvr(void) 246 { 247 uint32_t pvr; 248 249 __asm __volatile ("mfpvr %0" : "=r"(pvr)); 250 return (pvr); 251 } 252 253 /* 254 * CLKF_BASEPRI is dependent on the underlying interrupt code 255 * and can not be defined here. It should be defined in 256 * <machine/intr.h> 257 */ 258 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 259 #define CLKF_PC(frame) ((frame)->srr0) 260 #define CLKF_INTR(frame) ((frame)->depth > 0) 261 262 #define LWP_PC(l) (trapframe(l)->srr0) 263 264 #define cpu_swapout(p) 265 #define cpu_proc_fork(p1, p2) 266 267 extern int powersave; 268 extern int cpu_timebase; 269 extern int cpu_printfataltraps; 270 extern char cpu_model[]; 271 272 struct cpu_info *cpu_attach_common(struct device *, int); 273 void cpu_setup(struct device *, struct cpu_info *); 274 void cpu_identify(char *, size_t); 275 void delay (unsigned int); 276 void cpu_probe_cache(void); 277 void dcache_flush_page(vaddr_t); 278 void icache_flush_page(vaddr_t); 279 void dcache_flush(vaddr_t, vsize_t); 280 void icache_flush(vaddr_t, vsize_t); 281 void *mapiodev(paddr_t, psize_t); 282 283 #define DELAY(n) delay(n) 284 285 #define need_resched(ci) (ci->ci_want_resched = 1, ci->ci_astpending = 1) 286 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, curcpu()->ci_astpending = 1) 287 #define signotify(p) (curcpu()->ci_astpending = 1) 288 289 #ifdef PPC_OEA 290 void oea_init(void (*)(void)); 291 void oea_startup(const char *); 292 void oea_dumpsys(void); 293 void oea_install_extint(void (*)(void)); 294 paddr_t kvtop(caddr_t); 295 void softnet(int); 296 297 extern paddr_t msgbuf_paddr; 298 extern int cpu_altivec; 299 #endif 300 301 #endif /* _KERNEL */ 302 303 #if defined(_KERNEL) || defined(_STANDALONE) 304 #if !defined(CACHELINESIZE) 305 #ifdef PPC_IBM403 306 #define CACHELINESIZE 16 307 #else 308 #define CACHELINESIZE 32 309 #endif 310 #endif 311 #endif 312 313 void __syncicache(void *, size_t); 314 315 /* 316 * CTL_MACHDEP definitions. 317 */ 318 #define CPU_CACHELINE 1 319 #define CPU_TIMEBASE 2 320 #define CPU_CPUTEMP 3 321 #define CPU_PRINTFATALTRAPS 4 322 #define CPU_CACHEINFO 5 323 #define CPU_ALTIVEC 6 324 #define CPU_MODEL 7 325 #define CPU_POWERSAVE 8 326 #define CPU_MAXID 9 327 328 #define CTL_MACHDEP_NAMES { \ 329 { 0, 0 }, \ 330 { "cachelinesize", CTLTYPE_INT }, \ 331 { "timebase", CTLTYPE_INT }, \ 332 { "cputempature", CTLTYPE_INT }, \ 333 { "printfataltraps", CTLTYPE_INT }, \ 334 { "cacheinfo", CTLTYPE_STRUCT }, \ 335 { "altivec", CTLTYPE_INT }, \ 336 { "model", CTLTYPE_STRING }, \ 337 { "powersave", CTLTYPE_INT }, \ 338 } 339 340 #endif /* _POWERPC_CPU_H_ */ 341