xref: /netbsd-src/sys/arch/powerpc/include/cpu.h (revision 220b5c059a84c51ea44107ea8951a57ffaecdc8c)
1 /*	$NetBSD: cpu.h,v 1.11 2001/12/05 05:02:10 chs Exp $	*/
2 
3 /*
4  * Copyright (C) 1999 Wolfgang Solfrank.
5  * Copyright (C) 1999 TooLs GmbH.
6  * Copyright (C) 1995-1997 Wolfgang Solfrank.
7  * Copyright (C) 1995-1997 TooLs GmbH.
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *	This product includes software developed by TooLs GmbH.
21  * 4. The name of TooLs GmbH may not be used to endorse or promote products
22  *    derived from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
30  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 #ifndef	_POWERPC_CPU_H_
36 #define	_POWERPC_CPU_H_
37 
38 #if defined(_KERNEL_OPT)
39 #include "opt_lockdebug.h"
40 #include "opt_multiprocessor.h"
41 #endif
42 
43 #include <sys/device.h>
44 #include <machine/frame.h>
45 #include <machine/psl.h>
46 #include <machine/intr.h>
47 
48 #ifdef _KERNEL
49 #include <sys/sched.h>
50 struct cpu_info {
51 	struct schedstate_percpu ci_schedstate; /* scheduler state */
52 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
53 	u_long ci_spin_locks;		/* # of spin locks held */
54 	u_long ci_simple_locks;		/* # of simple locks held */
55 #endif
56 	struct device *ci_dev;		/* device of corresponding cpu */
57 	struct proc *ci_curproc;	/* current owner of the processor */
58 
59 	struct pcb *ci_curpcb;
60 	struct pmap *ci_curpm;
61 	struct proc *ci_fpuproc;
62 	struct pcb *ci_idle_pcb;	/* PA of our idle pcb */
63 	int ci_cpuid;
64 
65 	int ci_astpending;
66 	int ci_want_resched;
67 	u_long ci_lasttb;
68 	int ci_tickspending;
69 	int ci_cpl;
70 	int ci_ipending;
71 	int ci_intrdepth;
72 	char *ci_intstk;
73 	char *ci_spillstk;
74 	int ci_tempsave[8];
75 	int ci_ddbsave[8];
76 	int ci_ipkdbsave[8];
77 	int ci_disisave[4];
78 	struct evcnt ci_ev_traps;	/* calls to trap() */
79 	struct evcnt ci_ev_kdsi;	/* kernel DSI traps */
80 	struct evcnt ci_ev_udsi;	/* user DSI traps */
81 	struct evcnt ci_ev_udsi_fatal;	/* user DSI trap failures */
82 	struct evcnt ci_ev_isi;		/* user ISI traps */
83 	struct evcnt ci_ev_isi_fatal;	/* user ISI trap failures */
84 	struct evcnt ci_ev_pgm;		/* user PGM traps */
85 	struct evcnt ci_ev_fpu;		/* FPU traps */
86 	struct evcnt ci_ev_fpusw;	/* FPU context switch */
87 	struct evcnt ci_ev_ali;		/* Alignment traps */
88 	struct evcnt ci_ev_ali_fatal;	/* Alignment fatal trap */
89 	struct evcnt ci_ev_scalls;	/* system call traps */
90 	struct evcnt ci_ev_vec;		/* Altivec traps */
91 	struct evcnt ci_ev_vecsw;	/* Altivec context switches */
92 };
93 
94 #ifdef MULTIPROCESSOR
95 static __inline int
96 cpu_number(void)
97 {
98 	int pir;
99 
100 	asm ("mfspr %0,1023" : "=r"(pir));
101 	return pir;
102 }
103 
104 static __inline struct cpu_info *
105 curcpu(void)
106 {
107 	struct cpu_info *ci;
108 
109 	asm volatile ("mfsprg %0,0" : "=r"(ci));
110 	return ci;
111 }
112 
113 void	cpu_boot_secondary_processors(void);
114 
115 extern struct cpu_info cpu_info[];
116 
117 #define CPU_IS_PRIMARY(ci)	((ci)->ci_cpuid == 0)
118 #define curproc			curcpu()->ci_curproc
119 #define fpuproc			curcpu()->ci_fpuproc
120 #define curpcb			curcpu()->ci_curpcb
121 #define curpm			curcpu()->ci_curpm
122 #define want_resched		curcpu()->ci_want_resched
123 #define astpending		curcpu()->ci_astpending
124 #define	intr_depth		curcpu()->ci_intrdepth
125 
126 #else
127 extern struct cpu_info cpu_info_store;
128 extern volatile int want_resched;
129 extern volatile int astpending;
130 extern volatile int intr_depth;
131 
132 #define curcpu()		(&cpu_info_store)
133 #define cpu_number()		0
134 
135 #endif /* MULTIPROCESSOR */
136 
137 #define	CLKF_USERMODE(frame)	(((frame)->srr1 & PSL_PR) != 0)
138 #define	CLKF_BASEPRI(frame)	((frame)->pri == 0)
139 #define	CLKF_PC(frame)		((frame)->srr0)
140 #define	CLKF_INTR(frame)	((frame)->depth > 0)
141 
142 #define	PROC_PC(p)		(trapframe(p)->srr0)
143 
144 #define	cpu_swapout(p)
145 #define cpu_wait(p)
146 
147 extern int powersave;
148 extern int cpu_timebase;
149 extern int cpu_printfataltraps;
150 
151 extern struct cpu_info *cpu_attach_common(struct device *, int);
152 extern void cpu_identify(char *, size_t);
153 extern void delay (unsigned int);
154 #define	DELAY(n)		delay(n)
155 
156 #define	need_resched(ci)	(want_resched = 1, astpending = 1)
157 #define	need_proftick(p)	((p)->p_flag |= P_OWEUPC, astpending = 1)
158 #define	signotify(p)		(astpending = 1)
159 
160 #endif /* _KERNEL */
161 
162 #if defined(_KERNEL) || defined(_STANDALONE)
163 #if !defined(CACHELINESIZE)
164 #define	CACHELINESIZE	32
165 #endif
166 #endif
167 
168 void __syncicache(void *, int);
169 
170 /*
171  * CTL_MACHDEP definitions.
172  */
173 #define	CPU_CACHELINE		1
174 #define	CPU_TIMEBASE		2
175 #define	CPU_CPUTEMP		3
176 #define	CPU_PRINTFATALTRAPS	4
177 #define	CPU_MAXID		5
178 
179 #define	CTL_MACHDEP_NAMES { \
180 	{ 0, 0 }, \
181 	{ "cachelinesize", CTLTYPE_INT }, \
182 	{ "timebase", CTLTYPE_INT }, \
183 	{ "cputempature", CTLTYPE_INT }, \
184 	{ "printfataltraps", CTLTYPE_INT }, \
185 }
186 
187 #endif	/* _POWERPC_CPU_H_ */
188