1 /* $NetBSD: if_emac.c,v 1.15 2003/07/15 02:54:44 lukem Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.15 2003/07/15 02:54:44 lukem Exp $"); 40 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 50 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #if NBPFILTER > 0 58 #include <net/bpf.h> 59 #endif 60 61 #include <powerpc/ibm4xx/dev/opbvar.h> 62 63 #include <powerpc/ibm4xx/ibm405gp.h> 64 #include <powerpc/ibm4xx/mal405gp.h> 65 #include <powerpc/ibm4xx/dcr405gp.h> 66 #include <powerpc/ibm4xx/dev/emacreg.h> 67 #include <powerpc/ibm4xx/dev/if_emacreg.h> 68 69 #include <dev/mii/miivar.h> 70 71 /* 72 * Transmit descriptor list size. There are two Tx channels, each with 73 * up to 256 hardware descriptors available. We currently use one Tx 74 * channel. We tell the upper layers that they can queue a lot of 75 * packets, and we go ahead and manage up to 64 of them at a time. We 76 * allow up to 16 DMA segments per packet. 77 */ 78 #define EMAC_NTXSEGS 16 79 #define EMAC_TXQUEUELEN 64 80 #define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 81 #define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 82 #define EMAC_NTXDESC 256 83 #define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 84 #define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 85 #define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 86 87 /* 88 * Receive descriptor list size. There is one Rx channel with up to 256 89 * hardware descriptors available. We allocate 64 receive descriptors, 90 * each with a 2k buffer (MCLBYTES). 91 */ 92 #define EMAC_NRXDESC 64 93 #define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 94 #define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 95 #define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 96 97 /* 98 * Transmit/receive descriptors that are DMA'd to the EMAC. 99 */ 100 struct emac_control_data { 101 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 102 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 103 }; 104 105 #define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 106 #define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 107 #define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 108 109 /* 110 * Software state for transmit jobs. 111 */ 112 struct emac_txsoft { 113 struct mbuf *txs_mbuf; /* head of mbuf chain */ 114 bus_dmamap_t txs_dmamap; /* our DMA map */ 115 int txs_firstdesc; /* first descriptor in packet */ 116 int txs_lastdesc; /* last descriptor in packet */ 117 int txs_ndesc; /* # of descriptors used */ 118 }; 119 120 /* 121 * Software state for receive descriptors. 122 */ 123 struct emac_rxsoft { 124 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 125 bus_dmamap_t rxs_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct emac_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 void *sc_powerhook; /* power management hook */ 139 140 struct mii_data sc_mii; /* MII/media information */ 141 struct callout sc_callout; /* tick callout */ 142 143 u_int32_t sc_mr1; /* copy of Mode Register 1 */ 144 145 bus_dmamap_t sc_cddmamap; /* control data dma map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* Software state for transmit/receive descriptors. */ 149 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 150 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 151 152 /* Control data structures. */ 153 struct emac_control_data *sc_control_data; 154 #define sc_txdescs sc_control_data->ecd_txdesc 155 #define sc_rxdescs sc_control_data->ecd_rxdesc 156 157 #ifdef EMAC_EVENT_COUNTERS 158 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 159 struct evcnt sc_ev_txintr; /* Tx interrupts */ 160 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 161 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 162 struct evcnt sc_ev_wol; /* Wake-On-Lan interrupts */ 163 struct evcnt sc_ev_serr; /* MAL system error interrupts */ 164 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 165 166 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 167 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 168 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 169 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 170 struct evcnt sc_ev_tu; /* Tx underrun */ 171 #endif /* EMAC_EVENT_COUNTERS */ 172 173 int sc_txfree; /* number of free Tx descriptors */ 174 int sc_txnext; /* next ready Tx descriptor */ 175 176 int sc_txsfree; /* number of free Tx jobs */ 177 int sc_txsnext; /* next ready Tx job */ 178 int sc_txsdirty; /* dirty Tx jobs */ 179 180 int sc_rxptr; /* next ready RX descriptor/descsoft */ 181 }; 182 183 #ifdef EMAC_EVENT_COUNTERS 184 #define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 185 #else 186 #define EMAC_EVCNT_INCR(ev) /* nothing */ 187 #endif 188 189 #define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 190 #define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 191 192 #define EMAC_CDTXSYNC(sc, x, n, ops) \ 193 do { \ 194 int __x, __n; \ 195 \ 196 __x = (x); \ 197 __n = (n); \ 198 \ 199 /* If it will wrap around, sync to the end of the ring. */ \ 200 if ((__x + __n) > EMAC_NTXDESC) { \ 201 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 202 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 203 (EMAC_NTXDESC - __x), (ops)); \ 204 __n -= (EMAC_NTXDESC - __x); \ 205 __x = 0; \ 206 } \ 207 \ 208 /* Now sync whatever is left. */ \ 209 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 210 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 211 } while (/*CONSTCOND*/0) 212 213 #define EMAC_CDRXSYNC(sc, x, ops) \ 214 do { \ 215 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 216 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 217 } while (/*CONSTCOND*/0) 218 219 #define EMAC_INIT_RXDESC(sc, x) \ 220 do { \ 221 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 222 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 223 struct mbuf *__m = __rxs->rxs_mbuf; \ 224 \ 225 /* \ 226 * Note: We scoot the packet forward 2 bytes in the buffer \ 227 * so that the payload after the Ethernet header is aligned \ 228 * to a 4-byte boundary. \ 229 */ \ 230 __m->m_data = __m->m_ext.ext_buf + 2; \ 231 \ 232 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 233 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 234 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 235 /* Set wrap on last descriptor. */ \ 236 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 237 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 238 } while (/*CONSTCOND*/0) 239 240 #define EMAC_WRITE(sc, reg, val) \ 241 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 242 #define EMAC_READ(sc, reg) \ 243 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 244 245 static int emac_match(struct device *, struct cfdata *, void *); 246 static void emac_attach(struct device *, struct device *, void *); 247 248 static int emac_add_rxbuf(struct emac_softc *, int); 249 static int emac_init(struct ifnet *); 250 static int emac_ioctl(struct ifnet *, u_long, caddr_t); 251 static void emac_reset(struct emac_softc *); 252 static void emac_rxdrain(struct emac_softc *); 253 static int emac_txreap(struct emac_softc *); 254 static void emac_shutdown(void *); 255 static void emac_start(struct ifnet *); 256 static void emac_stop(struct ifnet *, int); 257 static void emac_watchdog(struct ifnet *); 258 259 static int emac_wol_intr(void *); 260 static int emac_serr_intr(void *); 261 static int emac_txeob_intr(void *); 262 static int emac_rxeob_intr(void *); 263 static int emac_txde_intr(void *); 264 static int emac_rxde_intr(void *); 265 static int emac_intr(void *); 266 267 static int emac_mediachange(struct ifnet *); 268 static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 269 static int emac_mii_readreg(struct device *, int, int); 270 static void emac_mii_statchg(struct device *); 271 static void emac_mii_tick(void *); 272 static uint32_t emac_mii_wait(struct emac_softc *); 273 static void emac_mii_writereg(struct device *, int, int, int); 274 275 int emac_copy_small = 0; 276 277 CFATTACH_DECL(emac, sizeof(struct emac_softc), 278 emac_match, emac_attach, NULL, NULL); 279 280 static int 281 emac_match(struct device *parent, struct cfdata *cf, void *aux) 282 { 283 struct opb_attach_args *oaa = aux; 284 285 /* match only on-chip ethernet devices */ 286 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 287 return (1); 288 289 return (0); 290 } 291 292 static void 293 emac_attach(struct device *parent, struct device *self, void *aux) 294 { 295 struct opb_attach_args *oaa = aux; 296 struct emac_softc *sc = (struct emac_softc *)self; 297 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 298 struct mii_data *mii = &sc->sc_mii; 299 bus_dma_segment_t seg; 300 int error, i, nseg; 301 uint8_t enaddr[ETHER_ADDR_LEN]; 302 303 sc->sc_st = oaa->opb_bt; 304 sc->sc_sh = oaa->opb_addr; 305 sc->sc_dmat = oaa->opb_dmat; 306 307 printf(": 405GP EMAC\n"); 308 309 /* 310 * Set up Mode Register 1 - set receive and transmit FIFOs to maximum 311 * size, allow transmit of multiple packets (only channel 0 is used). 312 * 313 * XXX: Allow pause packets?? 314 */ 315 sc->sc_mr1 = MR1_RFS_4KB | MR1_TFS_2KB | MR1_TR0_MULTIPLE; 316 317 intr_establish(oaa->opb_irq , IST_LEVEL, IPL_NET, emac_wol_intr, sc); 318 intr_establish(oaa->opb_irq + 1, IST_LEVEL, IPL_NET, emac_serr_intr, sc); 319 intr_establish(oaa->opb_irq + 2, IST_LEVEL, IPL_NET, emac_txeob_intr, sc); 320 intr_establish(oaa->opb_irq + 3, IST_LEVEL, IPL_NET, emac_rxeob_intr, sc); 321 intr_establish(oaa->opb_irq + 4, IST_LEVEL, IPL_NET, emac_txde_intr, sc); 322 intr_establish(oaa->opb_irq + 5, IST_LEVEL, IPL_NET, emac_rxde_intr, sc); 323 intr_establish(oaa->opb_irq + 6, IST_LEVEL, IPL_NET, emac_intr, sc); 324 printf("%s: interrupting at irqs %d .. %d\n", sc->sc_dev.dv_xname, 325 oaa->opb_irq, oaa->opb_irq + 6); 326 327 /* 328 * Allocate the control data structures, and create and load the 329 * DMA map for it. 330 */ 331 if ((error = bus_dmamem_alloc(sc->sc_dmat, 332 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 333 printf("%s: unable to allocate control data, error = %d\n", 334 sc->sc_dev.dv_xname, error); 335 goto fail_0; 336 } 337 338 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 339 sizeof(struct emac_control_data), (caddr_t *)&sc->sc_control_data, 340 BUS_DMA_COHERENT)) != 0) { 341 printf("%s: unable to map control data, error = %d\n", 342 sc->sc_dev.dv_xname, error); 343 goto fail_1; 344 } 345 346 if ((error = bus_dmamap_create(sc->sc_dmat, 347 sizeof(struct emac_control_data), 1, 348 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 349 printf("%s: unable to create control data DMA map, " 350 "error = %d\n", sc->sc_dev.dv_xname, error); 351 goto fail_2; 352 } 353 354 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 355 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 356 0)) != 0) { 357 printf("%s: unable to load control data DMA map, error = %d\n", 358 sc->sc_dev.dv_xname, error); 359 goto fail_3; 360 } 361 362 /* 363 * Create the transmit buffer DMA maps. 364 */ 365 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 366 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 367 EMAC_NTXSEGS, MCLBYTES, 0, 0, 368 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 369 printf("%s: unable to create tx DMA map %d, " 370 "error = %d\n", sc->sc_dev.dv_xname, i, error); 371 goto fail_4; 372 } 373 } 374 375 /* 376 * Create the receive buffer DMA maps. 377 */ 378 for (i = 0; i < EMAC_NRXDESC; i++) { 379 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 380 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 381 printf("%s: unable to create rx DMA map %d, " 382 "error = %d\n", sc->sc_dev.dv_xname, i, error); 383 goto fail_5; 384 } 385 sc->sc_rxsoft[i].rxs_mbuf = NULL; 386 } 387 388 /* 389 * Reset the chip to a known state. 390 */ 391 emac_reset(sc); 392 393 /* Fetch the Ethernet address. */ 394 if (prop_get(dev_propdb, &sc->sc_dev, "mac-addr", enaddr, 395 sizeof(enaddr), NULL) != sizeof(enaddr)) { 396 printf("%s: unable to get mac-addr property\n", 397 sc->sc_dev.dv_xname); 398 return; 399 } 400 401 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 402 ether_sprintf(enaddr)); 403 404 /* 405 * Initialise the media structures. 406 */ 407 mii->mii_ifp = ifp; 408 mii->mii_readreg = emac_mii_readreg; 409 mii->mii_writereg = emac_mii_writereg; 410 mii->mii_statchg = emac_mii_statchg; 411 412 ifmedia_init(&mii->mii_media, 0, emac_mediachange, 413 emac_mediastatus); 414 mii_attach(&sc->sc_dev, mii, 0xffffffff, 415 MII_PHY_ANY, MII_OFFSET_ANY, 0); 416 if (LIST_FIRST(&mii->mii_phys) == NULL) { 417 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 418 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 419 } else 420 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 421 422 ifp = &sc->sc_ethercom.ec_if; 423 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 424 ifp->if_softc = sc; 425 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 426 ifp->if_ioctl = emac_ioctl; 427 ifp->if_start = emac_start; 428 ifp->if_watchdog = emac_watchdog; 429 ifp->if_init = emac_init; 430 ifp->if_stop = emac_stop; 431 IFQ_SET_READY(&ifp->if_snd); 432 433 /* 434 * We can support 802.1Q VLAN-sized frames. 435 */ 436 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 437 438 /* 439 * Attach the interface. 440 */ 441 if_attach(ifp); 442 ether_ifattach(ifp, enaddr); 443 444 #ifdef EMAC_EVENT_COUNTERS 445 /* 446 * Attach the event counters. 447 */ 448 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 449 NULL, sc->sc_dev.dv_xname, "rxintr"); 450 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 451 NULL, sc->sc_dev.dv_xname, "txintr"); 452 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 453 NULL, sc->sc_dev.dv_xname, "rxde"); 454 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 455 NULL, sc->sc_dev.dv_xname, "txde"); 456 evcnt_attach_dynamic(&sc->sc_ev_wol, EVCNT_TYPE_INTR, 457 NULL, sc->sc_dev.dv_xname, "wol"); 458 evcnt_attach_dynamic(&sc->sc_ev_serr, EVCNT_TYPE_INTR, 459 NULL, sc->sc_dev.dv_xname, "serr"); 460 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 461 NULL, sc->sc_dev.dv_xname, "intr"); 462 463 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 464 NULL, sc->sc_dev.dv_xname, "txreap"); 465 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 466 NULL, sc->sc_dev.dv_xname, "txsstall"); 467 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 468 NULL, sc->sc_dev.dv_xname, "txdstall"); 469 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 470 NULL, sc->sc_dev.dv_xname, "txdrop"); 471 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 472 NULL, sc->sc_dev.dv_xname, "tu"); 473 #endif /* EMAC_EVENT_COUNTERS */ 474 475 /* 476 * Make sure the interface is shutdown during reboot. 477 */ 478 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 479 if (sc->sc_sdhook == NULL) 480 printf("%s: WARNING: unable to establish shutdown hook\n", 481 sc->sc_dev.dv_xname); 482 483 return; 484 485 /* 486 * Free any resources we've allocated during the failed attach 487 * attempt. Do this in reverse order and fall through. 488 */ 489 fail_5: 490 for (i = 0; i < EMAC_NRXDESC; i++) { 491 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 492 bus_dmamap_destroy(sc->sc_dmat, 493 sc->sc_rxsoft[i].rxs_dmamap); 494 } 495 fail_4: 496 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 497 if (sc->sc_txsoft[i].txs_dmamap != NULL) 498 bus_dmamap_destroy(sc->sc_dmat, 499 sc->sc_txsoft[i].txs_dmamap); 500 } 501 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 502 fail_3: 503 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 504 fail_2: 505 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 506 sizeof(struct emac_control_data)); 507 fail_1: 508 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 509 fail_0: 510 return; 511 } 512 513 /* 514 * Device shutdown routine. 515 */ 516 static void 517 emac_shutdown(void *arg) 518 { 519 struct emac_softc *sc = arg; 520 521 emac_stop(&sc->sc_ethercom.ec_if, 0); 522 } 523 524 /* ifnet interface function */ 525 static void 526 emac_start(struct ifnet *ifp) 527 { 528 struct emac_softc *sc = ifp->if_softc; 529 struct mbuf *m0; 530 struct emac_txsoft *txs; 531 bus_dmamap_t dmamap; 532 int error, firsttx, nexttx, lasttx, ofree, seg; 533 534 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 535 return; 536 537 /* 538 * Remember the previous number of free descriptors. 539 */ 540 ofree = sc->sc_txfree; 541 542 /* 543 * Loop through the send queue, setting up transmit descriptors 544 * until we drain the queue, or use up all available transmit 545 * descriptors. 546 */ 547 for (;;) { 548 /* Grab a packet off the queue. */ 549 IFQ_POLL(&ifp->if_snd, m0); 550 if (m0 == NULL) 551 break; 552 553 /* 554 * Get a work queue entry. Reclaim used Tx descriptors if 555 * we are running low. 556 */ 557 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 558 emac_txreap(sc); 559 if (sc->sc_txsfree == 0) { 560 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 561 break; 562 } 563 } 564 565 txs = &sc->sc_txsoft[sc->sc_txsnext]; 566 dmamap = txs->txs_dmamap; 567 568 /* 569 * Load the DMA map. If this fails, the packet either 570 * didn't fit in the alloted number of segments, or we 571 * were short on resources. In this case, we'll copy 572 * and try again. 573 */ 574 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 575 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 576 if (error) { 577 if (error == EFBIG) { 578 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 579 printf("%s: Tx packet consumes too many " 580 "DMA segments, dropping...\n", 581 sc->sc_dev.dv_xname); 582 IFQ_DEQUEUE(&ifp->if_snd, m0); 583 m_freem(m0); 584 continue; 585 } 586 /* Short on resources, just stop for now. */ 587 break; 588 } 589 590 /* 591 * Ensure we have enough descriptors free to describe 592 * the packet. 593 */ 594 if (dmamap->dm_nsegs > sc->sc_txfree) { 595 /* 596 * Not enough free descriptors to transmit this 597 * packet. We haven't committed anything yet, 598 * so just unload the DMA map, put the packet 599 * back on the queue, and punt. Notify the upper 600 * layer that there are not more slots left. 601 * 602 */ 603 ifp->if_flags |= IFF_OACTIVE; 604 bus_dmamap_unload(sc->sc_dmat, dmamap); 605 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 606 break; 607 } 608 609 IFQ_DEQUEUE(&ifp->if_snd, m0); 610 611 /* 612 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 613 */ 614 615 /* Sync the DMA map. */ 616 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 617 BUS_DMASYNC_PREWRITE); 618 619 /* 620 * Store a pointer to the packet so that we can free it 621 * later. 622 */ 623 txs->txs_mbuf = m0; 624 txs->txs_firstdesc = sc->sc_txnext; 625 txs->txs_ndesc = dmamap->dm_nsegs; 626 627 /* 628 * Initialize the transmit descriptor. 629 */ 630 firsttx = sc->sc_txnext; 631 for (nexttx = sc->sc_txnext, seg = 0; 632 seg < dmamap->dm_nsegs; 633 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 634 /* 635 * If this is the first descriptor we're 636 * enqueueing, don't set the TX_READY bit just 637 * yet. That could cause a race condition. 638 * We'll do it below. 639 */ 640 sc->sc_txdescs[nexttx].md_data = 641 dmamap->dm_segs[seg].ds_addr; 642 sc->sc_txdescs[nexttx].md_data_len = 643 dmamap->dm_segs[seg].ds_len; 644 sc->sc_txdescs[nexttx].md_stat_ctrl = 645 (sc->sc_txdescs[nexttx].md_stat_ctrl & MAL_TX_WRAP) | 646 (nexttx == firsttx ? 0 : MAL_TX_READY) | 647 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 648 lasttx = nexttx; 649 } 650 651 /* Set the LAST bit on the last segment. */ 652 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 653 654 txs->txs_lastdesc = lasttx; 655 656 /* Sync the descriptors we're using. */ 657 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 658 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 659 660 /* 661 * The entire packet chain is set up. Give the 662 * first descriptor to the chip now. 663 */ 664 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 665 EMAC_CDTXSYNC(sc, firsttx, 1, 666 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 667 /* 668 * Tell the EMAC that a new packet is available. 669 */ 670 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0); 671 672 /* Advance the tx pointer. */ 673 sc->sc_txfree -= txs->txs_ndesc; 674 sc->sc_txnext = nexttx; 675 676 sc->sc_txsfree--; 677 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 678 679 #if NBPFILTER > 0 680 /* 681 * Pass the packet to any BPF listeners. 682 */ 683 if (ifp->if_bpf) 684 bpf_mtap(ifp->if_bpf, m0); 685 #endif /* NBPFILTER > 0 */ 686 } 687 688 if (txs == NULL || sc->sc_txfree == 0) { 689 /* No more slots left; notify upper layer. */ 690 ifp->if_flags |= IFF_OACTIVE; 691 } 692 693 if (sc->sc_txfree != ofree) { 694 /* Set a watchdog timer in case the chip flakes out. */ 695 ifp->if_timer = 5; 696 } 697 } 698 699 static int 700 emac_init(struct ifnet *ifp) 701 { 702 struct emac_softc *sc = ifp->if_softc; 703 struct emac_rxsoft *rxs; 704 uint8_t *enaddr = LLADDR(ifp->if_sadl); 705 int error, i; 706 707 error = 0; 708 709 /* Cancel any pending I/O. */ 710 emac_stop(ifp, 0); 711 712 /* Reset the chip to a known state. */ 713 emac_reset(sc); 714 715 /* 716 * Initialise the transmit descriptor ring. 717 */ 718 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 719 /* set wrap on last descriptor */ 720 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 721 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 722 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 723 sc->sc_txfree = EMAC_NTXDESC; 724 sc->sc_txnext = 0; 725 726 /* 727 * Initialise the transmit job descriptors. 728 */ 729 for (i = 0; i < EMAC_TXQUEUELEN; i++) 730 sc->sc_txsoft[i].txs_mbuf = NULL; 731 sc->sc_txsfree = EMAC_TXQUEUELEN; 732 sc->sc_txsnext = 0; 733 sc->sc_txsdirty = 0; 734 735 /* 736 * Initialise the receiver descriptor and receive job 737 * descriptor rings. 738 */ 739 for (i = 0; i < EMAC_NRXDESC; i++) { 740 rxs = &sc->sc_rxsoft[i]; 741 if (rxs->rxs_mbuf == NULL) { 742 if ((error = emac_add_rxbuf(sc, i)) != 0) { 743 printf("%s: unable to allocate or map rx " 744 "buffer %d, error = %d\n", 745 sc->sc_dev.dv_xname, i, error); 746 /* 747 * XXX Should attempt to run with fewer receive 748 * XXX buffers instead of just failing. 749 */ 750 emac_rxdrain(sc); 751 goto out; 752 } 753 } else 754 EMAC_INIT_RXDESC(sc, i); 755 } 756 sc->sc_rxptr = 0; 757 758 /* 759 * Set the current media. 760 */ 761 mii_mediachg(&sc->sc_mii); 762 763 /* 764 * Give the transmit and receive rings to the MAL. 765 */ 766 mtdcr(DCR_MAL0_TXCTP0R, EMAC_CDTXADDR(sc, 0)); 767 mtdcr(DCR_MAL0_RXCTP0R, EMAC_CDRXADDR(sc, 0)); 768 769 /* 770 * Load the MAC address. 771 */ 772 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 773 EMAC_WRITE(sc, EMAC_IALR, 774 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 775 776 /* 777 * Set the receive channel buffer size (in units of 16 bytes). 778 */ 779 #if MCLBYTES > (4096 - 16) /* XXX! */ 780 # error MCLBYTES > max rx channel buffer size 781 #endif 782 mtdcr(DCR_MAL0_RCBS0, MCLBYTES / 16); 783 784 /* Set fifos, media modes. */ 785 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 786 787 /* 788 * Enable Individual and (possibly) Broadcast Address modes, 789 * runt packets, and strip padding. 790 * 791 * XXX: promiscuous mode (and promiscuous multicast mode) need to be 792 * dealt with here! 793 */ 794 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | 795 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 796 797 /* 798 * Set low- and urgent-priority request thresholds. 799 */ 800 EMAC_WRITE(sc, EMAC_TMR1, 801 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 802 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 803 /* 804 * Set Transmit Request Threshold Register. 805 */ 806 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 807 808 /* 809 * Set high and low receive watermarks. 810 */ 811 EMAC_WRITE(sc, EMAC_RWMR, 812 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 813 814 /* 815 * Set frame gap. 816 */ 817 EMAC_WRITE(sc, EMAC_IPGVR, 8); 818 819 /* 820 * Set interrupt status enable bits for EMAC and MAL. 821 */ 822 EMAC_WRITE(sc, EMAC_ISER, 823 ISR_BP | ISR_SE | ISR_ALE | ISR_BFCS | ISR_PTLE | ISR_ORE | ISR_IRE); 824 mtdcr(DCR_MAL0_IER, MAL0_IER_DE | MAL0_IER_NWE | MAL0_IER_TO | 825 MAL0_IER_OPB | MAL0_IER_PLB); 826 827 /* 828 * Enable the transmit and receive channel on the MAL. 829 */ 830 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 831 mtdcr(DCR_MAL0_TXCASR, MAL0_TXCASR_CHAN0); 832 833 /* 834 * Enable the transmit and receive channel on the EMAC. 835 */ 836 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 837 838 /* 839 * Start the one second MII clock. 840 */ 841 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 842 843 /* 844 * ... all done! 845 */ 846 ifp->if_flags |= IFF_RUNNING; 847 ifp->if_flags &= ~IFF_OACTIVE; 848 849 out: 850 if (error) { 851 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 852 ifp->if_timer = 0; 853 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 854 } 855 return (error); 856 } 857 858 static int 859 emac_add_rxbuf(struct emac_softc *sc, int idx) 860 { 861 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 862 struct mbuf *m; 863 int error; 864 865 MGETHDR(m, M_DONTWAIT, MT_DATA); 866 if (m == NULL) 867 return (ENOBUFS); 868 869 MCLGET(m, M_DONTWAIT); 870 if ((m->m_flags & M_EXT) == 0) { 871 m_freem(m); 872 return (ENOBUFS); 873 } 874 875 if (rxs->rxs_mbuf != NULL) 876 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 877 878 rxs->rxs_mbuf = m; 879 880 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 881 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 882 if (error) { 883 printf("%s: can't load rx DMA map %d, error = %d\n", 884 sc->sc_dev.dv_xname, idx, error); 885 panic("emac_add_rxbuf"); /* XXX */ 886 } 887 888 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 889 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 890 891 EMAC_INIT_RXDESC(sc, idx); 892 893 return (0); 894 } 895 896 /* ifnet interface function */ 897 static void 898 emac_watchdog(struct ifnet *ifp) 899 { 900 struct emac_softc *sc = ifp->if_softc; 901 902 /* 903 * Since we're not interrupting every packet, sweep 904 * up before we report an error. 905 */ 906 emac_txreap(sc); 907 908 if (sc->sc_txfree != EMAC_NTXDESC) { 909 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 910 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 911 sc->sc_txnext); 912 ifp->if_oerrors++; 913 914 /* Reset the interface. */ 915 (void)emac_init(ifp); 916 } else if (ifp->if_flags & IFF_DEBUG) 917 printf("%s: recovered from device timeout\n", 918 sc->sc_dev.dv_xname); 919 920 /* try to get more packets going */ 921 emac_start(ifp); 922 } 923 924 static void 925 emac_rxdrain(struct emac_softc *sc) 926 { 927 struct emac_rxsoft *rxs; 928 int i; 929 930 for (i = 0; i < EMAC_NRXDESC; i++) { 931 rxs = &sc->sc_rxsoft[i]; 932 if (rxs->rxs_mbuf != NULL) { 933 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 934 m_freem(rxs->rxs_mbuf); 935 rxs->rxs_mbuf = NULL; 936 } 937 } 938 } 939 940 /* ifnet interface function */ 941 static void 942 emac_stop(struct ifnet *ifp, int disable) 943 { 944 struct emac_softc *sc = ifp->if_softc; 945 struct emac_txsoft *txs; 946 int i; 947 948 /* Stop the one second clock. */ 949 callout_stop(&sc->sc_callout); 950 951 /* Down the MII */ 952 mii_down(&sc->sc_mii); 953 954 /* Disable interrupts. */ 955 #if 0 /* Can't disable MAL interrupts without a reset... */ 956 EMAC_WRITE(sc, EMAC_ISER, 0); 957 #endif 958 mtdcr(DCR_MAL0_IER, 0); 959 960 /* Disable the receive and transmit channels. */ 961 mtdcr(DCR_MAL0_RXCARR, MAL0_RXCARR_CHAN0); 962 mtdcr(DCR_MAL0_TXCARR, MAL0_TXCARR_CHAN0 | MAL0_TXCARR_CHAN1); 963 964 /* Disable the transmit enable and receive MACs. */ 965 EMAC_WRITE(sc, EMAC_MR0, 966 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 967 968 /* Release any queued transmit buffers. */ 969 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 970 txs = &sc->sc_txsoft[i]; 971 if (txs->txs_mbuf != NULL) { 972 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 973 m_freem(txs->txs_mbuf); 974 txs->txs_mbuf = NULL; 975 } 976 } 977 978 if (disable) 979 emac_rxdrain(sc); 980 981 /* 982 * Mark the interface down and cancel the watchdog timer. 983 */ 984 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 985 ifp->if_timer = 0; 986 } 987 988 /* ifnet interface function */ 989 static int 990 emac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 991 { 992 struct emac_softc *sc = ifp->if_softc; 993 struct ifreq *ifr = (struct ifreq *)data; 994 int s, error; 995 996 s = splnet(); 997 998 switch (cmd) { 999 case SIOCSIFMEDIA: 1000 case SIOCGIFMEDIA: 1001 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1002 break; 1003 1004 default: 1005 error = ether_ioctl(ifp, cmd, data); 1006 if (error == ENETRESET) { 1007 /* 1008 * Multicast list has changed; set the hardware filter 1009 * accordingly. 1010 */ 1011 #if 0 1012 error = emac_set_filter(sc); /* XXX not done yet */ 1013 #else 1014 error = emac_init(ifp); 1015 #endif 1016 } 1017 break; 1018 } 1019 1020 /* try to get more packets going */ 1021 emac_start(ifp); 1022 1023 splx(s); 1024 return (error); 1025 } 1026 1027 static void 1028 emac_reset(struct emac_softc *sc) 1029 { 1030 1031 /* reset the MAL */ 1032 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR); 1033 1034 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1035 delay(5); 1036 1037 /* XXX: check if MR0_SRST is clear until a timeout instead? */ 1038 EMAC_WRITE(sc, EMAC_MR0, EMAC_READ(sc, EMAC_MR0) & ~MR0_SRST); 1039 1040 /* XXX clear interrupts in EMAC_ISR just to be sure?? */ 1041 1042 /* set the MAL config register */ 1043 mtdcr(DCR_MAL0_CFG, MAL0_CFG_PLBB | MAL0_CFG_OPBBL | MAL0_CFG_LEA | 1044 MAL0_CFG_SD | MAL0_CFG_PLBLT); 1045 } 1046 1047 /* 1048 * EMAC General interrupt handler 1049 */ 1050 static int 1051 emac_intr(void *arg) 1052 { 1053 struct emac_softc *sc = arg; 1054 uint32_t status; 1055 1056 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 1057 status = EMAC_READ(sc, EMAC_ISR); 1058 1059 /* Clear the interrupt status bits. */ 1060 EMAC_WRITE(sc, EMAC_ISR, status); 1061 1062 return (0); 1063 } 1064 1065 /* 1066 * EMAC Wake-On-LAN interrupt handler 1067 */ 1068 static int 1069 emac_wol_intr(void *arg) 1070 { 1071 struct emac_softc *sc = arg; 1072 1073 EMAC_EVCNT_INCR(&sc->sc_ev_wol); 1074 printf("%s: emac_wol_intr\n", sc->sc_dev.dv_xname); 1075 return (0); 1076 } 1077 1078 /* 1079 * MAL System ERRor interrupt handler 1080 */ 1081 static int 1082 emac_serr_intr(void *arg) 1083 { 1084 #ifdef EMAC_EVENT_COUNTERS 1085 struct emac_softc *sc = arg; 1086 #endif 1087 u_int32_t esr; 1088 1089 EMAC_EVCNT_INCR(&sc->sc_ev_serr); 1090 esr = mfdcr(DCR_MAL0_ESR); 1091 1092 /* Clear the interrupt status bits. */ 1093 mtdcr(DCR_MAL0_ESR, esr); 1094 return (0); 1095 } 1096 1097 /* 1098 * MAL Transmit End-Of-Buffer interrupt handler. 1099 * NOTE: This shouldn't be called! 1100 */ 1101 static int 1102 emac_txeob_intr(void *arg) 1103 { 1104 #ifdef EMAC_EVENT_COUNTERS 1105 struct emac_softc *sc = arg; 1106 #endif 1107 1108 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1109 emac_txreap(arg); 1110 1111 return (0); 1112 1113 } 1114 1115 /* 1116 * Reap completed Tx descriptors. 1117 */ 1118 static int 1119 emac_txreap(struct emac_softc *sc) 1120 { 1121 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1122 struct emac_txsoft *txs; 1123 int i; 1124 u_int32_t txstat; 1125 1126 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1127 1128 /* Clear the interrupt */ 1129 mtdcr(DCR_MAL0_TXEOBISR, mfdcr(DCR_MAL0_TXEOBISR)); 1130 1131 ifp->if_flags &= ~IFF_OACTIVE; 1132 1133 /* 1134 * Go through our Tx list and free mbufs for those 1135 * frames that have been transmitted. 1136 */ 1137 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1138 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1139 txs = &sc->sc_txsoft[i]; 1140 1141 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1142 txs->txs_dmamap->dm_nsegs, 1143 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1144 1145 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1146 if (txstat & MAL_TX_READY) 1147 break; 1148 1149 /* 1150 * Check for errors and collisions. 1151 */ 1152 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1153 ifp->if_oerrors++; 1154 1155 #ifdef EMAC_EVENT_COUNTERS 1156 if (txstat & EMAC_TXS_UR) 1157 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1158 #endif /* EMAC_EVENT_COUNTERS */ 1159 1160 if (txstat & (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1161 if (txstat & EMAC_TXS_EC) 1162 ifp->if_collisions += 16; 1163 else if (txstat & EMAC_TXS_MC) 1164 ifp->if_collisions += 2; /* XXX? */ 1165 else if (txstat & EMAC_TXS_SC) 1166 ifp->if_collisions++; 1167 if (txstat & EMAC_TXS_LC) 1168 ifp->if_collisions++; 1169 } else 1170 ifp->if_opackets++; 1171 1172 if (ifp->if_flags & IFF_DEBUG) { 1173 if (txstat & EMAC_TXS_ED) 1174 printf("%s: excessive deferral\n", 1175 sc->sc_dev.dv_xname); 1176 if (txstat & EMAC_TXS_EC) 1177 printf("%s: excessive collisions\n", 1178 sc->sc_dev.dv_xname); 1179 } 1180 1181 sc->sc_txfree += txs->txs_ndesc; 1182 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1183 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1184 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1185 m_freem(txs->txs_mbuf); 1186 txs->txs_mbuf = NULL; 1187 } 1188 1189 /* Update the dirty transmit buffer pointer. */ 1190 sc->sc_txsdirty = i; 1191 1192 /* 1193 * If there are no more pending transmissions, cancel the watchdog 1194 * timer. 1195 */ 1196 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1197 ifp->if_timer = 0; 1198 1199 return (0); 1200 } 1201 1202 /* 1203 * MAL Receive End-Of-Buffer interrupt handler 1204 */ 1205 static int 1206 emac_rxeob_intr(void *arg) 1207 { 1208 struct emac_softc *sc = arg; 1209 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1210 struct emac_rxsoft *rxs; 1211 struct mbuf *m; 1212 u_int32_t rxstat; 1213 int i, len; 1214 1215 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1216 1217 /* Clear the interrupt */ 1218 mtdcr(DCR_MAL0_RXEOBISR, mfdcr(DCR_MAL0_RXEOBISR)); 1219 1220 for (i = sc->sc_rxptr;; i = EMAC_NEXTRX(i)) { 1221 rxs = &sc->sc_rxsoft[i]; 1222 1223 EMAC_CDRXSYNC(sc, i, 1224 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1225 1226 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1227 1228 if (rxstat & MAL_RX_EMPTY) 1229 /* 1230 * We have processed all of the receive buffers. 1231 */ 1232 break; 1233 1234 /* 1235 * If an error occurred, update stats, clear the status 1236 * word, and leave the packet buffer in place. It will 1237 * simply be reused the next time the ring comes around. 1238 */ 1239 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1240 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1241 EMAC_RXS_IRE)) { 1242 #define PRINTERR(bit, str) \ 1243 if (rxstat & (bit)) \ 1244 printf("%s: receive error: %s\n", \ 1245 sc->sc_dev.dv_xname, str) 1246 ifp->if_ierrors++; 1247 PRINTERR(EMAC_RXS_OE, "overrun error"); 1248 PRINTERR(EMAC_RXS_BP, "bad packet"); 1249 PRINTERR(EMAC_RXS_RP, "runt packet"); 1250 PRINTERR(EMAC_RXS_SE, "short event"); 1251 PRINTERR(EMAC_RXS_AE, "alignment error"); 1252 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1253 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1254 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1255 PRINTERR(EMAC_RXS_IRE, "in range error"); 1256 #undef PRINTERR 1257 EMAC_INIT_RXDESC(sc, i); 1258 continue; 1259 } 1260 1261 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1262 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1263 1264 /* 1265 * No errors; receive the packet. Note, the 405GP emac 1266 * includes the CRC with every packet. 1267 */ 1268 len = sc->sc_rxdescs[i].md_data_len; 1269 1270 /* 1271 * If the packet is small enough to fit in a 1272 * single header mbuf, allocate one and copy 1273 * the data into it. This greatly reduces 1274 * memory consumption when we receive lots 1275 * of small packets. 1276 * 1277 * Otherwise, we add a new buffer to the receive 1278 * chain. If this fails, we drop the packet and 1279 * recycle the old buffer. 1280 */ 1281 if (emac_copy_small != 0 && len <= MHLEN) { 1282 MGETHDR(m, M_DONTWAIT, MT_DATA); 1283 if (m == NULL) 1284 goto dropit; 1285 memcpy(mtod(m, caddr_t), 1286 mtod(rxs->rxs_mbuf, caddr_t), len); 1287 EMAC_INIT_RXDESC(sc, i); 1288 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1289 rxs->rxs_dmamap->dm_mapsize, 1290 BUS_DMASYNC_PREREAD); 1291 } else { 1292 m = rxs->rxs_mbuf; 1293 if (emac_add_rxbuf(sc, i) != 0) { 1294 dropit: 1295 ifp->if_ierrors++; 1296 EMAC_INIT_RXDESC(sc, i); 1297 bus_dmamap_sync(sc->sc_dmat, 1298 rxs->rxs_dmamap, 0, 1299 rxs->rxs_dmamap->dm_mapsize, 1300 BUS_DMASYNC_PREREAD); 1301 continue; 1302 } 1303 } 1304 1305 ifp->if_ipackets++; 1306 m->m_flags |= M_HASFCS; 1307 m->m_pkthdr.rcvif = ifp; 1308 m->m_pkthdr.len = m->m_len = len; 1309 1310 #if NBPFILTER > 0 1311 /* 1312 * Pass this up to any BPF listeners, but only 1313 * pass if up the stack if it's for us. 1314 */ 1315 if (ifp->if_bpf) 1316 bpf_mtap(ifp->if_bpf, m); 1317 #endif /* NBPFILTER > 0 */ 1318 1319 /* Pass it on. */ 1320 (*ifp->if_input)(ifp, m); 1321 } 1322 1323 /* Update the receive pointer. */ 1324 sc->sc_rxptr = i; 1325 1326 return (0); 1327 } 1328 1329 /* 1330 * MAL Transmit Descriptor Error interrupt handler 1331 */ 1332 static int 1333 emac_txde_intr(void *arg) 1334 { 1335 struct emac_softc *sc = arg; 1336 1337 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1338 printf("%s: emac_txde_intr\n", sc->sc_dev.dv_xname); 1339 return (0); 1340 } 1341 1342 /* 1343 * MAL Receive Descriptor Error interrupt handler 1344 */ 1345 static int 1346 emac_rxde_intr(void *arg) 1347 { 1348 int i; 1349 struct emac_softc *sc = arg; 1350 1351 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1352 printf("%s: emac_rxde_intr\n", sc->sc_dev.dv_xname); 1353 /* 1354 * XXX! 1355 * This is a bit drastic; we just drop all descriptors that aren't 1356 * "clean". We should probably send any that are up the stack. 1357 */ 1358 for (i = 0; i < EMAC_NRXDESC; i++) { 1359 EMAC_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1360 1361 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) { 1362 EMAC_INIT_RXDESC(sc, i); 1363 } 1364 1365 } 1366 1367 /* Reenable the receive channel */ 1368 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 1369 1370 /* Clear the interrupt */ 1371 mtdcr(DCR_MAL0_RXDEIR, mfdcr(DCR_MAL0_RXDEIR)); 1372 1373 return (0); 1374 } 1375 1376 static uint32_t 1377 emac_mii_wait(struct emac_softc *sc) 1378 { 1379 int i; 1380 uint32_t reg; 1381 1382 /* wait for PHY data transfer to complete */ 1383 i = 0; 1384 while ((reg = EMAC_READ(sc, EMAC_STACR) & STACR_OC) == 0) { 1385 delay(7); 1386 if (i++ > 5) { 1387 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1388 return (0); 1389 } 1390 } 1391 return (reg); 1392 } 1393 1394 static int 1395 emac_mii_readreg(struct device *self, int phy, int reg) 1396 { 1397 struct emac_softc *sc = (struct emac_softc *)self; 1398 uint32_t sta_reg; 1399 1400 /* wait for PHY data transfer to complete */ 1401 if (emac_mii_wait(sc) == 0) 1402 return (0); 1403 1404 sta_reg = reg << STACR_PRASHIFT; 1405 sta_reg |= STACR_READ; 1406 sta_reg |= phy << STACR_PCDASHIFT; 1407 1408 sta_reg &= ~STACR_OPBC_MASK; 1409 sta_reg |= STACR_OPBC_50MHZ; 1410 1411 1412 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1413 1414 if ((sta_reg = emac_mii_wait(sc)) == 0) 1415 return (0); 1416 sta_reg = EMAC_READ(sc, EMAC_STACR); 1417 if ((sta_reg & STACR_PHYE) != 0) 1418 return (0); 1419 return (sta_reg >> STACR_PHYDSHIFT); 1420 } 1421 1422 static void 1423 emac_mii_writereg(struct device *self, int phy, int reg, int val) 1424 { 1425 struct emac_softc *sc = (struct emac_softc *)self; 1426 uint32_t sta_reg; 1427 1428 /* wait for PHY data transfer to complete */ 1429 if (emac_mii_wait(sc) == 0) 1430 return; 1431 1432 sta_reg = reg << STACR_PRASHIFT; 1433 sta_reg |= STACR_WRITE; 1434 sta_reg |= phy << STACR_PCDASHIFT; 1435 1436 sta_reg &= ~STACR_OPBC_MASK; 1437 sta_reg |= STACR_OPBC_50MHZ; 1438 1439 sta_reg |= val << STACR_PHYDSHIFT; 1440 1441 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1442 1443 if ((sta_reg = emac_mii_wait(sc)) == 0) 1444 return; 1445 if ((sta_reg & STACR_PHYE) != 0) 1446 /* error */ 1447 return; 1448 } 1449 1450 static void 1451 emac_mii_statchg(struct device *self) 1452 { 1453 struct emac_softc *sc = (void *)self; 1454 1455 if (sc->sc_mii.mii_media_active & IFM_FDX) 1456 sc->sc_mr1 |= MR1_FDE; 1457 else 1458 sc->sc_mr1 &= ~(MR1_FDE | MR1_EIFC); 1459 1460 /* XXX 802.1x flow-control? */ 1461 1462 /* 1463 * MR1 can only be written immediately after a reset... 1464 */ 1465 emac_reset(sc); 1466 } 1467 1468 static void 1469 emac_mii_tick(void *arg) 1470 { 1471 struct emac_softc *sc = arg; 1472 int s; 1473 1474 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1475 return; 1476 1477 s = splnet(); 1478 mii_tick(&sc->sc_mii); 1479 splx(s); 1480 1481 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1482 } 1483 1484 /* ifmedia interface function */ 1485 static void 1486 emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1487 { 1488 struct emac_softc *sc = ifp->if_softc; 1489 1490 mii_pollstat(&sc->sc_mii); 1491 1492 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1493 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1494 } 1495 1496 /* ifmedia interface function */ 1497 static int 1498 emac_mediachange(struct ifnet *ifp) 1499 { 1500 struct emac_softc *sc = ifp->if_softc; 1501 1502 if (ifp->if_flags & IFF_UP) 1503 mii_mediachg(&sc->sc_mii); 1504 return (0); 1505 } 1506