1 /* $NetBSD: if_emac.c,v 1.17 2003/10/27 03:58:17 simonb Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.17 2003/10/27 03:58:17 simonb Exp $"); 40 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 50 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #if NBPFILTER > 0 58 #include <net/bpf.h> 59 #endif 60 61 #include <powerpc/ibm4xx/dev/opbvar.h> 62 63 #include <powerpc/ibm4xx/ibm405gp.h> 64 #include <powerpc/ibm4xx/mal405gp.h> 65 #include <powerpc/ibm4xx/dcr405gp.h> 66 #include <powerpc/ibm4xx/dev/emacreg.h> 67 #include <powerpc/ibm4xx/dev/if_emacreg.h> 68 69 #include <dev/mii/miivar.h> 70 71 /* 72 * Transmit descriptor list size. There are two Tx channels, each with 73 * up to 256 hardware descriptors available. We currently use one Tx 74 * channel. We tell the upper layers that they can queue a lot of 75 * packets, and we go ahead and manage up to 64 of them at a time. We 76 * allow up to 16 DMA segments per packet. 77 */ 78 #define EMAC_NTXSEGS 16 79 #define EMAC_TXQUEUELEN 64 80 #define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 81 #define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 82 #define EMAC_NTXDESC 256 83 #define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 84 #define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 85 #define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 86 87 /* 88 * Receive descriptor list size. There is one Rx channel with up to 256 89 * hardware descriptors available. We allocate 64 receive descriptors, 90 * each with a 2k buffer (MCLBYTES). 91 */ 92 #define EMAC_NRXDESC 64 93 #define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 94 #define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 95 #define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 96 97 /* 98 * Transmit/receive descriptors that are DMA'd to the EMAC. 99 */ 100 struct emac_control_data { 101 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 102 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 103 }; 104 105 #define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 106 #define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 107 #define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 108 109 /* 110 * Software state for transmit jobs. 111 */ 112 struct emac_txsoft { 113 struct mbuf *txs_mbuf; /* head of mbuf chain */ 114 bus_dmamap_t txs_dmamap; /* our DMA map */ 115 int txs_firstdesc; /* first descriptor in packet */ 116 int txs_lastdesc; /* last descriptor in packet */ 117 int txs_ndesc; /* # of descriptors used */ 118 }; 119 120 /* 121 * Software state for receive descriptors. 122 */ 123 struct emac_rxsoft { 124 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 125 bus_dmamap_t rxs_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct emac_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 void *sc_powerhook; /* power management hook */ 139 140 struct mii_data sc_mii; /* MII/media information */ 141 struct callout sc_callout; /* tick callout */ 142 143 u_int32_t sc_mr1; /* copy of Mode Register 1 */ 144 145 bus_dmamap_t sc_cddmamap; /* control data dma map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* Software state for transmit/receive descriptors. */ 149 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 150 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 151 152 /* Control data structures. */ 153 struct emac_control_data *sc_control_data; 154 #define sc_txdescs sc_control_data->ecd_txdesc 155 #define sc_rxdescs sc_control_data->ecd_rxdesc 156 157 #ifdef EMAC_EVENT_COUNTERS 158 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 159 struct evcnt sc_ev_txintr; /* Tx interrupts */ 160 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 161 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 162 struct evcnt sc_ev_wol; /* Wake-On-Lan interrupts */ 163 struct evcnt sc_ev_serr; /* MAL system error interrupts */ 164 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 165 166 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 167 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 168 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 169 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 170 struct evcnt sc_ev_tu; /* Tx underrun */ 171 #endif /* EMAC_EVENT_COUNTERS */ 172 173 int sc_txfree; /* number of free Tx descriptors */ 174 int sc_txnext; /* next ready Tx descriptor */ 175 176 int sc_txsfree; /* number of free Tx jobs */ 177 int sc_txsnext; /* next ready Tx job */ 178 int sc_txsdirty; /* dirty Tx jobs */ 179 180 int sc_rxptr; /* next ready RX descriptor/descsoft */ 181 }; 182 183 #ifdef EMAC_EVENT_COUNTERS 184 #define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 185 #else 186 #define EMAC_EVCNT_INCR(ev) /* nothing */ 187 #endif 188 189 #define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 190 #define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 191 192 #define EMAC_CDTXSYNC(sc, x, n, ops) \ 193 do { \ 194 int __x, __n; \ 195 \ 196 __x = (x); \ 197 __n = (n); \ 198 \ 199 /* If it will wrap around, sync to the end of the ring. */ \ 200 if ((__x + __n) > EMAC_NTXDESC) { \ 201 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 202 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 203 (EMAC_NTXDESC - __x), (ops)); \ 204 __n -= (EMAC_NTXDESC - __x); \ 205 __x = 0; \ 206 } \ 207 \ 208 /* Now sync whatever is left. */ \ 209 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 210 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 211 } while (/*CONSTCOND*/0) 212 213 #define EMAC_CDRXSYNC(sc, x, ops) \ 214 do { \ 215 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 216 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 217 } while (/*CONSTCOND*/0) 218 219 #define EMAC_INIT_RXDESC(sc, x) \ 220 do { \ 221 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 222 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 223 struct mbuf *__m = __rxs->rxs_mbuf; \ 224 \ 225 /* \ 226 * Note: We scoot the packet forward 2 bytes in the buffer \ 227 * so that the payload after the Ethernet header is aligned \ 228 * to a 4-byte boundary. \ 229 */ \ 230 __m->m_data = __m->m_ext.ext_buf + 2; \ 231 \ 232 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 233 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 234 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 235 /* Set wrap on last descriptor. */ \ 236 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 237 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 238 } while (/*CONSTCOND*/0) 239 240 #define EMAC_WRITE(sc, reg, val) \ 241 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 242 #define EMAC_READ(sc, reg) \ 243 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 244 245 static int emac_match(struct device *, struct cfdata *, void *); 246 static void emac_attach(struct device *, struct device *, void *); 247 248 static int emac_add_rxbuf(struct emac_softc *, int); 249 static int emac_init(struct ifnet *); 250 static int emac_ioctl(struct ifnet *, u_long, caddr_t); 251 static void emac_reset(struct emac_softc *); 252 static void emac_rxdrain(struct emac_softc *); 253 static int emac_txreap(struct emac_softc *); 254 static void emac_shutdown(void *); 255 static void emac_start(struct ifnet *); 256 static void emac_stop(struct ifnet *, int); 257 static void emac_watchdog(struct ifnet *); 258 259 static int emac_wol_intr(void *); 260 static int emac_serr_intr(void *); 261 static int emac_txeob_intr(void *); 262 static int emac_rxeob_intr(void *); 263 static int emac_txde_intr(void *); 264 static int emac_rxde_intr(void *); 265 static int emac_intr(void *); 266 267 static int emac_mediachange(struct ifnet *); 268 static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 269 static int emac_mii_readreg(struct device *, int, int); 270 static void emac_mii_statchg(struct device *); 271 static void emac_mii_tick(void *); 272 static uint32_t emac_mii_wait(struct emac_softc *); 273 static void emac_mii_writereg(struct device *, int, int, int); 274 275 int emac_copy_small = 0; 276 277 CFATTACH_DECL(emac, sizeof(struct emac_softc), 278 emac_match, emac_attach, NULL, NULL); 279 280 static int 281 emac_match(struct device *parent, struct cfdata *cf, void *aux) 282 { 283 struct opb_attach_args *oaa = aux; 284 285 /* match only on-chip ethernet devices */ 286 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 287 return (1); 288 289 return (0); 290 } 291 292 static void 293 emac_attach(struct device *parent, struct device *self, void *aux) 294 { 295 struct opb_attach_args *oaa = aux; 296 struct emac_softc *sc = (struct emac_softc *)self; 297 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 298 struct mii_data *mii = &sc->sc_mii; 299 bus_dma_segment_t seg; 300 int error, i, nseg; 301 uint8_t enaddr[ETHER_ADDR_LEN]; 302 303 sc->sc_st = oaa->opb_bt; 304 sc->sc_sh = oaa->opb_addr; 305 sc->sc_dmat = oaa->opb_dmat; 306 307 printf(": 405GP EMAC\n"); 308 309 /* 310 * Set up Mode Register 1 - set receive and transmit FIFOs to maximum 311 * size, allow transmit of multiple packets (only channel 0 is used). 312 * 313 * XXX: Allow pause packets?? 314 */ 315 sc->sc_mr1 = MR1_RFS_4KB | MR1_TFS_2KB | MR1_TR0_MULTIPLE; 316 317 intr_establish(oaa->opb_irq , IST_LEVEL, IPL_NET, emac_wol_intr, sc); 318 intr_establish(oaa->opb_irq + 1, IST_LEVEL, IPL_NET, emac_serr_intr, sc); 319 intr_establish(oaa->opb_irq + 2, IST_LEVEL, IPL_NET, emac_txeob_intr, sc); 320 intr_establish(oaa->opb_irq + 3, IST_LEVEL, IPL_NET, emac_rxeob_intr, sc); 321 intr_establish(oaa->opb_irq + 4, IST_LEVEL, IPL_NET, emac_txde_intr, sc); 322 intr_establish(oaa->opb_irq + 5, IST_LEVEL, IPL_NET, emac_rxde_intr, sc); 323 intr_establish(oaa->opb_irq + 6, IST_LEVEL, IPL_NET, emac_intr, sc); 324 printf("%s: interrupting at irqs %d .. %d\n", sc->sc_dev.dv_xname, 325 oaa->opb_irq, oaa->opb_irq + 6); 326 327 /* 328 * Allocate the control data structures, and create and load the 329 * DMA map for it. 330 */ 331 if ((error = bus_dmamem_alloc(sc->sc_dmat, 332 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 333 printf("%s: unable to allocate control data, error = %d\n", 334 sc->sc_dev.dv_xname, error); 335 goto fail_0; 336 } 337 338 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 339 sizeof(struct emac_control_data), (caddr_t *)&sc->sc_control_data, 340 BUS_DMA_COHERENT)) != 0) { 341 printf("%s: unable to map control data, error = %d\n", 342 sc->sc_dev.dv_xname, error); 343 goto fail_1; 344 } 345 346 if ((error = bus_dmamap_create(sc->sc_dmat, 347 sizeof(struct emac_control_data), 1, 348 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 349 printf("%s: unable to create control data DMA map, " 350 "error = %d\n", sc->sc_dev.dv_xname, error); 351 goto fail_2; 352 } 353 354 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 355 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 356 0)) != 0) { 357 printf("%s: unable to load control data DMA map, error = %d\n", 358 sc->sc_dev.dv_xname, error); 359 goto fail_3; 360 } 361 362 /* 363 * Create the transmit buffer DMA maps. 364 */ 365 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 366 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 367 EMAC_NTXSEGS, MCLBYTES, 0, 0, 368 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 369 printf("%s: unable to create tx DMA map %d, " 370 "error = %d\n", sc->sc_dev.dv_xname, i, error); 371 goto fail_4; 372 } 373 } 374 375 /* 376 * Create the receive buffer DMA maps. 377 */ 378 for (i = 0; i < EMAC_NRXDESC; i++) { 379 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 380 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 381 printf("%s: unable to create rx DMA map %d, " 382 "error = %d\n", sc->sc_dev.dv_xname, i, error); 383 goto fail_5; 384 } 385 sc->sc_rxsoft[i].rxs_mbuf = NULL; 386 } 387 388 /* 389 * Reset the chip to a known state. 390 */ 391 emac_reset(sc); 392 393 /* Fetch the Ethernet address. */ 394 if (prop_get(dev_propdb, &sc->sc_dev, "mac-addr", enaddr, 395 sizeof(enaddr), NULL) != sizeof(enaddr)) { 396 printf("%s: unable to get mac-addr property\n", 397 sc->sc_dev.dv_xname); 398 return; 399 } 400 401 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 402 ether_sprintf(enaddr)); 403 404 /* 405 * Initialise the media structures. 406 */ 407 mii->mii_ifp = ifp; 408 mii->mii_readreg = emac_mii_readreg; 409 mii->mii_writereg = emac_mii_writereg; 410 mii->mii_statchg = emac_mii_statchg; 411 412 ifmedia_init(&mii->mii_media, 0, emac_mediachange, 413 emac_mediastatus); 414 mii_attach(&sc->sc_dev, mii, 0xffffffff, 415 MII_PHY_ANY, MII_OFFSET_ANY, 0); 416 if (LIST_FIRST(&mii->mii_phys) == NULL) { 417 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 418 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 419 } else 420 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 421 422 ifp = &sc->sc_ethercom.ec_if; 423 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 424 ifp->if_softc = sc; 425 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 426 ifp->if_ioctl = emac_ioctl; 427 ifp->if_start = emac_start; 428 ifp->if_watchdog = emac_watchdog; 429 ifp->if_init = emac_init; 430 ifp->if_stop = emac_stop; 431 IFQ_SET_READY(&ifp->if_snd); 432 433 /* 434 * We can support 802.1Q VLAN-sized frames. 435 */ 436 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 437 438 /* 439 * Attach the interface. 440 */ 441 if_attach(ifp); 442 ether_ifattach(ifp, enaddr); 443 444 #ifdef EMAC_EVENT_COUNTERS 445 /* 446 * Attach the event counters. 447 */ 448 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 449 NULL, sc->sc_dev.dv_xname, "rxintr"); 450 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 451 NULL, sc->sc_dev.dv_xname, "txintr"); 452 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 453 NULL, sc->sc_dev.dv_xname, "rxde"); 454 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 455 NULL, sc->sc_dev.dv_xname, "txde"); 456 evcnt_attach_dynamic(&sc->sc_ev_wol, EVCNT_TYPE_INTR, 457 NULL, sc->sc_dev.dv_xname, "wol"); 458 evcnt_attach_dynamic(&sc->sc_ev_serr, EVCNT_TYPE_INTR, 459 NULL, sc->sc_dev.dv_xname, "serr"); 460 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 461 NULL, sc->sc_dev.dv_xname, "intr"); 462 463 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 464 NULL, sc->sc_dev.dv_xname, "txreap"); 465 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 466 NULL, sc->sc_dev.dv_xname, "txsstall"); 467 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 468 NULL, sc->sc_dev.dv_xname, "txdstall"); 469 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 470 NULL, sc->sc_dev.dv_xname, "txdrop"); 471 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 472 NULL, sc->sc_dev.dv_xname, "tu"); 473 #endif /* EMAC_EVENT_COUNTERS */ 474 475 /* 476 * Make sure the interface is shutdown during reboot. 477 */ 478 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 479 if (sc->sc_sdhook == NULL) 480 printf("%s: WARNING: unable to establish shutdown hook\n", 481 sc->sc_dev.dv_xname); 482 483 return; 484 485 /* 486 * Free any resources we've allocated during the failed attach 487 * attempt. Do this in reverse order and fall through. 488 */ 489 fail_5: 490 for (i = 0; i < EMAC_NRXDESC; i++) { 491 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 492 bus_dmamap_destroy(sc->sc_dmat, 493 sc->sc_rxsoft[i].rxs_dmamap); 494 } 495 fail_4: 496 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 497 if (sc->sc_txsoft[i].txs_dmamap != NULL) 498 bus_dmamap_destroy(sc->sc_dmat, 499 sc->sc_txsoft[i].txs_dmamap); 500 } 501 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 502 fail_3: 503 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 504 fail_2: 505 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 506 sizeof(struct emac_control_data)); 507 fail_1: 508 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 509 fail_0: 510 return; 511 } 512 513 /* 514 * Device shutdown routine. 515 */ 516 static void 517 emac_shutdown(void *arg) 518 { 519 struct emac_softc *sc = arg; 520 521 emac_stop(&sc->sc_ethercom.ec_if, 0); 522 } 523 524 /* ifnet interface function */ 525 static void 526 emac_start(struct ifnet *ifp) 527 { 528 struct emac_softc *sc = ifp->if_softc; 529 struct mbuf *m0; 530 struct emac_txsoft *txs; 531 bus_dmamap_t dmamap; 532 int error, firsttx, nexttx, lasttx, ofree, seg; 533 534 lasttx = 0; /* XXX gcc */ 535 536 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 537 return; 538 539 /* 540 * Remember the previous number of free descriptors. 541 */ 542 ofree = sc->sc_txfree; 543 544 /* 545 * Loop through the send queue, setting up transmit descriptors 546 * until we drain the queue, or use up all available transmit 547 * descriptors. 548 */ 549 for (;;) { 550 /* Grab a packet off the queue. */ 551 IFQ_POLL(&ifp->if_snd, m0); 552 if (m0 == NULL) 553 break; 554 555 /* 556 * Get a work queue entry. Reclaim used Tx descriptors if 557 * we are running low. 558 */ 559 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 560 emac_txreap(sc); 561 if (sc->sc_txsfree == 0) { 562 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 563 break; 564 } 565 } 566 567 txs = &sc->sc_txsoft[sc->sc_txsnext]; 568 dmamap = txs->txs_dmamap; 569 570 /* 571 * Load the DMA map. If this fails, the packet either 572 * didn't fit in the alloted number of segments, or we 573 * were short on resources. In this case, we'll copy 574 * and try again. 575 */ 576 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 577 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 578 if (error) { 579 if (error == EFBIG) { 580 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 581 printf("%s: Tx packet consumes too many " 582 "DMA segments, dropping...\n", 583 sc->sc_dev.dv_xname); 584 IFQ_DEQUEUE(&ifp->if_snd, m0); 585 m_freem(m0); 586 continue; 587 } 588 /* Short on resources, just stop for now. */ 589 break; 590 } 591 592 /* 593 * Ensure we have enough descriptors free to describe 594 * the packet. 595 */ 596 if (dmamap->dm_nsegs > sc->sc_txfree) { 597 /* 598 * Not enough free descriptors to transmit this 599 * packet. We haven't committed anything yet, 600 * so just unload the DMA map, put the packet 601 * back on the queue, and punt. Notify the upper 602 * layer that there are not more slots left. 603 * 604 */ 605 ifp->if_flags |= IFF_OACTIVE; 606 bus_dmamap_unload(sc->sc_dmat, dmamap); 607 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 608 break; 609 } 610 611 IFQ_DEQUEUE(&ifp->if_snd, m0); 612 613 /* 614 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 615 */ 616 617 /* Sync the DMA map. */ 618 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 619 BUS_DMASYNC_PREWRITE); 620 621 /* 622 * Store a pointer to the packet so that we can free it 623 * later. 624 */ 625 txs->txs_mbuf = m0; 626 txs->txs_firstdesc = sc->sc_txnext; 627 txs->txs_ndesc = dmamap->dm_nsegs; 628 629 /* 630 * Initialize the transmit descriptor. 631 */ 632 firsttx = sc->sc_txnext; 633 for (nexttx = sc->sc_txnext, seg = 0; 634 seg < dmamap->dm_nsegs; 635 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 636 /* 637 * If this is the first descriptor we're 638 * enqueueing, don't set the TX_READY bit just 639 * yet. That could cause a race condition. 640 * We'll do it below. 641 */ 642 sc->sc_txdescs[nexttx].md_data = 643 dmamap->dm_segs[seg].ds_addr; 644 sc->sc_txdescs[nexttx].md_data_len = 645 dmamap->dm_segs[seg].ds_len; 646 sc->sc_txdescs[nexttx].md_stat_ctrl = 647 (sc->sc_txdescs[nexttx].md_stat_ctrl & MAL_TX_WRAP) | 648 (nexttx == firsttx ? 0 : MAL_TX_READY) | 649 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 650 lasttx = nexttx; 651 } 652 653 /* Set the LAST bit on the last segment. */ 654 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 655 656 txs->txs_lastdesc = lasttx; 657 658 /* Sync the descriptors we're using. */ 659 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 661 662 /* 663 * The entire packet chain is set up. Give the 664 * first descriptor to the chip now. 665 */ 666 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 667 EMAC_CDTXSYNC(sc, firsttx, 1, 668 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 669 /* 670 * Tell the EMAC that a new packet is available. 671 */ 672 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0); 673 674 /* Advance the tx pointer. */ 675 sc->sc_txfree -= txs->txs_ndesc; 676 sc->sc_txnext = nexttx; 677 678 sc->sc_txsfree--; 679 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 680 681 #if NBPFILTER > 0 682 /* 683 * Pass the packet to any BPF listeners. 684 */ 685 if (ifp->if_bpf) 686 bpf_mtap(ifp->if_bpf, m0); 687 #endif /* NBPFILTER > 0 */ 688 } 689 690 if (sc->sc_txfree == 0) { 691 /* No more slots left; notify upper layer. */ 692 ifp->if_flags |= IFF_OACTIVE; 693 } 694 695 if (sc->sc_txfree != ofree) { 696 /* Set a watchdog timer in case the chip flakes out. */ 697 ifp->if_timer = 5; 698 } 699 } 700 701 static int 702 emac_init(struct ifnet *ifp) 703 { 704 struct emac_softc *sc = ifp->if_softc; 705 struct emac_rxsoft *rxs; 706 uint8_t *enaddr = LLADDR(ifp->if_sadl); 707 int error, i; 708 709 error = 0; 710 711 /* Cancel any pending I/O. */ 712 emac_stop(ifp, 0); 713 714 /* Reset the chip to a known state. */ 715 emac_reset(sc); 716 717 /* 718 * Initialise the transmit descriptor ring. 719 */ 720 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 721 /* set wrap on last descriptor */ 722 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 723 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 724 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 725 sc->sc_txfree = EMAC_NTXDESC; 726 sc->sc_txnext = 0; 727 728 /* 729 * Initialise the transmit job descriptors. 730 */ 731 for (i = 0; i < EMAC_TXQUEUELEN; i++) 732 sc->sc_txsoft[i].txs_mbuf = NULL; 733 sc->sc_txsfree = EMAC_TXQUEUELEN; 734 sc->sc_txsnext = 0; 735 sc->sc_txsdirty = 0; 736 737 /* 738 * Initialise the receiver descriptor and receive job 739 * descriptor rings. 740 */ 741 for (i = 0; i < EMAC_NRXDESC; i++) { 742 rxs = &sc->sc_rxsoft[i]; 743 if (rxs->rxs_mbuf == NULL) { 744 if ((error = emac_add_rxbuf(sc, i)) != 0) { 745 printf("%s: unable to allocate or map rx " 746 "buffer %d, error = %d\n", 747 sc->sc_dev.dv_xname, i, error); 748 /* 749 * XXX Should attempt to run with fewer receive 750 * XXX buffers instead of just failing. 751 */ 752 emac_rxdrain(sc); 753 goto out; 754 } 755 } else 756 EMAC_INIT_RXDESC(sc, i); 757 } 758 sc->sc_rxptr = 0; 759 760 /* 761 * Set the current media. 762 */ 763 mii_mediachg(&sc->sc_mii); 764 765 /* 766 * Give the transmit and receive rings to the MAL. 767 */ 768 mtdcr(DCR_MAL0_TXCTP0R, EMAC_CDTXADDR(sc, 0)); 769 mtdcr(DCR_MAL0_RXCTP0R, EMAC_CDRXADDR(sc, 0)); 770 771 /* 772 * Load the MAC address. 773 */ 774 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 775 EMAC_WRITE(sc, EMAC_IALR, 776 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 777 778 /* 779 * Set the receive channel buffer size (in units of 16 bytes). 780 */ 781 #if MCLBYTES > (4096 - 16) /* XXX! */ 782 # error MCLBYTES > max rx channel buffer size 783 #endif 784 mtdcr(DCR_MAL0_RCBS0, MCLBYTES / 16); 785 786 /* Set fifos, media modes. */ 787 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 788 789 /* 790 * Enable Individual and (possibly) Broadcast Address modes, 791 * runt packets, and strip padding. 792 * 793 * XXX: promiscuous mode (and promiscuous multicast mode) need to be 794 * dealt with here! 795 */ 796 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | 797 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 798 799 /* 800 * Set low- and urgent-priority request thresholds. 801 */ 802 EMAC_WRITE(sc, EMAC_TMR1, 803 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 804 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 805 /* 806 * Set Transmit Request Threshold Register. 807 */ 808 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 809 810 /* 811 * Set high and low receive watermarks. 812 */ 813 EMAC_WRITE(sc, EMAC_RWMR, 814 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 815 816 /* 817 * Set frame gap. 818 */ 819 EMAC_WRITE(sc, EMAC_IPGVR, 8); 820 821 /* 822 * Set interrupt status enable bits for EMAC and MAL. 823 */ 824 EMAC_WRITE(sc, EMAC_ISER, 825 ISR_BP | ISR_SE | ISR_ALE | ISR_BFCS | ISR_PTLE | ISR_ORE | ISR_IRE); 826 mtdcr(DCR_MAL0_IER, MAL0_IER_DE | MAL0_IER_NWE | MAL0_IER_TO | 827 MAL0_IER_OPB | MAL0_IER_PLB); 828 829 /* 830 * Enable the transmit and receive channel on the MAL. 831 */ 832 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 833 mtdcr(DCR_MAL0_TXCASR, MAL0_TXCASR_CHAN0); 834 835 /* 836 * Enable the transmit and receive channel on the EMAC. 837 */ 838 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 839 840 /* 841 * Start the one second MII clock. 842 */ 843 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 844 845 /* 846 * ... all done! 847 */ 848 ifp->if_flags |= IFF_RUNNING; 849 ifp->if_flags &= ~IFF_OACTIVE; 850 851 out: 852 if (error) { 853 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 854 ifp->if_timer = 0; 855 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 856 } 857 return (error); 858 } 859 860 static int 861 emac_add_rxbuf(struct emac_softc *sc, int idx) 862 { 863 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 864 struct mbuf *m; 865 int error; 866 867 MGETHDR(m, M_DONTWAIT, MT_DATA); 868 if (m == NULL) 869 return (ENOBUFS); 870 871 MCLGET(m, M_DONTWAIT); 872 if ((m->m_flags & M_EXT) == 0) { 873 m_freem(m); 874 return (ENOBUFS); 875 } 876 877 if (rxs->rxs_mbuf != NULL) 878 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 879 880 rxs->rxs_mbuf = m; 881 882 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 883 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 884 if (error) { 885 printf("%s: can't load rx DMA map %d, error = %d\n", 886 sc->sc_dev.dv_xname, idx, error); 887 panic("emac_add_rxbuf"); /* XXX */ 888 } 889 890 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 891 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 892 893 EMAC_INIT_RXDESC(sc, idx); 894 895 return (0); 896 } 897 898 /* ifnet interface function */ 899 static void 900 emac_watchdog(struct ifnet *ifp) 901 { 902 struct emac_softc *sc = ifp->if_softc; 903 904 /* 905 * Since we're not interrupting every packet, sweep 906 * up before we report an error. 907 */ 908 emac_txreap(sc); 909 910 if (sc->sc_txfree != EMAC_NTXDESC) { 911 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 912 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 913 sc->sc_txnext); 914 ifp->if_oerrors++; 915 916 /* Reset the interface. */ 917 (void)emac_init(ifp); 918 } else if (ifp->if_flags & IFF_DEBUG) 919 printf("%s: recovered from device timeout\n", 920 sc->sc_dev.dv_xname); 921 922 /* try to get more packets going */ 923 emac_start(ifp); 924 } 925 926 static void 927 emac_rxdrain(struct emac_softc *sc) 928 { 929 struct emac_rxsoft *rxs; 930 int i; 931 932 for (i = 0; i < EMAC_NRXDESC; i++) { 933 rxs = &sc->sc_rxsoft[i]; 934 if (rxs->rxs_mbuf != NULL) { 935 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 936 m_freem(rxs->rxs_mbuf); 937 rxs->rxs_mbuf = NULL; 938 } 939 } 940 } 941 942 /* ifnet interface function */ 943 static void 944 emac_stop(struct ifnet *ifp, int disable) 945 { 946 struct emac_softc *sc = ifp->if_softc; 947 struct emac_txsoft *txs; 948 int i; 949 950 /* Stop the one second clock. */ 951 callout_stop(&sc->sc_callout); 952 953 /* Down the MII */ 954 mii_down(&sc->sc_mii); 955 956 /* Disable interrupts. */ 957 #if 0 /* Can't disable MAL interrupts without a reset... */ 958 EMAC_WRITE(sc, EMAC_ISER, 0); 959 #endif 960 mtdcr(DCR_MAL0_IER, 0); 961 962 /* Disable the receive and transmit channels. */ 963 mtdcr(DCR_MAL0_RXCARR, MAL0_RXCARR_CHAN0); 964 mtdcr(DCR_MAL0_TXCARR, MAL0_TXCARR_CHAN0 | MAL0_TXCARR_CHAN1); 965 966 /* Disable the transmit enable and receive MACs. */ 967 EMAC_WRITE(sc, EMAC_MR0, 968 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 969 970 /* Release any queued transmit buffers. */ 971 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 972 txs = &sc->sc_txsoft[i]; 973 if (txs->txs_mbuf != NULL) { 974 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 975 m_freem(txs->txs_mbuf); 976 txs->txs_mbuf = NULL; 977 } 978 } 979 980 if (disable) 981 emac_rxdrain(sc); 982 983 /* 984 * Mark the interface down and cancel the watchdog timer. 985 */ 986 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 987 ifp->if_timer = 0; 988 } 989 990 /* ifnet interface function */ 991 static int 992 emac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 993 { 994 struct emac_softc *sc = ifp->if_softc; 995 struct ifreq *ifr = (struct ifreq *)data; 996 int s, error; 997 998 s = splnet(); 999 1000 switch (cmd) { 1001 case SIOCSIFMEDIA: 1002 case SIOCGIFMEDIA: 1003 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1004 break; 1005 1006 default: 1007 error = ether_ioctl(ifp, cmd, data); 1008 if (error == ENETRESET) { 1009 /* 1010 * Multicast list has changed; set the hardware filter 1011 * accordingly. 1012 */ 1013 #if 0 1014 error = emac_set_filter(sc); /* XXX not done yet */ 1015 #else 1016 error = emac_init(ifp); 1017 #endif 1018 } 1019 break; 1020 } 1021 1022 /* try to get more packets going */ 1023 emac_start(ifp); 1024 1025 splx(s); 1026 return (error); 1027 } 1028 1029 static void 1030 emac_reset(struct emac_softc *sc) 1031 { 1032 1033 /* reset the MAL */ 1034 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR); 1035 1036 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1037 delay(5); 1038 1039 /* XXX: check if MR0_SRST is clear until a timeout instead? */ 1040 EMAC_WRITE(sc, EMAC_MR0, EMAC_READ(sc, EMAC_MR0) & ~MR0_SRST); 1041 1042 /* XXX clear interrupts in EMAC_ISR just to be sure?? */ 1043 1044 /* set the MAL config register */ 1045 mtdcr(DCR_MAL0_CFG, MAL0_CFG_PLBB | MAL0_CFG_OPBBL | MAL0_CFG_LEA | 1046 MAL0_CFG_SD | MAL0_CFG_PLBLT); 1047 } 1048 1049 /* 1050 * EMAC General interrupt handler 1051 */ 1052 static int 1053 emac_intr(void *arg) 1054 { 1055 struct emac_softc *sc = arg; 1056 uint32_t status; 1057 1058 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 1059 status = EMAC_READ(sc, EMAC_ISR); 1060 1061 /* Clear the interrupt status bits. */ 1062 EMAC_WRITE(sc, EMAC_ISR, status); 1063 1064 return (0); 1065 } 1066 1067 /* 1068 * EMAC Wake-On-LAN interrupt handler 1069 */ 1070 static int 1071 emac_wol_intr(void *arg) 1072 { 1073 struct emac_softc *sc = arg; 1074 1075 EMAC_EVCNT_INCR(&sc->sc_ev_wol); 1076 printf("%s: emac_wol_intr\n", sc->sc_dev.dv_xname); 1077 return (0); 1078 } 1079 1080 /* 1081 * MAL System ERRor interrupt handler 1082 */ 1083 static int 1084 emac_serr_intr(void *arg) 1085 { 1086 #ifdef EMAC_EVENT_COUNTERS 1087 struct emac_softc *sc = arg; 1088 #endif 1089 u_int32_t esr; 1090 1091 EMAC_EVCNT_INCR(&sc->sc_ev_serr); 1092 esr = mfdcr(DCR_MAL0_ESR); 1093 1094 /* Clear the interrupt status bits. */ 1095 mtdcr(DCR_MAL0_ESR, esr); 1096 return (0); 1097 } 1098 1099 /* 1100 * MAL Transmit End-Of-Buffer interrupt handler. 1101 * NOTE: This shouldn't be called! 1102 */ 1103 static int 1104 emac_txeob_intr(void *arg) 1105 { 1106 #ifdef EMAC_EVENT_COUNTERS 1107 struct emac_softc *sc = arg; 1108 #endif 1109 1110 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1111 emac_txreap(arg); 1112 1113 return (0); 1114 1115 } 1116 1117 /* 1118 * Reap completed Tx descriptors. 1119 */ 1120 static int 1121 emac_txreap(struct emac_softc *sc) 1122 { 1123 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1124 struct emac_txsoft *txs; 1125 int i; 1126 u_int32_t txstat; 1127 1128 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1129 1130 /* Clear the interrupt */ 1131 mtdcr(DCR_MAL0_TXEOBISR, mfdcr(DCR_MAL0_TXEOBISR)); 1132 1133 ifp->if_flags &= ~IFF_OACTIVE; 1134 1135 /* 1136 * Go through our Tx list and free mbufs for those 1137 * frames that have been transmitted. 1138 */ 1139 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1140 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1141 txs = &sc->sc_txsoft[i]; 1142 1143 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1144 txs->txs_dmamap->dm_nsegs, 1145 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1146 1147 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1148 if (txstat & MAL_TX_READY) 1149 break; 1150 1151 /* 1152 * Check for errors and collisions. 1153 */ 1154 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1155 ifp->if_oerrors++; 1156 1157 #ifdef EMAC_EVENT_COUNTERS 1158 if (txstat & EMAC_TXS_UR) 1159 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1160 #endif /* EMAC_EVENT_COUNTERS */ 1161 1162 if (txstat & (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1163 if (txstat & EMAC_TXS_EC) 1164 ifp->if_collisions += 16; 1165 else if (txstat & EMAC_TXS_MC) 1166 ifp->if_collisions += 2; /* XXX? */ 1167 else if (txstat & EMAC_TXS_SC) 1168 ifp->if_collisions++; 1169 if (txstat & EMAC_TXS_LC) 1170 ifp->if_collisions++; 1171 } else 1172 ifp->if_opackets++; 1173 1174 if (ifp->if_flags & IFF_DEBUG) { 1175 if (txstat & EMAC_TXS_ED) 1176 printf("%s: excessive deferral\n", 1177 sc->sc_dev.dv_xname); 1178 if (txstat & EMAC_TXS_EC) 1179 printf("%s: excessive collisions\n", 1180 sc->sc_dev.dv_xname); 1181 } 1182 1183 sc->sc_txfree += txs->txs_ndesc; 1184 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1185 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1186 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1187 m_freem(txs->txs_mbuf); 1188 txs->txs_mbuf = NULL; 1189 } 1190 1191 /* Update the dirty transmit buffer pointer. */ 1192 sc->sc_txsdirty = i; 1193 1194 /* 1195 * If there are no more pending transmissions, cancel the watchdog 1196 * timer. 1197 */ 1198 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1199 ifp->if_timer = 0; 1200 1201 return (0); 1202 } 1203 1204 /* 1205 * MAL Receive End-Of-Buffer interrupt handler 1206 */ 1207 static int 1208 emac_rxeob_intr(void *arg) 1209 { 1210 struct emac_softc *sc = arg; 1211 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1212 struct emac_rxsoft *rxs; 1213 struct mbuf *m; 1214 u_int32_t rxstat; 1215 int i, len; 1216 1217 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1218 1219 /* Clear the interrupt */ 1220 mtdcr(DCR_MAL0_RXEOBISR, mfdcr(DCR_MAL0_RXEOBISR)); 1221 1222 for (i = sc->sc_rxptr;; i = EMAC_NEXTRX(i)) { 1223 rxs = &sc->sc_rxsoft[i]; 1224 1225 EMAC_CDRXSYNC(sc, i, 1226 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1227 1228 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1229 1230 if (rxstat & MAL_RX_EMPTY) 1231 /* 1232 * We have processed all of the receive buffers. 1233 */ 1234 break; 1235 1236 /* 1237 * If an error occurred, update stats, clear the status 1238 * word, and leave the packet buffer in place. It will 1239 * simply be reused the next time the ring comes around. 1240 */ 1241 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1242 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1243 EMAC_RXS_IRE)) { 1244 #define PRINTERR(bit, str) \ 1245 if (rxstat & (bit)) \ 1246 printf("%s: receive error: %s\n", \ 1247 sc->sc_dev.dv_xname, str) 1248 ifp->if_ierrors++; 1249 PRINTERR(EMAC_RXS_OE, "overrun error"); 1250 PRINTERR(EMAC_RXS_BP, "bad packet"); 1251 PRINTERR(EMAC_RXS_RP, "runt packet"); 1252 PRINTERR(EMAC_RXS_SE, "short event"); 1253 PRINTERR(EMAC_RXS_AE, "alignment error"); 1254 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1255 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1256 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1257 PRINTERR(EMAC_RXS_IRE, "in range error"); 1258 #undef PRINTERR 1259 EMAC_INIT_RXDESC(sc, i); 1260 continue; 1261 } 1262 1263 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1264 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1265 1266 /* 1267 * No errors; receive the packet. Note, the 405GP emac 1268 * includes the CRC with every packet. 1269 */ 1270 len = sc->sc_rxdescs[i].md_data_len; 1271 1272 /* 1273 * If the packet is small enough to fit in a 1274 * single header mbuf, allocate one and copy 1275 * the data into it. This greatly reduces 1276 * memory consumption when we receive lots 1277 * of small packets. 1278 * 1279 * Otherwise, we add a new buffer to the receive 1280 * chain. If this fails, we drop the packet and 1281 * recycle the old buffer. 1282 */ 1283 if (emac_copy_small != 0 && len <= MHLEN) { 1284 MGETHDR(m, M_DONTWAIT, MT_DATA); 1285 if (m == NULL) 1286 goto dropit; 1287 memcpy(mtod(m, caddr_t), 1288 mtod(rxs->rxs_mbuf, caddr_t), len); 1289 EMAC_INIT_RXDESC(sc, i); 1290 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1291 rxs->rxs_dmamap->dm_mapsize, 1292 BUS_DMASYNC_PREREAD); 1293 } else { 1294 m = rxs->rxs_mbuf; 1295 if (emac_add_rxbuf(sc, i) != 0) { 1296 dropit: 1297 ifp->if_ierrors++; 1298 EMAC_INIT_RXDESC(sc, i); 1299 bus_dmamap_sync(sc->sc_dmat, 1300 rxs->rxs_dmamap, 0, 1301 rxs->rxs_dmamap->dm_mapsize, 1302 BUS_DMASYNC_PREREAD); 1303 continue; 1304 } 1305 } 1306 1307 ifp->if_ipackets++; 1308 m->m_flags |= M_HASFCS; 1309 m->m_pkthdr.rcvif = ifp; 1310 m->m_pkthdr.len = m->m_len = len; 1311 1312 #if NBPFILTER > 0 1313 /* 1314 * Pass this up to any BPF listeners, but only 1315 * pass if up the stack if it's for us. 1316 */ 1317 if (ifp->if_bpf) 1318 bpf_mtap(ifp->if_bpf, m); 1319 #endif /* NBPFILTER > 0 */ 1320 1321 /* Pass it on. */ 1322 (*ifp->if_input)(ifp, m); 1323 } 1324 1325 /* Update the receive pointer. */ 1326 sc->sc_rxptr = i; 1327 1328 return (0); 1329 } 1330 1331 /* 1332 * MAL Transmit Descriptor Error interrupt handler 1333 */ 1334 static int 1335 emac_txde_intr(void *arg) 1336 { 1337 struct emac_softc *sc = arg; 1338 1339 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1340 printf("%s: emac_txde_intr\n", sc->sc_dev.dv_xname); 1341 return (0); 1342 } 1343 1344 /* 1345 * MAL Receive Descriptor Error interrupt handler 1346 */ 1347 static int 1348 emac_rxde_intr(void *arg) 1349 { 1350 int i; 1351 struct emac_softc *sc = arg; 1352 1353 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1354 printf("%s: emac_rxde_intr\n", sc->sc_dev.dv_xname); 1355 /* 1356 * XXX! 1357 * This is a bit drastic; we just drop all descriptors that aren't 1358 * "clean". We should probably send any that are up the stack. 1359 */ 1360 for (i = 0; i < EMAC_NRXDESC; i++) { 1361 EMAC_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1362 1363 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) { 1364 EMAC_INIT_RXDESC(sc, i); 1365 } 1366 1367 } 1368 1369 /* Reenable the receive channel */ 1370 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 1371 1372 /* Clear the interrupt */ 1373 mtdcr(DCR_MAL0_RXDEIR, mfdcr(DCR_MAL0_RXDEIR)); 1374 1375 return (0); 1376 } 1377 1378 static uint32_t 1379 emac_mii_wait(struct emac_softc *sc) 1380 { 1381 int i; 1382 uint32_t reg; 1383 1384 /* wait for PHY data transfer to complete */ 1385 i = 0; 1386 while ((reg = EMAC_READ(sc, EMAC_STACR) & STACR_OC) == 0) { 1387 delay(7); 1388 if (i++ > 5) { 1389 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1390 return (0); 1391 } 1392 } 1393 return (reg); 1394 } 1395 1396 static int 1397 emac_mii_readreg(struct device *self, int phy, int reg) 1398 { 1399 struct emac_softc *sc = (struct emac_softc *)self; 1400 uint32_t sta_reg; 1401 1402 /* wait for PHY data transfer to complete */ 1403 if (emac_mii_wait(sc) == 0) 1404 return (0); 1405 1406 sta_reg = reg << STACR_PRASHIFT; 1407 sta_reg |= STACR_READ; 1408 sta_reg |= phy << STACR_PCDASHIFT; 1409 1410 sta_reg &= ~STACR_OPBC_MASK; 1411 sta_reg |= STACR_OPBC_50MHZ; 1412 1413 1414 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1415 1416 if ((sta_reg = emac_mii_wait(sc)) == 0) 1417 return (0); 1418 sta_reg = EMAC_READ(sc, EMAC_STACR); 1419 if ((sta_reg & STACR_PHYE) != 0) 1420 return (0); 1421 return (sta_reg >> STACR_PHYDSHIFT); 1422 } 1423 1424 static void 1425 emac_mii_writereg(struct device *self, int phy, int reg, int val) 1426 { 1427 struct emac_softc *sc = (struct emac_softc *)self; 1428 uint32_t sta_reg; 1429 1430 /* wait for PHY data transfer to complete */ 1431 if (emac_mii_wait(sc) == 0) 1432 return; 1433 1434 sta_reg = reg << STACR_PRASHIFT; 1435 sta_reg |= STACR_WRITE; 1436 sta_reg |= phy << STACR_PCDASHIFT; 1437 1438 sta_reg &= ~STACR_OPBC_MASK; 1439 sta_reg |= STACR_OPBC_50MHZ; 1440 1441 sta_reg |= val << STACR_PHYDSHIFT; 1442 1443 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1444 1445 if ((sta_reg = emac_mii_wait(sc)) == 0) 1446 return; 1447 if ((sta_reg & STACR_PHYE) != 0) 1448 /* error */ 1449 return; 1450 } 1451 1452 static void 1453 emac_mii_statchg(struct device *self) 1454 { 1455 struct emac_softc *sc = (void *)self; 1456 1457 if (sc->sc_mii.mii_media_active & IFM_FDX) 1458 sc->sc_mr1 |= MR1_FDE; 1459 else 1460 sc->sc_mr1 &= ~(MR1_FDE | MR1_EIFC); 1461 1462 /* XXX 802.1x flow-control? */ 1463 1464 /* 1465 * MR1 can only be written immediately after a reset... 1466 */ 1467 emac_reset(sc); 1468 } 1469 1470 static void 1471 emac_mii_tick(void *arg) 1472 { 1473 struct emac_softc *sc = arg; 1474 int s; 1475 1476 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1477 return; 1478 1479 s = splnet(); 1480 mii_tick(&sc->sc_mii); 1481 splx(s); 1482 1483 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1484 } 1485 1486 /* ifmedia interface function */ 1487 static void 1488 emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1489 { 1490 struct emac_softc *sc = ifp->if_softc; 1491 1492 mii_pollstat(&sc->sc_mii); 1493 1494 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1495 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1496 } 1497 1498 /* ifmedia interface function */ 1499 static int 1500 emac_mediachange(struct ifnet *ifp) 1501 { 1502 struct emac_softc *sc = ifp->if_softc; 1503 1504 if (ifp->if_flags & IFF_UP) 1505 mii_mediachg(&sc->sc_mii); 1506 return (0); 1507 } 1508