1 /* $NetBSD: if_emac.c,v 1.32 2008/01/22 11:49:54 he Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.32 2008/01/22 11:49:54 he Exp $"); 40 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 50 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #if NBPFILTER > 0 58 #include <net/bpf.h> 59 #endif 60 61 #include <powerpc/ibm4xx/dev/opbvar.h> 62 63 #include <powerpc/ibm4xx/ibm405gp.h> 64 #include <powerpc/ibm4xx/mal405gp.h> 65 #include <powerpc/ibm4xx/dcr405gp.h> 66 #include <powerpc/ibm4xx/dev/emacreg.h> 67 #include <powerpc/ibm4xx/dev/if_emacreg.h> 68 69 #include <dev/mii/miivar.h> 70 71 /* 72 * Transmit descriptor list size. There are two Tx channels, each with 73 * up to 256 hardware descriptors available. We currently use one Tx 74 * channel. We tell the upper layers that they can queue a lot of 75 * packets, and we go ahead and manage up to 64 of them at a time. We 76 * allow up to 16 DMA segments per packet. 77 */ 78 #define EMAC_NTXSEGS 16 79 #define EMAC_TXQUEUELEN 64 80 #define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 81 #define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 82 #define EMAC_NTXDESC 256 83 #define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 84 #define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 85 #define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 86 87 /* 88 * Receive descriptor list size. There is one Rx channel with up to 256 89 * hardware descriptors available. We allocate 64 receive descriptors, 90 * each with a 2k buffer (MCLBYTES). 91 */ 92 #define EMAC_NRXDESC 64 93 #define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 94 #define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 95 #define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 96 97 /* 98 * Transmit/receive descriptors that are DMA'd to the EMAC. 99 */ 100 struct emac_control_data { 101 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 102 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 103 }; 104 105 #define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 106 #define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 107 #define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 108 109 /* 110 * Software state for transmit jobs. 111 */ 112 struct emac_txsoft { 113 struct mbuf *txs_mbuf; /* head of mbuf chain */ 114 bus_dmamap_t txs_dmamap; /* our DMA map */ 115 int txs_firstdesc; /* first descriptor in packet */ 116 int txs_lastdesc; /* last descriptor in packet */ 117 int txs_ndesc; /* # of descriptors used */ 118 }; 119 120 /* 121 * Software state for receive descriptors. 122 */ 123 struct emac_rxsoft { 124 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 125 bus_dmamap_t rxs_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct emac_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 void *sc_powerhook; /* power management hook */ 139 140 struct mii_data sc_mii; /* MII/media information */ 141 struct callout sc_callout; /* tick callout */ 142 143 u_int32_t sc_mr1; /* copy of Mode Register 1 */ 144 145 bus_dmamap_t sc_cddmamap; /* control data dma map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* Software state for transmit/receive descriptors. */ 149 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 150 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 151 152 /* Control data structures. */ 153 struct emac_control_data *sc_control_data; 154 #define sc_txdescs sc_control_data->ecd_txdesc 155 #define sc_rxdescs sc_control_data->ecd_rxdesc 156 157 #ifdef EMAC_EVENT_COUNTERS 158 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 159 struct evcnt sc_ev_txintr; /* Tx interrupts */ 160 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 161 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 162 struct evcnt sc_ev_wol; /* Wake-On-Lan interrupts */ 163 struct evcnt sc_ev_serr; /* MAL system error interrupts */ 164 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 165 166 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 167 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 168 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 169 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 170 struct evcnt sc_ev_tu; /* Tx underrun */ 171 #endif /* EMAC_EVENT_COUNTERS */ 172 173 int sc_txfree; /* number of free Tx descriptors */ 174 int sc_txnext; /* next ready Tx descriptor */ 175 176 int sc_txsfree; /* number of free Tx jobs */ 177 int sc_txsnext; /* next ready Tx job */ 178 int sc_txsdirty; /* dirty Tx jobs */ 179 180 int sc_rxptr; /* next ready RX descriptor/descsoft */ 181 }; 182 183 #ifdef EMAC_EVENT_COUNTERS 184 #define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 185 #else 186 #define EMAC_EVCNT_INCR(ev) /* nothing */ 187 #endif 188 189 #define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 190 #define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 191 192 #define EMAC_CDTXSYNC(sc, x, n, ops) \ 193 do { \ 194 int __x, __n; \ 195 \ 196 __x = (x); \ 197 __n = (n); \ 198 \ 199 /* If it will wrap around, sync to the end of the ring. */ \ 200 if ((__x + __n) > EMAC_NTXDESC) { \ 201 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 202 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 203 (EMAC_NTXDESC - __x), (ops)); \ 204 __n -= (EMAC_NTXDESC - __x); \ 205 __x = 0; \ 206 } \ 207 \ 208 /* Now sync whatever is left. */ \ 209 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 210 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 211 } while (/*CONSTCOND*/0) 212 213 #define EMAC_CDRXSYNC(sc, x, ops) \ 214 do { \ 215 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 216 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 217 } while (/*CONSTCOND*/0) 218 219 #define EMAC_INIT_RXDESC(sc, x) \ 220 do { \ 221 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 222 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 223 struct mbuf *__m = __rxs->rxs_mbuf; \ 224 \ 225 /* \ 226 * Note: We scoot the packet forward 2 bytes in the buffer \ 227 * so that the payload after the Ethernet header is aligned \ 228 * to a 4-byte boundary. \ 229 */ \ 230 __m->m_data = __m->m_ext.ext_buf + 2; \ 231 \ 232 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 233 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 234 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 235 /* Set wrap on last descriptor. */ \ 236 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 237 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 238 } while (/*CONSTCOND*/0) 239 240 #define EMAC_WRITE(sc, reg, val) \ 241 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 242 #define EMAC_READ(sc, reg) \ 243 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 244 245 #define EMAC_SET_FILTER(aht, category) \ 246 do { \ 247 (aht)[3 - ((category) >> 4)] |= 1 << ((category) & 0xf); \ 248 } while (/*CONSTCOND*/0) 249 250 static int emac_match(struct device *, struct cfdata *, void *); 251 static void emac_attach(struct device *, struct device *, void *); 252 253 static int emac_add_rxbuf(struct emac_softc *, int); 254 static int emac_init(struct ifnet *); 255 static int emac_ioctl(struct ifnet *, u_long, void *); 256 static void emac_reset(struct emac_softc *); 257 static void emac_rxdrain(struct emac_softc *); 258 static int emac_txreap(struct emac_softc *); 259 static void emac_shutdown(void *); 260 static void emac_start(struct ifnet *); 261 static void emac_stop(struct ifnet *, int); 262 static void emac_watchdog(struct ifnet *); 263 static int emac_set_filter(struct emac_softc *); 264 265 static int emac_wol_intr(void *); 266 static int emac_serr_intr(void *); 267 static int emac_txeob_intr(void *); 268 static int emac_rxeob_intr(void *); 269 static int emac_txde_intr(void *); 270 static int emac_rxde_intr(void *); 271 static int emac_intr(void *); 272 273 static int emac_mii_readreg(struct device *, int, int); 274 static void emac_mii_statchg(struct device *); 275 static void emac_mii_tick(void *); 276 static uint32_t emac_mii_wait(struct emac_softc *); 277 static void emac_mii_writereg(struct device *, int, int, int); 278 279 int emac_copy_small = 0; 280 281 CFATTACH_DECL(emac, sizeof(struct emac_softc), 282 emac_match, emac_attach, NULL, NULL); 283 284 static int 285 emac_match(struct device *parent, struct cfdata *cf, void *aux) 286 { 287 struct opb_attach_args *oaa = aux; 288 289 /* match only on-chip ethernet devices */ 290 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 291 return (1); 292 293 return (0); 294 } 295 296 static void 297 emac_attach(struct device *parent, struct device *self, void *aux) 298 { 299 struct opb_attach_args *oaa = aux; 300 struct emac_softc *sc = (struct emac_softc *)self; 301 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 302 struct mii_data *mii = &sc->sc_mii; 303 bus_dma_segment_t seg; 304 int error, i, nseg; 305 const uint8_t *enaddr; 306 prop_data_t ea; 307 308 bus_space_map(oaa->opb_bt, oaa->opb_addr, EMAC_NREG, 0, &sc->sc_sh); 309 sc->sc_st = oaa->opb_bt; 310 sc->sc_dmat = oaa->opb_dmat; 311 312 printf(": 405GP EMAC\n"); 313 314 /* 315 * Set up Mode Register 1 - set receive and transmit FIFOs to maximum 316 * size, allow transmit of multiple packets (only channel 0 is used). 317 * 318 * XXX: Allow pause packets?? 319 */ 320 sc->sc_mr1 = MR1_RFS_4KB | MR1_TFS_2KB | MR1_TR0_MULTIPLE; 321 322 intr_establish(oaa->opb_irq , IST_LEVEL, IPL_NET, emac_wol_intr, sc); 323 intr_establish(oaa->opb_irq + 1, IST_LEVEL, IPL_NET, emac_serr_intr, sc); 324 intr_establish(oaa->opb_irq + 2, IST_LEVEL, IPL_NET, emac_txeob_intr, sc); 325 intr_establish(oaa->opb_irq + 3, IST_LEVEL, IPL_NET, emac_rxeob_intr, sc); 326 intr_establish(oaa->opb_irq + 4, IST_LEVEL, IPL_NET, emac_txde_intr, sc); 327 intr_establish(oaa->opb_irq + 5, IST_LEVEL, IPL_NET, emac_rxde_intr, sc); 328 intr_establish(oaa->opb_irq + 6, IST_LEVEL, IPL_NET, emac_intr, sc); 329 printf("%s: interrupting at irqs %d .. %d\n", sc->sc_dev.dv_xname, 330 oaa->opb_irq, oaa->opb_irq + 6); 331 332 /* 333 * Allocate the control data structures, and create and load the 334 * DMA map for it. 335 */ 336 if ((error = bus_dmamem_alloc(sc->sc_dmat, 337 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 338 printf("%s: unable to allocate control data, error = %d\n", 339 sc->sc_dev.dv_xname, error); 340 goto fail_0; 341 } 342 343 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 344 sizeof(struct emac_control_data), (void **)&sc->sc_control_data, 345 BUS_DMA_COHERENT)) != 0) { 346 printf("%s: unable to map control data, error = %d\n", 347 sc->sc_dev.dv_xname, error); 348 goto fail_1; 349 } 350 351 if ((error = bus_dmamap_create(sc->sc_dmat, 352 sizeof(struct emac_control_data), 1, 353 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 354 printf("%s: unable to create control data DMA map, " 355 "error = %d\n", sc->sc_dev.dv_xname, error); 356 goto fail_2; 357 } 358 359 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 360 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 361 0)) != 0) { 362 printf("%s: unable to load control data DMA map, error = %d\n", 363 sc->sc_dev.dv_xname, error); 364 goto fail_3; 365 } 366 367 /* 368 * Create the transmit buffer DMA maps. 369 */ 370 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 371 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 372 EMAC_NTXSEGS, MCLBYTES, 0, 0, 373 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 374 printf("%s: unable to create tx DMA map %d, " 375 "error = %d\n", sc->sc_dev.dv_xname, i, error); 376 goto fail_4; 377 } 378 } 379 380 /* 381 * Create the receive buffer DMA maps. 382 */ 383 for (i = 0; i < EMAC_NRXDESC; i++) { 384 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 385 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 386 printf("%s: unable to create rx DMA map %d, " 387 "error = %d\n", sc->sc_dev.dv_xname, i, error); 388 goto fail_5; 389 } 390 sc->sc_rxsoft[i].rxs_mbuf = NULL; 391 } 392 393 /* 394 * Reset the chip to a known state. 395 */ 396 emac_reset(sc); 397 398 /* Fetch the Ethernet address. */ 399 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 400 if (ea == NULL) { 401 printf("%s: unable to get mac-addr property\n", 402 sc->sc_dev.dv_xname); 403 return; 404 } 405 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 406 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 407 enaddr = prop_data_data_nocopy(ea); 408 409 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 410 ether_sprintf(enaddr)); 411 412 /* 413 * Initialise the media structures. 414 */ 415 mii->mii_ifp = ifp; 416 mii->mii_readreg = emac_mii_readreg; 417 mii->mii_writereg = emac_mii_writereg; 418 mii->mii_statchg = emac_mii_statchg; 419 420 sc->sc_ethercom.ec_mii = mii; 421 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 422 mii_attach(&sc->sc_dev, mii, 0xffffffff, 423 MII_PHY_ANY, MII_OFFSET_ANY, 0); 424 if (LIST_FIRST(&mii->mii_phys) == NULL) { 425 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 426 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 427 } else 428 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 429 430 ifp = &sc->sc_ethercom.ec_if; 431 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 432 ifp->if_softc = sc; 433 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 434 ifp->if_ioctl = emac_ioctl; 435 ifp->if_start = emac_start; 436 ifp->if_watchdog = emac_watchdog; 437 ifp->if_init = emac_init; 438 ifp->if_stop = emac_stop; 439 IFQ_SET_READY(&ifp->if_snd); 440 441 /* 442 * We can support 802.1Q VLAN-sized frames. 443 */ 444 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 445 446 /* 447 * Attach the interface. 448 */ 449 if_attach(ifp); 450 ether_ifattach(ifp, enaddr); 451 452 #ifdef EMAC_EVENT_COUNTERS 453 /* 454 * Attach the event counters. 455 */ 456 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 457 NULL, sc->sc_dev.dv_xname, "rxintr"); 458 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 459 NULL, sc->sc_dev.dv_xname, "txintr"); 460 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 461 NULL, sc->sc_dev.dv_xname, "rxde"); 462 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 463 NULL, sc->sc_dev.dv_xname, "txde"); 464 evcnt_attach_dynamic(&sc->sc_ev_wol, EVCNT_TYPE_INTR, 465 NULL, sc->sc_dev.dv_xname, "wol"); 466 evcnt_attach_dynamic(&sc->sc_ev_serr, EVCNT_TYPE_INTR, 467 NULL, sc->sc_dev.dv_xname, "serr"); 468 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 469 NULL, sc->sc_dev.dv_xname, "intr"); 470 471 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 472 NULL, sc->sc_dev.dv_xname, "txreap"); 473 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 474 NULL, sc->sc_dev.dv_xname, "txsstall"); 475 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 476 NULL, sc->sc_dev.dv_xname, "txdstall"); 477 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 478 NULL, sc->sc_dev.dv_xname, "txdrop"); 479 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 480 NULL, sc->sc_dev.dv_xname, "tu"); 481 #endif /* EMAC_EVENT_COUNTERS */ 482 483 /* 484 * Make sure the interface is shutdown during reboot. 485 */ 486 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 487 if (sc->sc_sdhook == NULL) 488 printf("%s: WARNING: unable to establish shutdown hook\n", 489 sc->sc_dev.dv_xname); 490 491 return; 492 493 /* 494 * Free any resources we've allocated during the failed attach 495 * attempt. Do this in reverse order and fall through. 496 */ 497 fail_5: 498 for (i = 0; i < EMAC_NRXDESC; i++) { 499 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 500 bus_dmamap_destroy(sc->sc_dmat, 501 sc->sc_rxsoft[i].rxs_dmamap); 502 } 503 fail_4: 504 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 505 if (sc->sc_txsoft[i].txs_dmamap != NULL) 506 bus_dmamap_destroy(sc->sc_dmat, 507 sc->sc_txsoft[i].txs_dmamap); 508 } 509 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 510 fail_3: 511 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 512 fail_2: 513 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 514 sizeof(struct emac_control_data)); 515 fail_1: 516 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 517 fail_0: 518 return; 519 } 520 521 /* 522 * Device shutdown routine. 523 */ 524 static void 525 emac_shutdown(void *arg) 526 { 527 struct emac_softc *sc = arg; 528 529 emac_stop(&sc->sc_ethercom.ec_if, 0); 530 } 531 532 /* ifnet interface function */ 533 static void 534 emac_start(struct ifnet *ifp) 535 { 536 struct emac_softc *sc = ifp->if_softc; 537 struct mbuf *m0; 538 struct emac_txsoft *txs; 539 bus_dmamap_t dmamap; 540 int error, firsttx, nexttx, lasttx, ofree, seg; 541 542 lasttx = 0; /* XXX gcc */ 543 544 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 545 return; 546 547 /* 548 * Remember the previous number of free descriptors. 549 */ 550 ofree = sc->sc_txfree; 551 552 /* 553 * Loop through the send queue, setting up transmit descriptors 554 * until we drain the queue, or use up all available transmit 555 * descriptors. 556 */ 557 for (;;) { 558 /* Grab a packet off the queue. */ 559 IFQ_POLL(&ifp->if_snd, m0); 560 if (m0 == NULL) 561 break; 562 563 /* 564 * Get a work queue entry. Reclaim used Tx descriptors if 565 * we are running low. 566 */ 567 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 568 emac_txreap(sc); 569 if (sc->sc_txsfree == 0) { 570 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 571 break; 572 } 573 } 574 575 txs = &sc->sc_txsoft[sc->sc_txsnext]; 576 dmamap = txs->txs_dmamap; 577 578 /* 579 * Load the DMA map. If this fails, the packet either 580 * didn't fit in the alloted number of segments, or we 581 * were short on resources. In this case, we'll copy 582 * and try again. 583 */ 584 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 585 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 586 if (error) { 587 if (error == EFBIG) { 588 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 589 printf("%s: Tx packet consumes too many " 590 "DMA segments, dropping...\n", 591 sc->sc_dev.dv_xname); 592 IFQ_DEQUEUE(&ifp->if_snd, m0); 593 m_freem(m0); 594 continue; 595 } 596 /* Short on resources, just stop for now. */ 597 break; 598 } 599 600 /* 601 * Ensure we have enough descriptors free to describe 602 * the packet. 603 */ 604 if (dmamap->dm_nsegs > sc->sc_txfree) { 605 /* 606 * Not enough free descriptors to transmit this 607 * packet. We haven't committed anything yet, 608 * so just unload the DMA map, put the packet 609 * back on the queue, and punt. Notify the upper 610 * layer that there are not more slots left. 611 * 612 */ 613 ifp->if_flags |= IFF_OACTIVE; 614 bus_dmamap_unload(sc->sc_dmat, dmamap); 615 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 616 break; 617 } 618 619 IFQ_DEQUEUE(&ifp->if_snd, m0); 620 621 /* 622 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 623 */ 624 625 /* Sync the DMA map. */ 626 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 627 BUS_DMASYNC_PREWRITE); 628 629 /* 630 * Store a pointer to the packet so that we can free it 631 * later. 632 */ 633 txs->txs_mbuf = m0; 634 txs->txs_firstdesc = sc->sc_txnext; 635 txs->txs_ndesc = dmamap->dm_nsegs; 636 637 /* 638 * Initialize the transmit descriptor. 639 */ 640 firsttx = sc->sc_txnext; 641 for (nexttx = sc->sc_txnext, seg = 0; 642 seg < dmamap->dm_nsegs; 643 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 644 /* 645 * If this is the first descriptor we're 646 * enqueueing, don't set the TX_READY bit just 647 * yet. That could cause a race condition. 648 * We'll do it below. 649 */ 650 sc->sc_txdescs[nexttx].md_data = 651 dmamap->dm_segs[seg].ds_addr; 652 sc->sc_txdescs[nexttx].md_data_len = 653 dmamap->dm_segs[seg].ds_len; 654 sc->sc_txdescs[nexttx].md_stat_ctrl = 655 (sc->sc_txdescs[nexttx].md_stat_ctrl & MAL_TX_WRAP) | 656 (nexttx == firsttx ? 0 : MAL_TX_READY) | 657 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 658 lasttx = nexttx; 659 } 660 661 /* Set the LAST bit on the last segment. */ 662 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 663 664 /* 665 * Set up last segment descriptor to send an interrupt after 666 * that descriptor is transmitted, and bypass existing Tx 667 * descriptor reaping method (for now...). 668 */ 669 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_INTERRUPT; 670 671 672 txs->txs_lastdesc = lasttx; 673 674 /* Sync the descriptors we're using. */ 675 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 676 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 677 678 /* 679 * The entire packet chain is set up. Give the 680 * first descriptor to the chip now. 681 */ 682 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 683 EMAC_CDTXSYNC(sc, firsttx, 1, 684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 685 /* 686 * Tell the EMAC that a new packet is available. 687 */ 688 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0); 689 690 /* Advance the tx pointer. */ 691 sc->sc_txfree -= txs->txs_ndesc; 692 sc->sc_txnext = nexttx; 693 694 sc->sc_txsfree--; 695 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 696 697 #if NBPFILTER > 0 698 /* 699 * Pass the packet to any BPF listeners. 700 */ 701 if (ifp->if_bpf) 702 bpf_mtap(ifp->if_bpf, m0); 703 #endif /* NBPFILTER > 0 */ 704 } 705 706 if (sc->sc_txfree == 0) { 707 /* No more slots left; notify upper layer. */ 708 ifp->if_flags |= IFF_OACTIVE; 709 } 710 711 if (sc->sc_txfree != ofree) { 712 /* Set a watchdog timer in case the chip flakes out. */ 713 ifp->if_timer = 5; 714 } 715 } 716 717 static int 718 emac_init(struct ifnet *ifp) 719 { 720 struct emac_softc *sc = ifp->if_softc; 721 struct emac_rxsoft *rxs; 722 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 723 int error, i; 724 725 error = 0; 726 727 /* Cancel any pending I/O. */ 728 emac_stop(ifp, 0); 729 730 /* Reset the chip to a known state. */ 731 emac_reset(sc); 732 733 /* 734 * Initialise the transmit descriptor ring. 735 */ 736 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 737 /* set wrap on last descriptor */ 738 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 739 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 740 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 741 sc->sc_txfree = EMAC_NTXDESC; 742 sc->sc_txnext = 0; 743 744 /* 745 * Initialise the transmit job descriptors. 746 */ 747 for (i = 0; i < EMAC_TXQUEUELEN; i++) 748 sc->sc_txsoft[i].txs_mbuf = NULL; 749 sc->sc_txsfree = EMAC_TXQUEUELEN; 750 sc->sc_txsnext = 0; 751 sc->sc_txsdirty = 0; 752 753 /* 754 * Initialise the receiver descriptor and receive job 755 * descriptor rings. 756 */ 757 for (i = 0; i < EMAC_NRXDESC; i++) { 758 rxs = &sc->sc_rxsoft[i]; 759 if (rxs->rxs_mbuf == NULL) { 760 if ((error = emac_add_rxbuf(sc, i)) != 0) { 761 printf("%s: unable to allocate or map rx " 762 "buffer %d, error = %d\n", 763 sc->sc_dev.dv_xname, i, error); 764 /* 765 * XXX Should attempt to run with fewer receive 766 * XXX buffers instead of just failing. 767 */ 768 emac_rxdrain(sc); 769 goto out; 770 } 771 } else 772 EMAC_INIT_RXDESC(sc, i); 773 } 774 sc->sc_rxptr = 0; 775 776 /* 777 * Set the current media. 778 */ 779 if ((error = ether_mediachange(ifp)) != 0) 780 goto out; 781 782 /* 783 * Give the transmit and receive rings to the MAL. 784 */ 785 mtdcr(DCR_MAL0_TXCTP0R, EMAC_CDTXADDR(sc, 0)); 786 mtdcr(DCR_MAL0_RXCTP0R, EMAC_CDRXADDR(sc, 0)); 787 788 /* 789 * Load the MAC address. 790 */ 791 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 792 EMAC_WRITE(sc, EMAC_IALR, 793 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 794 795 /* 796 * Set the receive channel buffer size (in units of 16 bytes). 797 */ 798 #if MCLBYTES > (4096 - 16) /* XXX! */ 799 # error MCLBYTES > max rx channel buffer size 800 #endif 801 mtdcr(DCR_MAL0_RCBS0, MCLBYTES / 16); 802 803 /* Set fifos, media modes. */ 804 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 805 806 /* 807 * Enable Individual and (possibly) Broadcast Address modes, 808 * runt packets, and strip padding. 809 */ 810 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | 811 (ifp->if_flags & IFF_PROMISC ? RMR_PME : 0) | 812 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 813 814 /* 815 * Set multicast filter. 816 */ 817 emac_set_filter(sc); 818 819 /* 820 * Set low- and urgent-priority request thresholds. 821 */ 822 EMAC_WRITE(sc, EMAC_TMR1, 823 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 824 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 825 /* 826 * Set Transmit Request Threshold Register. 827 */ 828 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 829 830 /* 831 * Set high and low receive watermarks. 832 */ 833 EMAC_WRITE(sc, EMAC_RWMR, 834 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 835 836 /* 837 * Set frame gap. 838 */ 839 EMAC_WRITE(sc, EMAC_IPGVR, 8); 840 841 /* 842 * Set interrupt status enable bits for EMAC and MAL. 843 */ 844 EMAC_WRITE(sc, EMAC_ISER, 845 ISR_BP | ISR_SE | ISR_ALE | ISR_BFCS | ISR_PTLE | ISR_ORE | ISR_IRE); 846 mtdcr(DCR_MAL0_IER, MAL0_IER_DE | MAL0_IER_NWE | MAL0_IER_TO | 847 MAL0_IER_OPB | MAL0_IER_PLB); 848 849 /* 850 * Enable the transmit and receive channel on the MAL. 851 */ 852 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 853 mtdcr(DCR_MAL0_TXCASR, MAL0_TXCASR_CHAN0); 854 855 /* 856 * Enable the transmit and receive channel on the EMAC. 857 */ 858 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 859 860 /* 861 * Start the one second MII clock. 862 */ 863 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 864 865 /* 866 * ... all done! 867 */ 868 ifp->if_flags |= IFF_RUNNING; 869 ifp->if_flags &= ~IFF_OACTIVE; 870 871 out: 872 if (error) { 873 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 874 ifp->if_timer = 0; 875 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 876 } 877 return (error); 878 } 879 880 static int 881 emac_add_rxbuf(struct emac_softc *sc, int idx) 882 { 883 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 884 struct mbuf *m; 885 int error; 886 887 MGETHDR(m, M_DONTWAIT, MT_DATA); 888 if (m == NULL) 889 return (ENOBUFS); 890 891 MCLGET(m, M_DONTWAIT); 892 if ((m->m_flags & M_EXT) == 0) { 893 m_freem(m); 894 return (ENOBUFS); 895 } 896 897 if (rxs->rxs_mbuf != NULL) 898 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 899 900 rxs->rxs_mbuf = m; 901 902 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 903 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 904 if (error) { 905 printf("%s: can't load rx DMA map %d, error = %d\n", 906 sc->sc_dev.dv_xname, idx, error); 907 panic("emac_add_rxbuf"); /* XXX */ 908 } 909 910 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 911 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 912 913 EMAC_INIT_RXDESC(sc, idx); 914 915 return (0); 916 } 917 918 /* ifnet interface function */ 919 static void 920 emac_watchdog(struct ifnet *ifp) 921 { 922 struct emac_softc *sc = ifp->if_softc; 923 924 /* 925 * Since we're not interrupting every packet, sweep 926 * up before we report an error. 927 */ 928 emac_txreap(sc); 929 930 if (sc->sc_txfree != EMAC_NTXDESC) { 931 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 932 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 933 sc->sc_txnext); 934 ifp->if_oerrors++; 935 936 /* Reset the interface. */ 937 (void)emac_init(ifp); 938 } else if (ifp->if_flags & IFF_DEBUG) 939 printf("%s: recovered from device timeout\n", 940 sc->sc_dev.dv_xname); 941 942 /* try to get more packets going */ 943 emac_start(ifp); 944 } 945 946 static void 947 emac_rxdrain(struct emac_softc *sc) 948 { 949 struct emac_rxsoft *rxs; 950 int i; 951 952 for (i = 0; i < EMAC_NRXDESC; i++) { 953 rxs = &sc->sc_rxsoft[i]; 954 if (rxs->rxs_mbuf != NULL) { 955 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 956 m_freem(rxs->rxs_mbuf); 957 rxs->rxs_mbuf = NULL; 958 } 959 } 960 } 961 962 /* ifnet interface function */ 963 static void 964 emac_stop(struct ifnet *ifp, int disable) 965 { 966 struct emac_softc *sc = ifp->if_softc; 967 struct emac_txsoft *txs; 968 int i; 969 970 /* Stop the one second clock. */ 971 callout_stop(&sc->sc_callout); 972 973 /* Down the MII */ 974 mii_down(&sc->sc_mii); 975 976 /* Disable interrupts. */ 977 #if 0 /* Can't disable MAL interrupts without a reset... */ 978 EMAC_WRITE(sc, EMAC_ISER, 0); 979 #endif 980 mtdcr(DCR_MAL0_IER, 0); 981 982 /* Disable the receive and transmit channels. */ 983 mtdcr(DCR_MAL0_RXCARR, MAL0_RXCARR_CHAN0); 984 mtdcr(DCR_MAL0_TXCARR, MAL0_TXCARR_CHAN0 | MAL0_TXCARR_CHAN1); 985 986 /* Disable the transmit enable and receive MACs. */ 987 EMAC_WRITE(sc, EMAC_MR0, 988 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 989 990 /* Release any queued transmit buffers. */ 991 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 992 txs = &sc->sc_txsoft[i]; 993 if (txs->txs_mbuf != NULL) { 994 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 995 m_freem(txs->txs_mbuf); 996 txs->txs_mbuf = NULL; 997 } 998 } 999 1000 if (disable) 1001 emac_rxdrain(sc); 1002 1003 /* 1004 * Mark the interface down and cancel the watchdog timer. 1005 */ 1006 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1007 ifp->if_timer = 0; 1008 } 1009 1010 /* ifnet interface function */ 1011 static int 1012 emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1013 { 1014 struct emac_softc *sc = ifp->if_softc; 1015 int s, error; 1016 1017 s = splnet(); 1018 1019 error = ether_ioctl(ifp, cmd, data); 1020 if (error == ENETRESET) { 1021 /* 1022 * Multicast list has changed; set the hardware filter 1023 * accordingly. 1024 */ 1025 if (ifp->if_flags & IFF_RUNNING) 1026 error = emac_set_filter(sc); 1027 else 1028 error = 0; 1029 } 1030 1031 /* try to get more packets going */ 1032 emac_start(ifp); 1033 1034 splx(s); 1035 return (error); 1036 } 1037 1038 static void 1039 emac_reset(struct emac_softc *sc) 1040 { 1041 1042 /* reset the MAL */ 1043 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR); 1044 1045 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1046 delay(5); 1047 1048 /* XXX: check if MR0_SRST is clear until a timeout instead? */ 1049 EMAC_WRITE(sc, EMAC_MR0, EMAC_READ(sc, EMAC_MR0) & ~MR0_SRST); 1050 1051 /* XXX clear interrupts in EMAC_ISR just to be sure?? */ 1052 1053 /* set the MAL config register */ 1054 mtdcr(DCR_MAL0_CFG, MAL0_CFG_PLBB | MAL0_CFG_OPBBL | MAL0_CFG_LEA | 1055 MAL0_CFG_SD | MAL0_CFG_PLBLT); 1056 } 1057 1058 static int 1059 emac_set_filter(struct emac_softc *sc) 1060 { 1061 struct ether_multistep step; 1062 struct ether_multi *enm; 1063 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1064 uint32_t rmr, crc, gaht[4] = {0, 0, 0, 0}; 1065 int category, cnt = 0; 1066 1067 rmr = EMAC_READ(sc, EMAC_RMR); 1068 rmr &= ~(RMR_PMME | RMR_MAE); 1069 ifp->if_flags &= ~IFF_ALLMULTI; 1070 1071 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1072 while (enm != NULL) { 1073 if (memcmp(enm->enm_addrlo, 1074 enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1075 /* 1076 * We must listen to a range of multicast addresses. 1077 * For now, just accept all multicasts, rather than 1078 * trying to set only those filter bits needed to match 1079 * the range. (At this time, the only use of address 1080 * ranges is for IP multicast routing, for which the 1081 * range is big enough to require all bits set.) 1082 */ 1083 gaht[0] = gaht[1] = gaht[2] = gaht[3] = 0xffff; 1084 break; 1085 } 1086 1087 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1088 1089 /* Just want the 6 most significant bits. */ 1090 category = crc >> 26; 1091 EMAC_SET_FILTER(gaht, category); 1092 1093 ETHER_NEXT_MULTI(step, enm); 1094 cnt++; 1095 } 1096 1097 if ((gaht[0] & gaht[1] & gaht[2] & gaht[3]) == 0xffff) { 1098 /* All categories are true. */ 1099 ifp->if_flags |= IFF_ALLMULTI; 1100 rmr |= RMR_PMME; 1101 } else if (cnt != 0) { 1102 /* Some categories are true. */ 1103 EMAC_WRITE(sc, EMAC_GAHT1, gaht[0]); 1104 EMAC_WRITE(sc, EMAC_GAHT2, gaht[1]); 1105 EMAC_WRITE(sc, EMAC_GAHT3, gaht[2]); 1106 EMAC_WRITE(sc, EMAC_GAHT4, gaht[3]); 1107 1108 rmr |= RMR_MAE; 1109 } 1110 EMAC_WRITE(sc, EMAC_RMR, rmr); 1111 1112 return 0; 1113 } 1114 1115 /* 1116 * EMAC General interrupt handler 1117 */ 1118 static int 1119 emac_intr(void *arg) 1120 { 1121 struct emac_softc *sc = arg; 1122 uint32_t status; 1123 1124 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 1125 status = EMAC_READ(sc, EMAC_ISR); 1126 1127 /* Clear the interrupt status bits. */ 1128 EMAC_WRITE(sc, EMAC_ISR, status); 1129 1130 return (0); 1131 } 1132 1133 /* 1134 * EMAC Wake-On-LAN interrupt handler 1135 */ 1136 static int 1137 emac_wol_intr(void *arg) 1138 { 1139 struct emac_softc *sc = arg; 1140 1141 EMAC_EVCNT_INCR(&sc->sc_ev_wol); 1142 printf("%s: emac_wol_intr\n", sc->sc_dev.dv_xname); 1143 return (0); 1144 } 1145 1146 /* 1147 * MAL System ERRor interrupt handler 1148 */ 1149 static int 1150 emac_serr_intr(void *arg) 1151 { 1152 #ifdef EMAC_EVENT_COUNTERS 1153 struct emac_softc *sc = arg; 1154 #endif 1155 u_int32_t esr; 1156 1157 EMAC_EVCNT_INCR(&sc->sc_ev_serr); 1158 esr = mfdcr(DCR_MAL0_ESR); 1159 1160 /* Clear the interrupt status bits. */ 1161 mtdcr(DCR_MAL0_ESR, esr); 1162 return (0); 1163 } 1164 1165 /* 1166 * MAL Transmit End-Of-Buffer interrupt handler. 1167 * NOTE: This shouldn't be called! 1168 */ 1169 static int 1170 emac_txeob_intr(void *arg) 1171 { 1172 struct emac_softc *sc = arg; 1173 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1174 int handled; 1175 1176 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1177 handled = emac_txreap(arg); 1178 1179 /* try to get more packets going */ 1180 emac_start(ifp); 1181 1182 return (handled); 1183 1184 } 1185 1186 /* 1187 * Reap completed Tx descriptors. 1188 */ 1189 static int 1190 emac_txreap(struct emac_softc *sc) 1191 { 1192 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1193 struct emac_txsoft *txs; 1194 int handled, i; 1195 u_int32_t txstat; 1196 1197 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1198 handled = 0; 1199 1200 /* Clear the interrupt */ 1201 mtdcr(DCR_MAL0_TXEOBISR, mfdcr(DCR_MAL0_TXEOBISR)); 1202 1203 ifp->if_flags &= ~IFF_OACTIVE; 1204 1205 /* 1206 * Go through our Tx list and free mbufs for those 1207 * frames that have been transmitted. 1208 */ 1209 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1210 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1211 txs = &sc->sc_txsoft[i]; 1212 1213 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1214 txs->txs_dmamap->dm_nsegs, 1215 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1216 1217 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1218 if (txstat & MAL_TX_READY) 1219 break; 1220 1221 handled = 1; 1222 1223 /* 1224 * Check for errors and collisions. 1225 */ 1226 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1227 ifp->if_oerrors++; 1228 1229 #ifdef EMAC_EVENT_COUNTERS 1230 if (txstat & EMAC_TXS_UR) 1231 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1232 #endif /* EMAC_EVENT_COUNTERS */ 1233 1234 if (txstat & (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1235 if (txstat & EMAC_TXS_EC) 1236 ifp->if_collisions += 16; 1237 else if (txstat & EMAC_TXS_MC) 1238 ifp->if_collisions += 2; /* XXX? */ 1239 else if (txstat & EMAC_TXS_SC) 1240 ifp->if_collisions++; 1241 if (txstat & EMAC_TXS_LC) 1242 ifp->if_collisions++; 1243 } else 1244 ifp->if_opackets++; 1245 1246 if (ifp->if_flags & IFF_DEBUG) { 1247 if (txstat & EMAC_TXS_ED) 1248 printf("%s: excessive deferral\n", 1249 sc->sc_dev.dv_xname); 1250 if (txstat & EMAC_TXS_EC) 1251 printf("%s: excessive collisions\n", 1252 sc->sc_dev.dv_xname); 1253 } 1254 1255 sc->sc_txfree += txs->txs_ndesc; 1256 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1257 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1258 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1259 m_freem(txs->txs_mbuf); 1260 txs->txs_mbuf = NULL; 1261 } 1262 1263 /* Update the dirty transmit buffer pointer. */ 1264 sc->sc_txsdirty = i; 1265 1266 /* 1267 * If there are no more pending transmissions, cancel the watchdog 1268 * timer. 1269 */ 1270 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1271 ifp->if_timer = 0; 1272 1273 return (handled); 1274 } 1275 1276 /* 1277 * MAL Receive End-Of-Buffer interrupt handler 1278 */ 1279 static int 1280 emac_rxeob_intr(void *arg) 1281 { 1282 struct emac_softc *sc = arg; 1283 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1284 struct emac_rxsoft *rxs; 1285 struct mbuf *m; 1286 u_int32_t rxstat; 1287 int i, len; 1288 1289 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1290 1291 /* Clear the interrupt */ 1292 mtdcr(DCR_MAL0_RXEOBISR, mfdcr(DCR_MAL0_RXEOBISR)); 1293 1294 for (i = sc->sc_rxptr;; i = EMAC_NEXTRX(i)) { 1295 rxs = &sc->sc_rxsoft[i]; 1296 1297 EMAC_CDRXSYNC(sc, i, 1298 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1299 1300 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1301 1302 if (rxstat & MAL_RX_EMPTY) 1303 /* 1304 * We have processed all of the receive buffers. 1305 */ 1306 break; 1307 1308 /* 1309 * If an error occurred, update stats, clear the status 1310 * word, and leave the packet buffer in place. It will 1311 * simply be reused the next time the ring comes around. 1312 */ 1313 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1314 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1315 EMAC_RXS_IRE)) { 1316 #define PRINTERR(bit, str) \ 1317 if (rxstat & (bit)) \ 1318 printf("%s: receive error: %s\n", \ 1319 sc->sc_dev.dv_xname, str) 1320 ifp->if_ierrors++; 1321 PRINTERR(EMAC_RXS_OE, "overrun error"); 1322 PRINTERR(EMAC_RXS_BP, "bad packet"); 1323 PRINTERR(EMAC_RXS_RP, "runt packet"); 1324 PRINTERR(EMAC_RXS_SE, "short event"); 1325 PRINTERR(EMAC_RXS_AE, "alignment error"); 1326 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1327 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1328 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1329 PRINTERR(EMAC_RXS_IRE, "in range error"); 1330 #undef PRINTERR 1331 EMAC_INIT_RXDESC(sc, i); 1332 continue; 1333 } 1334 1335 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1336 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1337 1338 /* 1339 * No errors; receive the packet. Note, the 405GP emac 1340 * includes the CRC with every packet. 1341 */ 1342 len = sc->sc_rxdescs[i].md_data_len - ETHER_CRC_LEN; 1343 1344 /* 1345 * If the packet is small enough to fit in a 1346 * single header mbuf, allocate one and copy 1347 * the data into it. This greatly reduces 1348 * memory consumption when we receive lots 1349 * of small packets. 1350 * 1351 * Otherwise, we add a new buffer to the receive 1352 * chain. If this fails, we drop the packet and 1353 * recycle the old buffer. 1354 */ 1355 if (emac_copy_small != 0 && len <= MHLEN) { 1356 MGETHDR(m, M_DONTWAIT, MT_DATA); 1357 if (m == NULL) 1358 goto dropit; 1359 memcpy(mtod(m, void *), 1360 mtod(rxs->rxs_mbuf, void *), len); 1361 EMAC_INIT_RXDESC(sc, i); 1362 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1363 rxs->rxs_dmamap->dm_mapsize, 1364 BUS_DMASYNC_PREREAD); 1365 } else { 1366 m = rxs->rxs_mbuf; 1367 if (emac_add_rxbuf(sc, i) != 0) { 1368 dropit: 1369 ifp->if_ierrors++; 1370 EMAC_INIT_RXDESC(sc, i); 1371 bus_dmamap_sync(sc->sc_dmat, 1372 rxs->rxs_dmamap, 0, 1373 rxs->rxs_dmamap->dm_mapsize, 1374 BUS_DMASYNC_PREREAD); 1375 continue; 1376 } 1377 } 1378 1379 ifp->if_ipackets++; 1380 m->m_pkthdr.rcvif = ifp; 1381 m->m_pkthdr.len = m->m_len = len; 1382 1383 #if NBPFILTER > 0 1384 /* 1385 * Pass this up to any BPF listeners, but only 1386 * pass if up the stack if it's for us. 1387 */ 1388 if (ifp->if_bpf) 1389 bpf_mtap(ifp->if_bpf, m); 1390 #endif /* NBPFILTER > 0 */ 1391 1392 /* Pass it on. */ 1393 (*ifp->if_input)(ifp, m); 1394 } 1395 1396 /* Update the receive pointer. */ 1397 sc->sc_rxptr = i; 1398 1399 return (0); 1400 } 1401 1402 /* 1403 * MAL Transmit Descriptor Error interrupt handler 1404 */ 1405 static int 1406 emac_txde_intr(void *arg) 1407 { 1408 struct emac_softc *sc = arg; 1409 1410 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1411 printf("%s: emac_txde_intr\n", sc->sc_dev.dv_xname); 1412 return (0); 1413 } 1414 1415 /* 1416 * MAL Receive Descriptor Error interrupt handler 1417 */ 1418 static int 1419 emac_rxde_intr(void *arg) 1420 { 1421 int i; 1422 struct emac_softc *sc = arg; 1423 1424 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1425 printf("%s: emac_rxde_intr\n", sc->sc_dev.dv_xname); 1426 /* 1427 * XXX! 1428 * This is a bit drastic; we just drop all descriptors that aren't 1429 * "clean". We should probably send any that are up the stack. 1430 */ 1431 for (i = 0; i < EMAC_NRXDESC; i++) { 1432 EMAC_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1433 1434 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) { 1435 EMAC_INIT_RXDESC(sc, i); 1436 } 1437 1438 } 1439 1440 /* Reenable the receive channel */ 1441 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 1442 1443 /* Clear the interrupt */ 1444 mtdcr(DCR_MAL0_RXDEIR, mfdcr(DCR_MAL0_RXDEIR)); 1445 1446 return (0); 1447 } 1448 1449 static uint32_t 1450 emac_mii_wait(struct emac_softc *sc) 1451 { 1452 int i; 1453 uint32_t reg; 1454 1455 /* wait for PHY data transfer to complete */ 1456 i = 0; 1457 while ((reg = EMAC_READ(sc, EMAC_STACR) & STACR_OC) == 0) { 1458 delay(7); 1459 if (i++ > 5) { 1460 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1461 return (0); 1462 } 1463 } 1464 return (reg); 1465 } 1466 1467 static int 1468 emac_mii_readreg(struct device *self, int phy, int reg) 1469 { 1470 struct emac_softc *sc = (struct emac_softc *)self; 1471 uint32_t sta_reg; 1472 1473 /* wait for PHY data transfer to complete */ 1474 if (emac_mii_wait(sc) == 0) 1475 return (0); 1476 1477 sta_reg = reg << STACR_PRASHIFT; 1478 sta_reg |= STACR_READ; 1479 sta_reg |= phy << STACR_PCDASHIFT; 1480 1481 sta_reg &= ~STACR_OPBC_MASK; 1482 sta_reg |= STACR_OPBC_50MHZ; 1483 1484 1485 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1486 1487 if ((sta_reg = emac_mii_wait(sc)) == 0) 1488 return (0); 1489 sta_reg = EMAC_READ(sc, EMAC_STACR); 1490 if ((sta_reg & STACR_PHYE) != 0) 1491 return (0); 1492 return (sta_reg >> STACR_PHYDSHIFT); 1493 } 1494 1495 static void 1496 emac_mii_writereg(struct device *self, int phy, int reg, int val) 1497 { 1498 struct emac_softc *sc = (struct emac_softc *)self; 1499 uint32_t sta_reg; 1500 1501 /* wait for PHY data transfer to complete */ 1502 if (emac_mii_wait(sc) == 0) 1503 return; 1504 1505 sta_reg = reg << STACR_PRASHIFT; 1506 sta_reg |= STACR_WRITE; 1507 sta_reg |= phy << STACR_PCDASHIFT; 1508 1509 sta_reg &= ~STACR_OPBC_MASK; 1510 sta_reg |= STACR_OPBC_50MHZ; 1511 1512 sta_reg |= val << STACR_PHYDSHIFT; 1513 1514 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1515 1516 if ((sta_reg = emac_mii_wait(sc)) == 0) 1517 return; 1518 if ((sta_reg & STACR_PHYE) != 0) 1519 /* error */ 1520 return; 1521 } 1522 1523 static void 1524 emac_mii_statchg(struct device *self) 1525 { 1526 struct emac_softc *sc = (void *)self; 1527 1528 if (sc->sc_mii.mii_media_active & IFM_FDX) 1529 sc->sc_mr1 |= MR1_FDE; 1530 else 1531 sc->sc_mr1 &= ~(MR1_FDE | MR1_EIFC); 1532 1533 /* XXX 802.1x flow-control? */ 1534 1535 /* 1536 * MR1 can only be written immediately after a reset... 1537 */ 1538 emac_reset(sc); 1539 } 1540 1541 static void 1542 emac_mii_tick(void *arg) 1543 { 1544 struct emac_softc *sc = arg; 1545 int s; 1546 1547 if (!device_is_active(&sc->sc_dev)) 1548 return; 1549 1550 s = splnet(); 1551 mii_tick(&sc->sc_mii); 1552 splx(s); 1553 1554 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1555 } 1556