1 /* $NetBSD: if_emac.c,v 1.55 2021/02/27 20:43:58 rin Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * emac(4) supports following ibm4xx's EMACs. 40 * XXXX: ZMII and 'TCP Accelaration Hardware' not support yet... 41 * 42 * tested 43 * ------ 44 * 405EP - 10/100 x2 45 * 405EX/EXr o 10/100/1000 x2 (EXr x1), STA v2, 256bit hash-Table, RGMII 46 * 405GP/GPr o 10/100 47 * 440EP - 10/100 x2, ZMII 48 * 440GP - 10/100 x2, ZMII 49 * 440GX - 10/100/1000 x4, ZMII/RGMII(ch 2, 3), TAH(ch 2, 3) 50 * 440SP - 10/100/1000 51 * 440SPe - 10/100/1000, STA v2 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.55 2021/02/27 20:43:58 rin Exp $"); 56 57 #ifdef _KERNEL_OPT 58 #include "opt_emac.h" 59 #endif 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/mbuf.h> 64 #include <sys/kernel.h> 65 #include <sys/socket.h> 66 #include <sys/ioctl.h> 67 #include <sys/cpu.h> 68 #include <sys/device.h> 69 70 #include <sys/rndsource.h> 71 72 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #include <net/bpf.h> 80 81 #include <powerpc/ibm4xx/cpu.h> 82 #include <powerpc/ibm4xx/dcr4xx.h> 83 #include <powerpc/ibm4xx/mal405gp.h> 84 #include <powerpc/ibm4xx/dev/emacreg.h> 85 #include <powerpc/ibm4xx/dev/if_emacreg.h> 86 #include <powerpc/ibm4xx/dev/if_emacvar.h> 87 #include <powerpc/ibm4xx/dev/malvar.h> 88 #include <powerpc/ibm4xx/dev/opbreg.h> 89 #include <powerpc/ibm4xx/dev/opbvar.h> 90 #include <powerpc/ibm4xx/dev/plbvar.h> 91 #if defined(EMAC_ZMII_PHY) || defined(EMAC_RGMII_PHY) 92 #include <powerpc/ibm4xx/dev/rmiivar.h> 93 #endif 94 95 #include <dev/mii/miivar.h> 96 97 #include "locators.h" 98 99 100 /* 101 * Transmit descriptor list size. There are two Tx channels, each with 102 * up to 256 hardware descriptors available. We currently use one Tx 103 * channel. We tell the upper layers that they can queue a lot of 104 * packets, and we go ahead and manage up to 64 of them at a time. We 105 * allow up to 16 DMA segments per packet. 106 */ 107 #define EMAC_NTXSEGS 16 108 #define EMAC_TXQUEUELEN 64 109 #define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 110 #define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 111 #define EMAC_NTXDESC 256 112 #define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 113 #define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 114 #define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 115 116 /* 117 * Receive descriptor list size. There is one Rx channel with up to 256 118 * hardware descriptors available. We allocate 64 receive descriptors, 119 * each with a 2k buffer (MCLBYTES). 120 */ 121 #define EMAC_NRXDESC 64 122 #define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 123 #define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 124 #define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 125 126 /* 127 * Transmit/receive descriptors that are DMA'd to the EMAC. 128 */ 129 struct emac_control_data { 130 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 131 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 132 }; 133 134 #define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 135 #define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 136 #define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 137 138 /* 139 * Software state for transmit jobs. 140 */ 141 struct emac_txsoft { 142 struct mbuf *txs_mbuf; /* head of mbuf chain */ 143 bus_dmamap_t txs_dmamap; /* our DMA map */ 144 int txs_firstdesc; /* first descriptor in packet */ 145 int txs_lastdesc; /* last descriptor in packet */ 146 int txs_ndesc; /* # of descriptors used */ 147 }; 148 149 /* 150 * Software state for receive descriptors. 151 */ 152 struct emac_rxsoft { 153 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 154 bus_dmamap_t rxs_dmamap; /* our DMA map */ 155 }; 156 157 /* 158 * Software state per device. 159 */ 160 struct emac_softc { 161 device_t sc_dev; /* generic device information */ 162 int sc_instance; /* instance no. */ 163 bus_space_tag_t sc_st; /* bus space tag */ 164 bus_space_handle_t sc_sh; /* bus space handle */ 165 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 166 struct ethercom sc_ethercom; /* ethernet common data */ 167 void *sc_sdhook; /* shutdown hook */ 168 void *sc_powerhook; /* power management hook */ 169 170 struct mii_data sc_mii; /* MII/media information */ 171 struct callout sc_callout; /* tick callout */ 172 173 uint32_t sc_mr1; /* copy of Mode Register 1 */ 174 uint32_t sc_stacr_read; /* Read opcode of STAOPC of STACR */ 175 uint32_t sc_stacr_write; /* Write opcode of STAOPC of STACR */ 176 uint32_t sc_stacr_bits; /* misc bits of STACR */ 177 bool sc_stacr_completed; /* Operation completed of STACR */ 178 int sc_htsize; /* Hash Table size */ 179 180 bus_dmamap_t sc_cddmamap; /* control data dma map */ 181 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 182 183 /* Software state for transmit/receive descriptors. */ 184 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 185 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 186 187 /* Control data structures. */ 188 struct emac_control_data *sc_control_data; 189 #define sc_txdescs sc_control_data->ecd_txdesc 190 #define sc_rxdescs sc_control_data->ecd_rxdesc 191 192 #ifdef EMAC_EVENT_COUNTERS 193 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 194 struct evcnt sc_ev_txintr; /* Tx interrupts */ 195 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 196 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 197 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 198 199 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 200 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 201 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 202 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 203 struct evcnt sc_ev_tu; /* Tx underrun */ 204 #endif /* EMAC_EVENT_COUNTERS */ 205 206 int sc_txfree; /* number of free Tx descriptors */ 207 int sc_txnext; /* next ready Tx descriptor */ 208 209 int sc_txsfree; /* number of free Tx jobs */ 210 int sc_txsnext; /* next ready Tx job */ 211 int sc_txsdirty; /* dirty Tx jobs */ 212 213 int sc_rxptr; /* next ready RX descriptor/descsoft */ 214 215 krndsource_t rnd_source; /* random source */ 216 217 void (*sc_rmii_enable)(device_t, int); /* reduced MII enable */ 218 void (*sc_rmii_disable)(device_t, int); /* reduced MII disable*/ 219 void (*sc_rmii_speed)(device_t, int, int); /* reduced MII speed */ 220 }; 221 222 #ifdef EMAC_EVENT_COUNTERS 223 #define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 224 #else 225 #define EMAC_EVCNT_INCR(ev) /* nothing */ 226 #endif 227 228 #define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 229 #define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 230 231 #define EMAC_CDTXSYNC(sc, x, n, ops) \ 232 do { \ 233 int __x, __n; \ 234 \ 235 __x = (x); \ 236 __n = (n); \ 237 \ 238 /* If it will wrap around, sync to the end of the ring. */ \ 239 if ((__x + __n) > EMAC_NTXDESC) { \ 240 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 241 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 242 (EMAC_NTXDESC - __x), (ops)); \ 243 __n -= (EMAC_NTXDESC - __x); \ 244 __x = 0; \ 245 } \ 246 \ 247 /* Now sync whatever is left. */ \ 248 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 249 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 250 } while (/*CONSTCOND*/0) 251 252 #define EMAC_CDRXSYNC(sc, x, ops) \ 253 do { \ 254 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 255 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 256 } while (/*CONSTCOND*/0) 257 258 #define EMAC_INIT_RXDESC(sc, x) \ 259 do { \ 260 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 261 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 262 struct mbuf *__m = __rxs->rxs_mbuf; \ 263 \ 264 /* \ 265 * Note: We scoot the packet forward 2 bytes in the buffer \ 266 * so that the payload after the Ethernet header is aligned \ 267 * to a 4-byte boundary. \ 268 */ \ 269 __m->m_data = __m->m_ext.ext_buf + 2; \ 270 \ 271 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 272 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 273 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 274 /* Set wrap on last descriptor. */ \ 275 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 276 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 277 } while (/*CONSTCOND*/0) 278 279 #define EMAC_WRITE(sc, reg, val) \ 280 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 281 #define EMAC_READ(sc, reg) \ 282 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 283 284 #define EMAC_SET_FILTER(aht, crc) \ 285 do { \ 286 (aht)[3 - (((crc) >> 26) >> 4)] |= 1 << (((crc) >> 26) & 0xf); \ 287 } while (/*CONSTCOND*/0) 288 #define EMAC_SET_FILTER256(aht, crc) \ 289 do { \ 290 (aht)[7 - (((crc) >> 24) >> 5)] |= 1 << (((crc) >> 24) & 0x1f); \ 291 } while (/*CONSTCOND*/0) 292 293 static int emac_match(device_t, cfdata_t, void *); 294 static void emac_attach(device_t, device_t, void *); 295 296 static int emac_intr(void *); 297 static void emac_shutdown(void *); 298 299 static void emac_start(struct ifnet *); 300 static int emac_ioctl(struct ifnet *, u_long, void *); 301 static int emac_init(struct ifnet *); 302 static void emac_stop(struct ifnet *, int); 303 static void emac_watchdog(struct ifnet *); 304 305 static int emac_add_rxbuf(struct emac_softc *, int); 306 static void emac_rxdrain(struct emac_softc *); 307 static int emac_set_filter(struct emac_softc *); 308 static int emac_txreap(struct emac_softc *); 309 310 static void emac_soft_reset(struct emac_softc *); 311 static void emac_smart_reset(struct emac_softc *); 312 313 static int emac_mii_readreg(device_t, int, int, uint16_t *); 314 static int emac_mii_writereg(device_t, int, int, uint16_t); 315 static void emac_mii_statchg(struct ifnet *); 316 static uint32_t emac_mii_wait(struct emac_softc *); 317 static void emac_mii_tick(void *); 318 319 int emac_copy_small = 0; 320 321 CFATTACH_DECL_NEW(emac, sizeof(struct emac_softc), 322 emac_match, emac_attach, NULL, NULL); 323 324 325 static int 326 emac_match(device_t parent, cfdata_t cf, void *aux) 327 { 328 struct opb_attach_args *oaa = aux; 329 330 /* match only on-chip ethernet devices */ 331 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 332 return 1; 333 334 return 0; 335 } 336 337 static void 338 emac_attach(device_t parent, device_t self, void *aux) 339 { 340 struct opb_attach_args *oaa = aux; 341 struct emac_softc *sc = device_private(self); 342 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 343 struct mii_data *mii = &sc->sc_mii; 344 const char * xname = device_xname(self); 345 bus_dma_segment_t seg; 346 int error, i, nseg, opb_freq, opbc, mii_phy = MII_PHY_ANY; 347 const uint8_t *enaddr; 348 prop_dictionary_t dict = device_properties(self); 349 prop_data_t ea; 350 351 bus_space_map(oaa->opb_bt, oaa->opb_addr, EMAC_NREG, 0, &sc->sc_sh); 352 353 sc->sc_dev = self; 354 sc->sc_instance = oaa->opb_instance; 355 sc->sc_st = oaa->opb_bt; 356 sc->sc_dmat = oaa->opb_dmat; 357 358 callout_init(&sc->sc_callout, 0); 359 360 aprint_naive("\n"); 361 aprint_normal(": Ethernet Media Access Controller\n"); 362 363 /* Fetch the Ethernet address. */ 364 ea = prop_dictionary_get(dict, "mac-address"); 365 if (ea == NULL) { 366 aprint_error_dev(self, "unable to get mac-address property\n"); 367 return; 368 } 369 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 370 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 371 enaddr = prop_data_data_nocopy(ea); 372 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 373 374 #if defined(EMAC_ZMII_PHY) || defined(EMAC_RGMII_PHY) 375 /* Fetch the MII offset. */ 376 prop_dictionary_get_uint32(dict, "mii-phy", &mii_phy); 377 378 #ifdef EMAC_ZMII_PHY 379 if (oaa->opb_flags & OPB_FLAGS_EMAC_RMII_ZMII) 380 zmii_attach(parent, sc->sc_instance, &sc->sc_rmii_enable, 381 &sc->sc_rmii_disable, &sc->sc_rmii_speed); 382 #endif 383 #ifdef EMAC_RGMII_PHY 384 if (oaa->opb_flags & OPB_FLAGS_EMAC_RMII_RGMII) 385 rgmii_attach(parent, sc->sc_instance, &sc->sc_rmii_enable, 386 &sc->sc_rmii_disable, &sc->sc_rmii_speed); 387 #endif 388 #endif 389 390 /* 391 * Allocate the control data structures, and create and load the 392 * DMA map for it. 393 */ 394 if ((error = bus_dmamem_alloc(sc->sc_dmat, 395 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 396 aprint_error_dev(self, 397 "unable to allocate control data, error = %d\n", error); 398 goto fail_0; 399 } 400 401 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 402 sizeof(struct emac_control_data), (void **)&sc->sc_control_data, 403 BUS_DMA_COHERENT)) != 0) { 404 aprint_error_dev(self, 405 "unable to map control data, error = %d\n", error); 406 goto fail_1; 407 } 408 409 if ((error = bus_dmamap_create(sc->sc_dmat, 410 sizeof(struct emac_control_data), 1, 411 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 412 aprint_error_dev(self, 413 "unable to create control data DMA map, error = %d\n", 414 error); 415 goto fail_2; 416 } 417 418 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 419 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 420 0)) != 0) { 421 aprint_error_dev(self, 422 "unable to load control data DMA map, error = %d\n", error); 423 goto fail_3; 424 } 425 426 /* 427 * Create the transmit buffer DMA maps. 428 */ 429 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 430 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 431 EMAC_NTXSEGS, MCLBYTES, 0, 0, 432 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 433 aprint_error_dev(self, 434 "unable to create tx DMA map %d, error = %d\n", 435 i, error); 436 goto fail_4; 437 } 438 } 439 440 /* 441 * Create the receive buffer DMA maps. 442 */ 443 for (i = 0; i < EMAC_NRXDESC; i++) { 444 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 445 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 446 aprint_error_dev(self, 447 "unable to create rx DMA map %d, error = %d\n", 448 i, error); 449 goto fail_5; 450 } 451 sc->sc_rxsoft[i].rxs_mbuf = NULL; 452 } 453 454 /* Soft Reset the EMAC. The chip to a known state. */ 455 emac_soft_reset(sc); 456 457 opb_freq = opb_get_frequency(); 458 switch (opb_freq) { 459 case 50000000: opbc = STACR_OPBC_50MHZ; break; 460 case 66666666: opbc = STACR_OPBC_66MHZ; break; 461 case 83333333: opbc = STACR_OPBC_83MHZ; break; 462 case 100000000: opbc = STACR_OPBC_100MHZ; break; 463 464 default: 465 if (opb_freq > 100000000) { 466 opbc = STACR_OPBC_A100MHZ; 467 break; 468 } 469 aprint_error_dev(self, "unsupport OPB frequency %dMHz\n", 470 opb_freq / 1000 / 1000); 471 goto fail_5; 472 } 473 if (oaa->opb_flags & OPB_FLAGS_EMAC_GBE) { 474 sc->sc_mr1 = 475 MR1_RFS_GBE(MR1__FS_16KB) | 476 MR1_TFS_GBE(MR1__FS_16KB) | 477 MR1_TR0_MULTIPLE | 478 MR1_OBCI(opbc); 479 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 480 481 if (oaa->opb_flags & OPB_FLAGS_EMAC_STACV2) { 482 sc->sc_stacr_read = STACR_STAOPC_READ; 483 sc->sc_stacr_write = STACR_STAOPC_WRITE; 484 sc->sc_stacr_bits = STACR_OC; 485 sc->sc_stacr_completed = false; 486 } else { 487 sc->sc_stacr_read = STACR_READ; 488 sc->sc_stacr_write = STACR_WRITE; 489 sc->sc_stacr_completed = true; 490 } 491 } else { 492 /* 493 * Set up Mode Register 1 - set receive and transmit FIFOs to 494 * maximum size, allow transmit of multiple packets (only 495 * channel 0 is used). 496 * 497 * XXX: Allow pause packets?? 498 */ 499 sc->sc_mr1 = 500 MR1_RFS(MR1__FS_4KB) | 501 MR1_TFS(MR1__FS_2KB) | 502 MR1_TR0_MULTIPLE; 503 504 sc->sc_stacr_read = STACR_READ; 505 sc->sc_stacr_write = STACR_WRITE; 506 sc->sc_stacr_bits = STACR_OPBC(opbc); 507 sc->sc_stacr_completed = true; 508 } 509 510 intr_establish_xname(oaa->opb_irq, IST_LEVEL, IPL_NET, emac_intr, sc, 511 device_xname(self)); 512 mal_intr_establish(sc->sc_instance, sc); 513 514 if (oaa->opb_flags & OPB_FLAGS_EMAC_HT256) 515 sc->sc_htsize = 256; 516 else 517 sc->sc_htsize = 64; 518 519 /* Clear all interrupts */ 520 EMAC_WRITE(sc, EMAC_ISR, ISR_ALL); 521 522 /* 523 * Initialise the media structures. 524 */ 525 mii->mii_ifp = ifp; 526 mii->mii_readreg = emac_mii_readreg; 527 mii->mii_writereg = emac_mii_writereg; 528 mii->mii_statchg = emac_mii_statchg; 529 530 sc->sc_ethercom.ec_mii = mii; 531 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 532 mii_attach(self, mii, 0xffffffff, mii_phy, MII_OFFSET_ANY, 533 MIIF_DOPAUSE); 534 if (LIST_FIRST(&mii->mii_phys) == NULL) { 535 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 536 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 537 } else 538 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 539 540 ifp = &sc->sc_ethercom.ec_if; 541 strcpy(ifp->if_xname, xname); 542 ifp->if_softc = sc; 543 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 544 ifp->if_start = emac_start; 545 ifp->if_ioctl = emac_ioctl; 546 ifp->if_init = emac_init; 547 ifp->if_stop = emac_stop; 548 ifp->if_watchdog = emac_watchdog; 549 IFQ_SET_READY(&ifp->if_snd); 550 551 /* 552 * We can support 802.1Q VLAN-sized frames. 553 */ 554 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 555 556 /* 557 * Attach the interface. 558 */ 559 if_attach(ifp); 560 if_deferred_start_init(ifp, NULL); 561 ether_ifattach(ifp, enaddr); 562 563 rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, 564 RND_FLAG_DEFAULT); 565 566 #ifdef EMAC_EVENT_COUNTERS 567 /* 568 * Attach the event counters. 569 */ 570 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 571 NULL, xname, "txintr"); 572 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 573 NULL, xname, "rxintr"); 574 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 575 NULL, xname, "txde"); 576 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 577 NULL, xname, "rxde"); 578 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 579 NULL, xname, "intr"); 580 581 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 582 NULL, xname, "txreap"); 583 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 584 NULL, xname, "txsstall"); 585 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 586 NULL, xname, "txdstall"); 587 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 588 NULL, xname, "txdrop"); 589 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 590 NULL, xname, "tu"); 591 #endif /* EMAC_EVENT_COUNTERS */ 592 593 /* 594 * Make sure the interface is shutdown during reboot. 595 */ 596 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 597 if (sc->sc_sdhook == NULL) 598 aprint_error_dev(self, 599 "WARNING: unable to establish shutdown hook\n"); 600 601 return; 602 603 /* 604 * Free any resources we've allocated during the failed attach 605 * attempt. Do this in reverse order and fall through. 606 */ 607 fail_5: 608 for (i = 0; i < EMAC_NRXDESC; i++) { 609 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 610 bus_dmamap_destroy(sc->sc_dmat, 611 sc->sc_rxsoft[i].rxs_dmamap); 612 } 613 fail_4: 614 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 615 if (sc->sc_txsoft[i].txs_dmamap != NULL) 616 bus_dmamap_destroy(sc->sc_dmat, 617 sc->sc_txsoft[i].txs_dmamap); 618 } 619 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 620 fail_3: 621 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 622 fail_2: 623 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 624 sizeof(struct emac_control_data)); 625 fail_1: 626 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 627 fail_0: 628 return; 629 } 630 631 /* 632 * EMAC General interrupt handler 633 */ 634 static int 635 emac_intr(void *arg) 636 { 637 struct emac_softc *sc = arg; 638 uint32_t status; 639 640 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 641 status = EMAC_READ(sc, EMAC_ISR); 642 643 /* Clear the interrupt status bits. */ 644 EMAC_WRITE(sc, EMAC_ISR, status); 645 646 return 1; 647 } 648 649 static void 650 emac_shutdown(void *arg) 651 { 652 struct emac_softc *sc = arg; 653 654 emac_stop(&sc->sc_ethercom.ec_if, 0); 655 } 656 657 658 /* 659 * ifnet interface functions 660 */ 661 662 static void 663 emac_start(struct ifnet *ifp) 664 { 665 struct emac_softc *sc = ifp->if_softc; 666 struct mbuf *m0; 667 struct emac_txsoft *txs; 668 bus_dmamap_t dmamap; 669 int error, firsttx, nexttx, lasttx, ofree, seg; 670 671 lasttx = 0; /* XXX gcc */ 672 673 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 674 return; 675 676 /* 677 * Remember the previous number of free descriptors. 678 */ 679 ofree = sc->sc_txfree; 680 681 /* 682 * Loop through the send queue, setting up transmit descriptors 683 * until we drain the queue, or use up all available transmit 684 * descriptors. 685 */ 686 for (;;) { 687 /* Grab a packet off the queue. */ 688 IFQ_POLL(&ifp->if_snd, m0); 689 if (m0 == NULL) 690 break; 691 692 /* 693 * Get a work queue entry. Reclaim used Tx descriptors if 694 * we are running low. 695 */ 696 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 697 emac_txreap(sc); 698 if (sc->sc_txsfree == 0) { 699 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 700 break; 701 } 702 } 703 704 txs = &sc->sc_txsoft[sc->sc_txsnext]; 705 dmamap = txs->txs_dmamap; 706 707 /* 708 * Load the DMA map. If this fails, the packet either 709 * didn't fit in the alloted number of segments, or we 710 * were short on resources. In this case, we'll copy 711 * and try again. 712 */ 713 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 714 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 715 if (error) { 716 if (error == EFBIG) { 717 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 718 aprint_error_ifnet(ifp, 719 "Tx packet consumes too many " 720 "DMA segments, dropping...\n"); 721 IFQ_DEQUEUE(&ifp->if_snd, m0); 722 m_freem(m0); 723 continue; 724 } 725 /* Short on resources, just stop for now. */ 726 break; 727 } 728 729 /* 730 * Ensure we have enough descriptors free to describe 731 * the packet. 732 */ 733 if (dmamap->dm_nsegs > sc->sc_txfree) { 734 /* 735 * Not enough free descriptors to transmit this 736 * packet. We haven't committed anything yet, 737 * so just unload the DMA map, put the packet 738 * back on the queue, and punt. Notify the upper 739 * layer that there are not more slots left. 740 * 741 */ 742 ifp->if_flags |= IFF_OACTIVE; 743 bus_dmamap_unload(sc->sc_dmat, dmamap); 744 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 745 break; 746 } 747 748 IFQ_DEQUEUE(&ifp->if_snd, m0); 749 750 /* 751 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 752 */ 753 754 /* Sync the DMA map. */ 755 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 756 BUS_DMASYNC_PREWRITE); 757 758 /* 759 * Store a pointer to the packet so that we can free it 760 * later. 761 */ 762 txs->txs_mbuf = m0; 763 txs->txs_firstdesc = sc->sc_txnext; 764 txs->txs_ndesc = dmamap->dm_nsegs; 765 766 /* 767 * Initialize the transmit descriptor. 768 */ 769 firsttx = sc->sc_txnext; 770 for (nexttx = sc->sc_txnext, seg = 0; 771 seg < dmamap->dm_nsegs; 772 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 773 struct mal_descriptor *txdesc = 774 &sc->sc_txdescs[nexttx]; 775 776 /* 777 * If this is the first descriptor we're 778 * enqueueing, don't set the TX_READY bit just 779 * yet. That could cause a race condition. 780 * We'll do it below. 781 */ 782 txdesc->md_data = dmamap->dm_segs[seg].ds_addr; 783 txdesc->md_data_len = dmamap->dm_segs[seg].ds_len; 784 txdesc->md_stat_ctrl = 785 (txdesc->md_stat_ctrl & MAL_TX_WRAP) | 786 (nexttx == firsttx ? 0 : MAL_TX_READY) | 787 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 788 lasttx = nexttx; 789 } 790 791 /* Set the LAST bit on the last segment. */ 792 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 793 794 /* 795 * Set up last segment descriptor to send an interrupt after 796 * that descriptor is transmitted, and bypass existing Tx 797 * descriptor reaping method (for now...). 798 */ 799 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_INTERRUPT; 800 801 802 txs->txs_lastdesc = lasttx; 803 804 /* Sync the descriptors we're using. */ 805 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 806 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 807 808 /* 809 * The entire packet chain is set up. Give the 810 * first descriptor to the chip now. 811 */ 812 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 813 EMAC_CDTXSYNC(sc, firsttx, 1, 814 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 815 /* 816 * Tell the EMAC that a new packet is available. 817 */ 818 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0 | TMR0_TFAE_2); 819 820 /* Advance the tx pointer. */ 821 sc->sc_txfree -= txs->txs_ndesc; 822 sc->sc_txnext = nexttx; 823 824 sc->sc_txsfree--; 825 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 826 827 /* 828 * Pass the packet to any BPF listeners. 829 */ 830 bpf_mtap(ifp, m0, BPF_D_OUT); 831 } 832 833 if (sc->sc_txfree == 0) 834 /* No more slots left; notify upper layer. */ 835 ifp->if_flags |= IFF_OACTIVE; 836 837 if (sc->sc_txfree != ofree) 838 /* Set a watchdog timer in case the chip flakes out. */ 839 ifp->if_timer = 5; 840 } 841 842 static int 843 emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 844 { 845 struct emac_softc *sc = ifp->if_softc; 846 int s, error; 847 848 s = splnet(); 849 850 switch (cmd) { 851 case SIOCSIFMTU: 852 { 853 struct ifreq *ifr = (struct ifreq *)data; 854 int maxmtu; 855 856 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) 857 maxmtu = EMAC_MAX_MTU; 858 else 859 maxmtu = ETHERMTU; 860 861 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > maxmtu) 862 error = EINVAL; 863 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 864 break; 865 else if (ifp->if_flags & IFF_UP) 866 error = emac_init(ifp); 867 else 868 error = 0; 869 break; 870 } 871 872 default: 873 error = ether_ioctl(ifp, cmd, data); 874 if (error == ENETRESET) { 875 /* 876 * Multicast list has changed; set the hardware filter 877 * accordingly. 878 */ 879 if (ifp->if_flags & IFF_RUNNING) 880 error = emac_set_filter(sc); 881 else 882 error = 0; 883 } 884 } 885 886 /* try to get more packets going */ 887 emac_start(ifp); 888 889 splx(s); 890 return error; 891 } 892 893 static int 894 emac_init(struct ifnet *ifp) 895 { 896 struct emac_softc *sc = ifp->if_softc; 897 struct emac_rxsoft *rxs; 898 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 899 int error, i; 900 901 error = 0; 902 903 /* Cancel any pending I/O. */ 904 emac_stop(ifp, 0); 905 906 /* Reset the chip to a known state. */ 907 emac_soft_reset(sc); 908 909 /* 910 * Initialise the transmit descriptor ring. 911 */ 912 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 913 /* set wrap on last descriptor */ 914 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 915 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 916 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 917 sc->sc_txfree = EMAC_NTXDESC; 918 sc->sc_txnext = 0; 919 920 /* 921 * Initialise the transmit job descriptors. 922 */ 923 for (i = 0; i < EMAC_TXQUEUELEN; i++) 924 sc->sc_txsoft[i].txs_mbuf = NULL; 925 sc->sc_txsfree = EMAC_TXQUEUELEN; 926 sc->sc_txsnext = 0; 927 sc->sc_txsdirty = 0; 928 929 /* 930 * Initialise the receiver descriptor and receive job 931 * descriptor rings. 932 */ 933 for (i = 0; i < EMAC_NRXDESC; i++) { 934 rxs = &sc->sc_rxsoft[i]; 935 if (rxs->rxs_mbuf == NULL) { 936 if ((error = emac_add_rxbuf(sc, i)) != 0) { 937 aprint_error_ifnet(ifp, 938 "unable to allocate or map rx buffer %d," 939 " error = %d\n", 940 i, error); 941 /* 942 * XXX Should attempt to run with fewer receive 943 * XXX buffers instead of just failing. 944 */ 945 emac_rxdrain(sc); 946 goto out; 947 } 948 } else 949 EMAC_INIT_RXDESC(sc, i); 950 } 951 sc->sc_rxptr = 0; 952 953 /* 954 * Set the current media. 955 */ 956 if ((error = ether_mediachange(ifp)) != 0) 957 goto out; 958 959 /* 960 * Load the MAC address. 961 */ 962 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 963 EMAC_WRITE(sc, EMAC_IALR, 964 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 965 966 /* Enable the transmit and receive channel on the MAL. */ 967 error = mal_start(sc->sc_instance, 968 EMAC_CDTXADDR(sc, 0), EMAC_CDRXADDR(sc, 0)); 969 if (error) 970 goto out; 971 972 sc->sc_mr1 &= ~MR1_JPSM; 973 if (ifp->if_mtu > ETHERMTU) 974 /* Enable Jumbo Packet Support Mode */ 975 sc->sc_mr1 |= MR1_JPSM; 976 977 /* Set fifos, media modes. */ 978 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 979 980 /* 981 * Enable Individual and (possibly) Broadcast Address modes, 982 * runt packets, and strip padding. 983 */ 984 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | RMR_TFAE_2 | 985 (ifp->if_flags & IFF_PROMISC ? RMR_PME : 0) | 986 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 987 988 /* 989 * Set multicast filter. 990 */ 991 emac_set_filter(sc); 992 993 /* 994 * Set low- and urgent-priority request thresholds. 995 */ 996 EMAC_WRITE(sc, EMAC_TMR1, 997 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 998 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 999 /* 1000 * Set Transmit Request Threshold Register. 1001 */ 1002 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 1003 1004 /* 1005 * Set high and low receive watermarks. 1006 */ 1007 EMAC_WRITE(sc, EMAC_RWMR, 1008 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 1009 1010 /* 1011 * Set frame gap. 1012 */ 1013 EMAC_WRITE(sc, EMAC_IPGVR, 8); 1014 1015 /* 1016 * Set interrupt status enable bits for EMAC. 1017 */ 1018 EMAC_WRITE(sc, EMAC_ISER, 1019 ISR_TXPE | /* TX Parity Error */ 1020 ISR_RXPE | /* RX Parity Error */ 1021 ISR_TXUE | /* TX Underrun Event */ 1022 ISR_RXOE | /* RX Overrun Event */ 1023 ISR_OVR | /* Overrun Error */ 1024 ISR_PP | /* Pause Packet */ 1025 ISR_BP | /* Bad Packet */ 1026 ISR_RP | /* Runt Packet */ 1027 ISR_SE | /* Short Event */ 1028 ISR_ALE | /* Alignment Error */ 1029 ISR_BFCS | /* Bad FCS */ 1030 ISR_PTLE | /* Packet Too Long Error */ 1031 ISR_ORE | /* Out of Range Error */ 1032 ISR_IRE | /* In Range Error */ 1033 ISR_SE0 | /* Signal Quality Error 0 (SQE) */ 1034 ISR_TE0 | /* Transmit Error 0 */ 1035 ISR_MOS | /* MMA Operation Succeeded */ 1036 ISR_MOF); /* MMA Operation Failed */ 1037 1038 /* 1039 * Enable the transmit and receive channel on the EMAC. 1040 */ 1041 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 1042 1043 /* 1044 * Start the one second MII clock. 1045 */ 1046 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1047 1048 /* 1049 * ... all done! 1050 */ 1051 ifp->if_flags |= IFF_RUNNING; 1052 ifp->if_flags &= ~IFF_OACTIVE; 1053 1054 out: 1055 if (error) { 1056 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1057 ifp->if_timer = 0; 1058 aprint_error_ifnet(ifp, "interface not running\n"); 1059 } 1060 return error; 1061 } 1062 1063 static void 1064 emac_stop(struct ifnet *ifp, int disable) 1065 { 1066 struct emac_softc *sc = ifp->if_softc; 1067 struct emac_txsoft *txs; 1068 int i; 1069 1070 /* Stop the one second clock. */ 1071 callout_stop(&sc->sc_callout); 1072 1073 /* Down the MII */ 1074 mii_down(&sc->sc_mii); 1075 1076 /* Disable interrupts. */ 1077 EMAC_WRITE(sc, EMAC_ISER, 0); 1078 1079 /* Disable the receive and transmit channels. */ 1080 mal_stop(sc->sc_instance); 1081 1082 /* Disable the transmit enable and receive MACs. */ 1083 EMAC_WRITE(sc, EMAC_MR0, 1084 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 1085 1086 /* Release any queued transmit buffers. */ 1087 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 1088 txs = &sc->sc_txsoft[i]; 1089 if (txs->txs_mbuf != NULL) { 1090 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1091 m_freem(txs->txs_mbuf); 1092 txs->txs_mbuf = NULL; 1093 } 1094 } 1095 1096 if (disable) 1097 emac_rxdrain(sc); 1098 1099 /* 1100 * Mark the interface down and cancel the watchdog timer. 1101 */ 1102 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1103 ifp->if_timer = 0; 1104 } 1105 1106 static void 1107 emac_watchdog(struct ifnet *ifp) 1108 { 1109 struct emac_softc *sc = ifp->if_softc; 1110 1111 /* 1112 * Since we're not interrupting every packet, sweep 1113 * up before we report an error. 1114 */ 1115 emac_txreap(sc); 1116 1117 if (sc->sc_txfree != EMAC_NTXDESC) { 1118 aprint_error_ifnet(ifp, 1119 "device timeout (txfree %d txsfree %d txnext %d)\n", 1120 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1121 if_statinc(ifp, if_oerrors); 1122 1123 /* Reset the interface. */ 1124 (void)emac_init(ifp); 1125 } else if (ifp->if_flags & IFF_DEBUG) 1126 aprint_error_ifnet(ifp, "recovered from device timeout\n"); 1127 1128 /* try to get more packets going */ 1129 emac_start(ifp); 1130 } 1131 1132 static int 1133 emac_add_rxbuf(struct emac_softc *sc, int idx) 1134 { 1135 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1136 struct mbuf *m; 1137 int error; 1138 1139 MGETHDR(m, M_DONTWAIT, MT_DATA); 1140 if (m == NULL) 1141 return ENOBUFS; 1142 1143 MCLGET(m, M_DONTWAIT); 1144 if ((m->m_flags & M_EXT) == 0) { 1145 m_freem(m); 1146 return ENOBUFS; 1147 } 1148 1149 if (rxs->rxs_mbuf != NULL) 1150 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1151 1152 rxs->rxs_mbuf = m; 1153 1154 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1155 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1156 if (error) { 1157 aprint_error_dev(sc->sc_dev, 1158 "can't load rx DMA map %d, error = %d\n", idx, error); 1159 panic("emac_add_rxbuf"); /* XXX */ 1160 } 1161 1162 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1163 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1164 1165 EMAC_INIT_RXDESC(sc, idx); 1166 1167 return 0; 1168 } 1169 1170 static void 1171 emac_rxdrain(struct emac_softc *sc) 1172 { 1173 struct emac_rxsoft *rxs; 1174 int i; 1175 1176 for (i = 0; i < EMAC_NRXDESC; i++) { 1177 rxs = &sc->sc_rxsoft[i]; 1178 if (rxs->rxs_mbuf != NULL) { 1179 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1180 m_freem(rxs->rxs_mbuf); 1181 rxs->rxs_mbuf = NULL; 1182 } 1183 } 1184 } 1185 1186 static int 1187 emac_set_filter(struct emac_softc *sc) 1188 { 1189 struct ethercom *ec = &sc->sc_ethercom; 1190 struct ether_multistep step; 1191 struct ether_multi *enm; 1192 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1193 uint32_t rmr, crc, mask, tmp, reg, gaht[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1194 int regs, cnt = 0, i; 1195 1196 if (sc->sc_htsize == 256) { 1197 reg = EMAC_GAHT256(0); 1198 regs = 8; 1199 } else { 1200 reg = EMAC_GAHT64(0); 1201 regs = 4; 1202 } 1203 mask = (1ULL << (sc->sc_htsize / regs)) - 1; 1204 1205 rmr = EMAC_READ(sc, EMAC_RMR); 1206 rmr &= ~(RMR_PMME | RMR_MAE); 1207 ifp->if_flags &= ~IFF_ALLMULTI; 1208 1209 ETHER_LOCK(ec); 1210 ETHER_FIRST_MULTI(step, ec, enm); 1211 while (enm != NULL) { 1212 if (memcmp(enm->enm_addrlo, 1213 enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1214 /* 1215 * We must listen to a range of multicast addresses. 1216 * For now, just accept all multicasts, rather than 1217 * trying to set only those filter bits needed to match 1218 * the range. (At this time, the only use of address 1219 * ranges is for IP multicast routing, for which the 1220 * range is big enough to require all bits set.) 1221 */ 1222 gaht[0] = gaht[1] = gaht[2] = gaht[3] = 1223 gaht[4] = gaht[5] = gaht[6] = gaht[7] = mask; 1224 break; 1225 } 1226 1227 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1228 1229 if (sc->sc_htsize == 256) 1230 EMAC_SET_FILTER256(gaht, crc); 1231 else 1232 EMAC_SET_FILTER(gaht, crc); 1233 1234 ETHER_NEXT_MULTI(step, enm); 1235 cnt++; 1236 } 1237 ETHER_UNLOCK(ec); 1238 1239 for (i = 1, tmp = gaht[0]; i < regs; i++) 1240 tmp &= gaht[i]; 1241 if (tmp == mask) { 1242 /* All categories are true. */ 1243 ifp->if_flags |= IFF_ALLMULTI; 1244 rmr |= RMR_PMME; 1245 } else if (cnt != 0) { 1246 /* Some categories are true. */ 1247 for (i = 0; i < regs; i++) 1248 EMAC_WRITE(sc, reg + (i << 2), gaht[i]); 1249 rmr |= RMR_MAE; 1250 } 1251 EMAC_WRITE(sc, EMAC_RMR, rmr); 1252 1253 return 0; 1254 } 1255 1256 /* 1257 * Reap completed Tx descriptors. 1258 */ 1259 static int 1260 emac_txreap(struct emac_softc *sc) 1261 { 1262 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1263 struct emac_txsoft *txs; 1264 int handled, i; 1265 uint32_t txstat, count; 1266 1267 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1268 handled = 0; 1269 1270 ifp->if_flags &= ~IFF_OACTIVE; 1271 1272 count = 0; 1273 /* 1274 * Go through our Tx list and free mbufs for those 1275 * frames that have been transmitted. 1276 */ 1277 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1278 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1279 txs = &sc->sc_txsoft[i]; 1280 1281 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1282 txs->txs_dmamap->dm_nsegs, 1283 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1284 1285 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1286 if (txstat & MAL_TX_READY) 1287 break; 1288 1289 handled = 1; 1290 1291 /* 1292 * Check for errors and collisions. 1293 */ 1294 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1295 if_statinc(ifp, if_oerrors); 1296 1297 #ifdef EMAC_EVENT_COUNTERS 1298 if (txstat & EMAC_TXS_UR) 1299 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1300 #endif /* EMAC_EVENT_COUNTERS */ 1301 1302 if (txstat & 1303 (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1304 if (txstat & EMAC_TXS_EC) 1305 if_statadd(ifp, if_collisions, 16); 1306 else if (txstat & EMAC_TXS_MC) 1307 if_statadd(ifp, if_collisions, 2); /* XXX? */ 1308 else if (txstat & EMAC_TXS_SC) 1309 if_statinc(ifp, if_collisions); 1310 if (txstat & EMAC_TXS_LC) 1311 if_statinc(ifp, if_collisions); 1312 } else 1313 if_statinc(ifp, if_opackets); 1314 1315 if (ifp->if_flags & IFF_DEBUG) { 1316 if (txstat & EMAC_TXS_ED) 1317 aprint_error_ifnet(ifp, "excessive deferral\n"); 1318 if (txstat & EMAC_TXS_EC) 1319 aprint_error_ifnet(ifp, 1320 "excessive collisions\n"); 1321 } 1322 1323 sc->sc_txfree += txs->txs_ndesc; 1324 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1325 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1326 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1327 m_freem(txs->txs_mbuf); 1328 txs->txs_mbuf = NULL; 1329 1330 count++; 1331 } 1332 1333 /* Update the dirty transmit buffer pointer. */ 1334 sc->sc_txsdirty = i; 1335 1336 /* 1337 * If there are no more pending transmissions, cancel the watchdog 1338 * timer. 1339 */ 1340 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1341 ifp->if_timer = 0; 1342 1343 if (count != 0) 1344 rnd_add_uint32(&sc->rnd_source, count); 1345 1346 return handled; 1347 } 1348 1349 1350 /* 1351 * Reset functions 1352 */ 1353 1354 static void 1355 emac_soft_reset(struct emac_softc *sc) 1356 { 1357 uint32_t sdr; 1358 int t = 0; 1359 1360 /* 1361 * The PHY must provide a TX Clk in order perform a soft reset the 1362 * EMAC. If none is present, select the internal clock, 1363 * SDR0_MFR[E0CS, E1CS]. After the soft reset, select the external 1364 * clock. 1365 */ 1366 1367 sdr = mfsdr(DCR_SDR0_MFR); 1368 sdr |= SDR0_MFR_ECS(sc->sc_instance); 1369 mtsdr(DCR_SDR0_MFR, sdr); 1370 1371 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1372 1373 sdr = mfsdr(DCR_SDR0_MFR); 1374 sdr &= ~SDR0_MFR_ECS(sc->sc_instance); 1375 mtsdr(DCR_SDR0_MFR, sdr); 1376 1377 delay(5); 1378 1379 /* wait finish */ 1380 while (EMAC_READ(sc, EMAC_MR0) & MR0_SRST) { 1381 if (++t == 1000000 /* 1sec XXXXX */) { 1382 aprint_error_dev(sc->sc_dev, "Soft Reset failed\n"); 1383 return; 1384 } 1385 delay(1); 1386 } 1387 } 1388 1389 static void 1390 emac_smart_reset(struct emac_softc *sc) 1391 { 1392 uint32_t mr0; 1393 int t = 0; 1394 1395 mr0 = EMAC_READ(sc, EMAC_MR0); 1396 if (mr0 & (MR0_TXE | MR0_RXE)) { 1397 mr0 &= ~(MR0_TXE | MR0_RXE); 1398 EMAC_WRITE(sc, EMAC_MR0, mr0); 1399 1400 /* wait idel state */ 1401 while ((EMAC_READ(sc, EMAC_MR0) & (MR0_TXI | MR0_RXI)) != 1402 (MR0_TXI | MR0_RXI)) { 1403 if (++t == 1000000 /* 1sec XXXXX */) { 1404 aprint_error_dev(sc->sc_dev, 1405 "Smart Reset failed\n"); 1406 return; 1407 } 1408 delay(1); 1409 } 1410 } 1411 } 1412 1413 1414 /* 1415 * MII related functions 1416 */ 1417 1418 static int 1419 emac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1420 { 1421 struct emac_softc *sc = device_private(self); 1422 uint32_t sta_reg; 1423 int rv; 1424 1425 if (sc->sc_rmii_enable) 1426 sc->sc_rmii_enable(device_parent(self), sc->sc_instance); 1427 1428 /* wait for PHY data transfer to complete */ 1429 if ((rv = emac_mii_wait(sc)) != 0) 1430 goto fail; 1431 1432 sta_reg = 1433 sc->sc_stacr_read | 1434 (reg << STACR_PRA_SHIFT) | 1435 (phy << STACR_PCDA_SHIFT) | 1436 sc->sc_stacr_bits; 1437 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1438 1439 if ((rv = emac_mii_wait(sc)) != 0) 1440 goto fail; 1441 sta_reg = EMAC_READ(sc, EMAC_STACR); 1442 1443 if (sta_reg & STACR_PHYE) { 1444 rv = -1; 1445 goto fail; 1446 } 1447 *val = sta_reg >> STACR_PHYD_SHIFT; 1448 1449 fail: 1450 if (sc->sc_rmii_disable) 1451 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 1452 return rv; 1453 } 1454 1455 static int 1456 emac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1457 { 1458 struct emac_softc *sc = device_private(self); 1459 uint32_t sta_reg; 1460 int rv; 1461 1462 if (sc->sc_rmii_enable) 1463 sc->sc_rmii_enable(device_parent(self), sc->sc_instance); 1464 1465 /* wait for PHY data transfer to complete */ 1466 if ((rv = emac_mii_wait(sc)) != 0) 1467 goto out; 1468 1469 sta_reg = 1470 (val << STACR_PHYD_SHIFT) | 1471 sc->sc_stacr_write | 1472 (reg << STACR_PRA_SHIFT) | 1473 (phy << STACR_PCDA_SHIFT) | 1474 sc->sc_stacr_bits; 1475 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1476 1477 if ((rv = emac_mii_wait(sc)) != 0) 1478 goto out; 1479 if (EMAC_READ(sc, EMAC_STACR) & STACR_PHYE) { 1480 aprint_error_dev(sc->sc_dev, "MII PHY Error\n"); 1481 rv = -1; 1482 } 1483 1484 out: 1485 if (sc->sc_rmii_disable) 1486 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 1487 1488 return rv; 1489 } 1490 1491 static void 1492 emac_mii_statchg(struct ifnet *ifp) 1493 { 1494 struct emac_softc *sc = ifp->if_softc; 1495 struct mii_data *mii = &sc->sc_mii; 1496 1497 /* 1498 * MR1 can only be written immediately after a reset... 1499 */ 1500 emac_smart_reset(sc); 1501 1502 sc->sc_mr1 &= ~(MR1_FDE | MR1_ILE | MR1_EIFC | MR1_MF_MASK | MR1_IST); 1503 if (mii->mii_media_active & IFM_FDX) 1504 sc->sc_mr1 |= (MR1_FDE | MR1_EIFC | MR1_IST); 1505 if (mii->mii_media_active & IFM_FLOW) 1506 sc->sc_mr1 |= MR1_EIFC; 1507 if (mii->mii_media_active & IFM_LOOP) 1508 sc->sc_mr1 |= MR1_ILE; 1509 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1510 case IFM_1000_T: 1511 sc->sc_mr1 |= (MR1_MF_1000MBS | MR1_IST); 1512 break; 1513 1514 case IFM_100_TX: 1515 sc->sc_mr1 |= (MR1_MF_100MBS | MR1_IST); 1516 break; 1517 1518 case IFM_10_T: 1519 sc->sc_mr1 |= MR1_MF_10MBS; 1520 break; 1521 1522 case IFM_NONE: 1523 break; 1524 1525 default: 1526 aprint_error_dev(sc->sc_dev, "unknown sub-type %d\n", 1527 IFM_SUBTYPE(mii->mii_media_active)); 1528 break; 1529 } 1530 if (sc->sc_rmii_speed) 1531 sc->sc_rmii_speed(device_parent(sc->sc_dev), sc->sc_instance, 1532 IFM_SUBTYPE(mii->mii_media_active)); 1533 1534 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 1535 1536 /* Enable TX and RX if already RUNNING */ 1537 if (ifp->if_flags & IFF_RUNNING) 1538 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 1539 } 1540 1541 static uint32_t 1542 emac_mii_wait(struct emac_softc *sc) 1543 { 1544 int i; 1545 uint32_t oc; 1546 1547 /* wait for PHY data transfer to complete */ 1548 i = 0; 1549 oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC; 1550 while ((oc == STACR_OC) != sc->sc_stacr_completed) { 1551 delay(7); 1552 if (i++ > 5) { 1553 aprint_error_dev(sc->sc_dev, "MII timed out\n"); 1554 return ETIMEDOUT; 1555 } 1556 oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC; 1557 } 1558 return 0; 1559 } 1560 1561 static void 1562 emac_mii_tick(void *arg) 1563 { 1564 struct emac_softc *sc = arg; 1565 int s; 1566 1567 if (!device_is_active(sc->sc_dev)) 1568 return; 1569 1570 s = splnet(); 1571 mii_tick(&sc->sc_mii); 1572 splx(s); 1573 1574 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1575 } 1576 1577 int 1578 emac_txeob_intr(void *arg) 1579 { 1580 struct emac_softc *sc = arg; 1581 int handled = 0; 1582 1583 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1584 handled |= emac_txreap(sc); 1585 1586 /* try to get more packets going */ 1587 if_schedule_deferred_start(&sc->sc_ethercom.ec_if); 1588 1589 return handled; 1590 } 1591 1592 int 1593 emac_rxeob_intr(void *arg) 1594 { 1595 struct emac_softc *sc = arg; 1596 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1597 struct emac_rxsoft *rxs; 1598 struct mbuf *m; 1599 uint32_t rxstat, count; 1600 int i, len; 1601 1602 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1603 1604 count = 0; 1605 for (i = sc->sc_rxptr; ; i = EMAC_NEXTRX(i)) { 1606 rxs = &sc->sc_rxsoft[i]; 1607 1608 EMAC_CDRXSYNC(sc, i, 1609 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1610 1611 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1612 1613 if (rxstat & MAL_RX_EMPTY) { 1614 /* 1615 * We have processed all of the receive buffers. 1616 */ 1617 /* Flush current empty descriptor */ 1618 EMAC_CDRXSYNC(sc, i, 1619 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1620 break; 1621 } 1622 1623 /* 1624 * If an error occurred, update stats, clear the status 1625 * word, and leave the packet buffer in place. It will 1626 * simply be reused the next time the ring comes around. 1627 */ 1628 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1629 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1630 EMAC_RXS_IRE)) { 1631 #define PRINTERR(bit, str) \ 1632 if (rxstat & (bit)) \ 1633 aprint_error_ifnet(ifp, \ 1634 "receive error: %s\n", str) 1635 if_statinc(ifp, if_ierrors); 1636 PRINTERR(EMAC_RXS_OE, "overrun error"); 1637 PRINTERR(EMAC_RXS_BP, "bad packet"); 1638 PRINTERR(EMAC_RXS_RP, "runt packet"); 1639 PRINTERR(EMAC_RXS_SE, "short event"); 1640 PRINTERR(EMAC_RXS_AE, "alignment error"); 1641 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1642 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1643 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1644 PRINTERR(EMAC_RXS_IRE, "in range error"); 1645 #undef PRINTERR 1646 EMAC_INIT_RXDESC(sc, i); 1647 continue; 1648 } 1649 1650 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1651 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1652 1653 /* 1654 * No errors; receive the packet. Note, the 405GP emac 1655 * includes the CRC with every packet. 1656 */ 1657 len = sc->sc_rxdescs[i].md_data_len - ETHER_CRC_LEN; 1658 1659 /* 1660 * If the packet is small enough to fit in a 1661 * single header mbuf, allocate one and copy 1662 * the data into it. This greatly reduces 1663 * memory consumption when we receive lots 1664 * of small packets. 1665 * 1666 * Otherwise, we add a new buffer to the receive 1667 * chain. If this fails, we drop the packet and 1668 * recycle the old buffer. 1669 */ 1670 if (emac_copy_small != 0 && len <= MHLEN) { 1671 MGETHDR(m, M_DONTWAIT, MT_DATA); 1672 if (m == NULL) 1673 goto dropit; 1674 memcpy(mtod(m, void *), 1675 mtod(rxs->rxs_mbuf, void *), len); 1676 EMAC_INIT_RXDESC(sc, i); 1677 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1678 rxs->rxs_dmamap->dm_mapsize, 1679 BUS_DMASYNC_PREREAD); 1680 } else { 1681 m = rxs->rxs_mbuf; 1682 if (emac_add_rxbuf(sc, i) != 0) { 1683 dropit: 1684 if_statinc(ifp, if_ierrors); 1685 EMAC_INIT_RXDESC(sc, i); 1686 bus_dmamap_sync(sc->sc_dmat, 1687 rxs->rxs_dmamap, 0, 1688 rxs->rxs_dmamap->dm_mapsize, 1689 BUS_DMASYNC_PREREAD); 1690 continue; 1691 } 1692 } 1693 1694 m_set_rcvif(m, ifp); 1695 m->m_pkthdr.len = m->m_len = len; 1696 1697 /* Pass it on. */ 1698 if_percpuq_enqueue(ifp->if_percpuq, m); 1699 1700 count++; 1701 } 1702 1703 /* Update the receive pointer. */ 1704 sc->sc_rxptr = i; 1705 1706 if (count != 0) 1707 rnd_add_uint32(&sc->rnd_source, count); 1708 1709 return 1; 1710 } 1711 1712 int 1713 emac_txde_intr(void *arg) 1714 { 1715 struct emac_softc *sc = arg; 1716 1717 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1718 aprint_error_dev(sc->sc_dev, "emac_txde_intr\n"); 1719 return 1; 1720 } 1721 1722 int 1723 emac_rxde_intr(void *arg) 1724 { 1725 struct emac_softc *sc = arg; 1726 int i; 1727 1728 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1729 aprint_error_dev(sc->sc_dev, "emac_rxde_intr\n"); 1730 /* 1731 * XXX! 1732 * This is a bit drastic; we just drop all descriptors that aren't 1733 * "clean". We should probably send any that are up the stack. 1734 */ 1735 for (i = 0; i < EMAC_NRXDESC; i++) { 1736 EMAC_CDRXSYNC(sc, i, 1737 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1738 1739 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) 1740 EMAC_INIT_RXDESC(sc, i); 1741 } 1742 1743 return 1; 1744 } 1745