1 /* $NetBSD: if_emac.c,v 1.35 2010/01/22 08:56:05 martin Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.35 2010/01/22 08:56:05 martin Exp $"); 40 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 49 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_ether.h> 55 56 #include <net/bpf.h> 57 58 #include <powerpc/ibm4xx/dev/opbvar.h> 59 60 #include <powerpc/ibm4xx/ibm405gp.h> 61 #include <powerpc/ibm4xx/mal405gp.h> 62 #include <powerpc/ibm4xx/dcr405gp.h> 63 #include <powerpc/ibm4xx/dev/emacreg.h> 64 #include <powerpc/ibm4xx/dev/if_emacreg.h> 65 66 #include <dev/mii/miivar.h> 67 68 /* 69 * Transmit descriptor list size. There are two Tx channels, each with 70 * up to 256 hardware descriptors available. We currently use one Tx 71 * channel. We tell the upper layers that they can queue a lot of 72 * packets, and we go ahead and manage up to 64 of them at a time. We 73 * allow up to 16 DMA segments per packet. 74 */ 75 #define EMAC_NTXSEGS 16 76 #define EMAC_TXQUEUELEN 64 77 #define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 78 #define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 79 #define EMAC_NTXDESC 256 80 #define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 81 #define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 82 #define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 83 84 /* 85 * Receive descriptor list size. There is one Rx channel with up to 256 86 * hardware descriptors available. We allocate 64 receive descriptors, 87 * each with a 2k buffer (MCLBYTES). 88 */ 89 #define EMAC_NRXDESC 64 90 #define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 91 #define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 92 #define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 93 94 /* 95 * Transmit/receive descriptors that are DMA'd to the EMAC. 96 */ 97 struct emac_control_data { 98 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 99 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 100 }; 101 102 #define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 103 #define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 104 #define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 105 106 /* 107 * Software state for transmit jobs. 108 */ 109 struct emac_txsoft { 110 struct mbuf *txs_mbuf; /* head of mbuf chain */ 111 bus_dmamap_t txs_dmamap; /* our DMA map */ 112 int txs_firstdesc; /* first descriptor in packet */ 113 int txs_lastdesc; /* last descriptor in packet */ 114 int txs_ndesc; /* # of descriptors used */ 115 }; 116 117 /* 118 * Software state for receive descriptors. 119 */ 120 struct emac_rxsoft { 121 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 122 bus_dmamap_t rxs_dmamap; /* our DMA map */ 123 }; 124 125 /* 126 * Software state per device. 127 */ 128 struct emac_softc { 129 struct device sc_dev; /* generic device information */ 130 bus_space_tag_t sc_st; /* bus space tag */ 131 bus_space_handle_t sc_sh; /* bus space handle */ 132 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 133 struct ethercom sc_ethercom; /* ethernet common data */ 134 void *sc_sdhook; /* shutdown hook */ 135 void *sc_powerhook; /* power management hook */ 136 137 struct mii_data sc_mii; /* MII/media information */ 138 struct callout sc_callout; /* tick callout */ 139 140 u_int32_t sc_mr1; /* copy of Mode Register 1 */ 141 142 bus_dmamap_t sc_cddmamap; /* control data dma map */ 143 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 144 145 /* Software state for transmit/receive descriptors. */ 146 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 147 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 148 149 /* Control data structures. */ 150 struct emac_control_data *sc_control_data; 151 #define sc_txdescs sc_control_data->ecd_txdesc 152 #define sc_rxdescs sc_control_data->ecd_rxdesc 153 154 #ifdef EMAC_EVENT_COUNTERS 155 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 156 struct evcnt sc_ev_txintr; /* Tx interrupts */ 157 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 158 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 159 struct evcnt sc_ev_wol; /* Wake-On-Lan interrupts */ 160 struct evcnt sc_ev_serr; /* MAL system error interrupts */ 161 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 162 163 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 164 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 165 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 166 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 167 struct evcnt sc_ev_tu; /* Tx underrun */ 168 #endif /* EMAC_EVENT_COUNTERS */ 169 170 int sc_txfree; /* number of free Tx descriptors */ 171 int sc_txnext; /* next ready Tx descriptor */ 172 173 int sc_txsfree; /* number of free Tx jobs */ 174 int sc_txsnext; /* next ready Tx job */ 175 int sc_txsdirty; /* dirty Tx jobs */ 176 177 int sc_rxptr; /* next ready RX descriptor/descsoft */ 178 }; 179 180 #ifdef EMAC_EVENT_COUNTERS 181 #define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 182 #else 183 #define EMAC_EVCNT_INCR(ev) /* nothing */ 184 #endif 185 186 #define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 187 #define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 188 189 #define EMAC_CDTXSYNC(sc, x, n, ops) \ 190 do { \ 191 int __x, __n; \ 192 \ 193 __x = (x); \ 194 __n = (n); \ 195 \ 196 /* If it will wrap around, sync to the end of the ring. */ \ 197 if ((__x + __n) > EMAC_NTXDESC) { \ 198 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 199 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 200 (EMAC_NTXDESC - __x), (ops)); \ 201 __n -= (EMAC_NTXDESC - __x); \ 202 __x = 0; \ 203 } \ 204 \ 205 /* Now sync whatever is left. */ \ 206 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 207 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 208 } while (/*CONSTCOND*/0) 209 210 #define EMAC_CDRXSYNC(sc, x, ops) \ 211 do { \ 212 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 213 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 214 } while (/*CONSTCOND*/0) 215 216 #define EMAC_INIT_RXDESC(sc, x) \ 217 do { \ 218 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 219 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 220 struct mbuf *__m = __rxs->rxs_mbuf; \ 221 \ 222 /* \ 223 * Note: We scoot the packet forward 2 bytes in the buffer \ 224 * so that the payload after the Ethernet header is aligned \ 225 * to a 4-byte boundary. \ 226 */ \ 227 __m->m_data = __m->m_ext.ext_buf + 2; \ 228 \ 229 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 230 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 231 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 232 /* Set wrap on last descriptor. */ \ 233 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 234 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 235 } while (/*CONSTCOND*/0) 236 237 #define EMAC_WRITE(sc, reg, val) \ 238 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 239 #define EMAC_READ(sc, reg) \ 240 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 241 242 #define EMAC_SET_FILTER(aht, category) \ 243 do { \ 244 (aht)[3 - ((category) >> 4)] |= 1 << ((category) & 0xf); \ 245 } while (/*CONSTCOND*/0) 246 247 static int emac_match(struct device *, struct cfdata *, void *); 248 static void emac_attach(struct device *, struct device *, void *); 249 250 static int emac_add_rxbuf(struct emac_softc *, int); 251 static int emac_init(struct ifnet *); 252 static int emac_ioctl(struct ifnet *, u_long, void *); 253 static void emac_reset(struct emac_softc *); 254 static void emac_rxdrain(struct emac_softc *); 255 static int emac_txreap(struct emac_softc *); 256 static void emac_shutdown(void *); 257 static void emac_start(struct ifnet *); 258 static void emac_stop(struct ifnet *, int); 259 static void emac_watchdog(struct ifnet *); 260 static int emac_set_filter(struct emac_softc *); 261 262 static int emac_wol_intr(void *); 263 static int emac_serr_intr(void *); 264 static int emac_txeob_intr(void *); 265 static int emac_rxeob_intr(void *); 266 static int emac_txde_intr(void *); 267 static int emac_rxde_intr(void *); 268 static int emac_intr(void *); 269 270 static int emac_mii_readreg(struct device *, int, int); 271 static void emac_mii_statchg(struct device *); 272 static void emac_mii_tick(void *); 273 static uint32_t emac_mii_wait(struct emac_softc *); 274 static void emac_mii_writereg(struct device *, int, int, int); 275 276 int emac_copy_small = 0; 277 278 CFATTACH_DECL(emac, sizeof(struct emac_softc), 279 emac_match, emac_attach, NULL, NULL); 280 281 static int 282 emac_match(struct device *parent, struct cfdata *cf, void *aux) 283 { 284 struct opb_attach_args *oaa = aux; 285 286 /* match only on-chip ethernet devices */ 287 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 288 return (1); 289 290 return (0); 291 } 292 293 static void 294 emac_attach(struct device *parent, struct device *self, void *aux) 295 { 296 struct opb_attach_args *oaa = aux; 297 struct emac_softc *sc = (struct emac_softc *)self; 298 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 299 struct mii_data *mii = &sc->sc_mii; 300 bus_dma_segment_t seg; 301 int error, i, nseg; 302 const uint8_t *enaddr; 303 prop_data_t ea; 304 305 bus_space_map(oaa->opb_bt, oaa->opb_addr, EMAC_NREG, 0, &sc->sc_sh); 306 sc->sc_st = oaa->opb_bt; 307 sc->sc_dmat = oaa->opb_dmat; 308 309 printf(": 405GP EMAC\n"); 310 311 callout_init(&sc->sc_callout, 0); 312 313 /* 314 * Set up Mode Register 1 - set receive and transmit FIFOs to maximum 315 * size, allow transmit of multiple packets (only channel 0 is used). 316 * 317 * XXX: Allow pause packets?? 318 */ 319 sc->sc_mr1 = MR1_RFS_4KB | MR1_TFS_2KB | MR1_TR0_MULTIPLE; 320 321 intr_establish(oaa->opb_irq , IST_LEVEL, IPL_NET, emac_wol_intr, sc); 322 intr_establish(oaa->opb_irq + 1, IST_LEVEL, IPL_NET, emac_serr_intr, sc); 323 intr_establish(oaa->opb_irq + 2, IST_LEVEL, IPL_NET, emac_txeob_intr, sc); 324 intr_establish(oaa->opb_irq + 3, IST_LEVEL, IPL_NET, emac_rxeob_intr, sc); 325 intr_establish(oaa->opb_irq + 4, IST_LEVEL, IPL_NET, emac_txde_intr, sc); 326 intr_establish(oaa->opb_irq + 5, IST_LEVEL, IPL_NET, emac_rxde_intr, sc); 327 intr_establish(oaa->opb_irq + 6, IST_LEVEL, IPL_NET, emac_intr, sc); 328 printf("%s: interrupting at irqs %d .. %d\n", sc->sc_dev.dv_xname, 329 oaa->opb_irq, oaa->opb_irq + 6); 330 331 /* 332 * Allocate the control data structures, and create and load the 333 * DMA map for it. 334 */ 335 if ((error = bus_dmamem_alloc(sc->sc_dmat, 336 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 337 printf("%s: unable to allocate control data, error = %d\n", 338 sc->sc_dev.dv_xname, error); 339 goto fail_0; 340 } 341 342 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 343 sizeof(struct emac_control_data), (void **)&sc->sc_control_data, 344 BUS_DMA_COHERENT)) != 0) { 345 printf("%s: unable to map control data, error = %d\n", 346 sc->sc_dev.dv_xname, error); 347 goto fail_1; 348 } 349 350 if ((error = bus_dmamap_create(sc->sc_dmat, 351 sizeof(struct emac_control_data), 1, 352 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 353 printf("%s: unable to create control data DMA map, " 354 "error = %d\n", sc->sc_dev.dv_xname, error); 355 goto fail_2; 356 } 357 358 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 359 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 360 0)) != 0) { 361 printf("%s: unable to load control data DMA map, error = %d\n", 362 sc->sc_dev.dv_xname, error); 363 goto fail_3; 364 } 365 366 /* 367 * Create the transmit buffer DMA maps. 368 */ 369 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 370 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 371 EMAC_NTXSEGS, MCLBYTES, 0, 0, 372 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 373 printf("%s: unable to create tx DMA map %d, " 374 "error = %d\n", sc->sc_dev.dv_xname, i, error); 375 goto fail_4; 376 } 377 } 378 379 /* 380 * Create the receive buffer DMA maps. 381 */ 382 for (i = 0; i < EMAC_NRXDESC; i++) { 383 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 384 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 385 printf("%s: unable to create rx DMA map %d, " 386 "error = %d\n", sc->sc_dev.dv_xname, i, error); 387 goto fail_5; 388 } 389 sc->sc_rxsoft[i].rxs_mbuf = NULL; 390 } 391 392 /* 393 * Reset the chip to a known state. 394 */ 395 emac_reset(sc); 396 397 /* Fetch the Ethernet address. */ 398 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-address"); 399 if (ea == NULL) { 400 printf("%s: unable to get mac-addr property\n", 401 sc->sc_dev.dv_xname); 402 return; 403 } 404 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 405 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 406 enaddr = prop_data_data_nocopy(ea); 407 408 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 409 ether_sprintf(enaddr)); 410 411 /* 412 * Initialise the media structures. 413 */ 414 mii->mii_ifp = ifp; 415 mii->mii_readreg = emac_mii_readreg; 416 mii->mii_writereg = emac_mii_writereg; 417 mii->mii_statchg = emac_mii_statchg; 418 419 sc->sc_ethercom.ec_mii = mii; 420 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 421 mii_attach(&sc->sc_dev, mii, 0xffffffff, 422 MII_PHY_ANY, MII_OFFSET_ANY, 0); 423 if (LIST_FIRST(&mii->mii_phys) == NULL) { 424 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 425 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 426 } else 427 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 428 429 ifp = &sc->sc_ethercom.ec_if; 430 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 431 ifp->if_softc = sc; 432 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 433 ifp->if_ioctl = emac_ioctl; 434 ifp->if_start = emac_start; 435 ifp->if_watchdog = emac_watchdog; 436 ifp->if_init = emac_init; 437 ifp->if_stop = emac_stop; 438 IFQ_SET_READY(&ifp->if_snd); 439 440 /* 441 * We can support 802.1Q VLAN-sized frames. 442 */ 443 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 444 445 /* 446 * Attach the interface. 447 */ 448 if_attach(ifp); 449 ether_ifattach(ifp, enaddr); 450 451 #ifdef EMAC_EVENT_COUNTERS 452 /* 453 * Attach the event counters. 454 */ 455 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 456 NULL, sc->sc_dev.dv_xname, "rxintr"); 457 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 458 NULL, sc->sc_dev.dv_xname, "txintr"); 459 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 460 NULL, sc->sc_dev.dv_xname, "rxde"); 461 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 462 NULL, sc->sc_dev.dv_xname, "txde"); 463 evcnt_attach_dynamic(&sc->sc_ev_wol, EVCNT_TYPE_INTR, 464 NULL, sc->sc_dev.dv_xname, "wol"); 465 evcnt_attach_dynamic(&sc->sc_ev_serr, EVCNT_TYPE_INTR, 466 NULL, sc->sc_dev.dv_xname, "serr"); 467 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 468 NULL, sc->sc_dev.dv_xname, "intr"); 469 470 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 471 NULL, sc->sc_dev.dv_xname, "txreap"); 472 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 473 NULL, sc->sc_dev.dv_xname, "txsstall"); 474 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 475 NULL, sc->sc_dev.dv_xname, "txdstall"); 476 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 477 NULL, sc->sc_dev.dv_xname, "txdrop"); 478 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 479 NULL, sc->sc_dev.dv_xname, "tu"); 480 #endif /* EMAC_EVENT_COUNTERS */ 481 482 /* 483 * Make sure the interface is shutdown during reboot. 484 */ 485 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 486 if (sc->sc_sdhook == NULL) 487 printf("%s: WARNING: unable to establish shutdown hook\n", 488 sc->sc_dev.dv_xname); 489 490 return; 491 492 /* 493 * Free any resources we've allocated during the failed attach 494 * attempt. Do this in reverse order and fall through. 495 */ 496 fail_5: 497 for (i = 0; i < EMAC_NRXDESC; i++) { 498 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 499 bus_dmamap_destroy(sc->sc_dmat, 500 sc->sc_rxsoft[i].rxs_dmamap); 501 } 502 fail_4: 503 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 504 if (sc->sc_txsoft[i].txs_dmamap != NULL) 505 bus_dmamap_destroy(sc->sc_dmat, 506 sc->sc_txsoft[i].txs_dmamap); 507 } 508 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 509 fail_3: 510 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 511 fail_2: 512 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 513 sizeof(struct emac_control_data)); 514 fail_1: 515 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 516 fail_0: 517 return; 518 } 519 520 /* 521 * Device shutdown routine. 522 */ 523 static void 524 emac_shutdown(void *arg) 525 { 526 struct emac_softc *sc = arg; 527 528 emac_stop(&sc->sc_ethercom.ec_if, 0); 529 } 530 531 /* ifnet interface function */ 532 static void 533 emac_start(struct ifnet *ifp) 534 { 535 struct emac_softc *sc = ifp->if_softc; 536 struct mbuf *m0; 537 struct emac_txsoft *txs; 538 bus_dmamap_t dmamap; 539 int error, firsttx, nexttx, lasttx, ofree, seg; 540 541 lasttx = 0; /* XXX gcc */ 542 543 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 544 return; 545 546 /* 547 * Remember the previous number of free descriptors. 548 */ 549 ofree = sc->sc_txfree; 550 551 /* 552 * Loop through the send queue, setting up transmit descriptors 553 * until we drain the queue, or use up all available transmit 554 * descriptors. 555 */ 556 for (;;) { 557 /* Grab a packet off the queue. */ 558 IFQ_POLL(&ifp->if_snd, m0); 559 if (m0 == NULL) 560 break; 561 562 /* 563 * Get a work queue entry. Reclaim used Tx descriptors if 564 * we are running low. 565 */ 566 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 567 emac_txreap(sc); 568 if (sc->sc_txsfree == 0) { 569 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 570 break; 571 } 572 } 573 574 txs = &sc->sc_txsoft[sc->sc_txsnext]; 575 dmamap = txs->txs_dmamap; 576 577 /* 578 * Load the DMA map. If this fails, the packet either 579 * didn't fit in the alloted number of segments, or we 580 * were short on resources. In this case, we'll copy 581 * and try again. 582 */ 583 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 584 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 585 if (error) { 586 if (error == EFBIG) { 587 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 588 printf("%s: Tx packet consumes too many " 589 "DMA segments, dropping...\n", 590 sc->sc_dev.dv_xname); 591 IFQ_DEQUEUE(&ifp->if_snd, m0); 592 m_freem(m0); 593 continue; 594 } 595 /* Short on resources, just stop for now. */ 596 break; 597 } 598 599 /* 600 * Ensure we have enough descriptors free to describe 601 * the packet. 602 */ 603 if (dmamap->dm_nsegs > sc->sc_txfree) { 604 /* 605 * Not enough free descriptors to transmit this 606 * packet. We haven't committed anything yet, 607 * so just unload the DMA map, put the packet 608 * back on the queue, and punt. Notify the upper 609 * layer that there are not more slots left. 610 * 611 */ 612 ifp->if_flags |= IFF_OACTIVE; 613 bus_dmamap_unload(sc->sc_dmat, dmamap); 614 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 615 break; 616 } 617 618 IFQ_DEQUEUE(&ifp->if_snd, m0); 619 620 /* 621 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 622 */ 623 624 /* Sync the DMA map. */ 625 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 626 BUS_DMASYNC_PREWRITE); 627 628 /* 629 * Store a pointer to the packet so that we can free it 630 * later. 631 */ 632 txs->txs_mbuf = m0; 633 txs->txs_firstdesc = sc->sc_txnext; 634 txs->txs_ndesc = dmamap->dm_nsegs; 635 636 /* 637 * Initialize the transmit descriptor. 638 */ 639 firsttx = sc->sc_txnext; 640 for (nexttx = sc->sc_txnext, seg = 0; 641 seg < dmamap->dm_nsegs; 642 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 643 /* 644 * If this is the first descriptor we're 645 * enqueueing, don't set the TX_READY bit just 646 * yet. That could cause a race condition. 647 * We'll do it below. 648 */ 649 sc->sc_txdescs[nexttx].md_data = 650 dmamap->dm_segs[seg].ds_addr; 651 sc->sc_txdescs[nexttx].md_data_len = 652 dmamap->dm_segs[seg].ds_len; 653 sc->sc_txdescs[nexttx].md_stat_ctrl = 654 (sc->sc_txdescs[nexttx].md_stat_ctrl & MAL_TX_WRAP) | 655 (nexttx == firsttx ? 0 : MAL_TX_READY) | 656 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 657 lasttx = nexttx; 658 } 659 660 /* Set the LAST bit on the last segment. */ 661 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 662 663 /* 664 * Set up last segment descriptor to send an interrupt after 665 * that descriptor is transmitted, and bypass existing Tx 666 * descriptor reaping method (for now...). 667 */ 668 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_INTERRUPT; 669 670 671 txs->txs_lastdesc = lasttx; 672 673 /* Sync the descriptors we're using. */ 674 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 675 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 676 677 /* 678 * The entire packet chain is set up. Give the 679 * first descriptor to the chip now. 680 */ 681 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 682 EMAC_CDTXSYNC(sc, firsttx, 1, 683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 684 /* 685 * Tell the EMAC that a new packet is available. 686 */ 687 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0); 688 689 /* Advance the tx pointer. */ 690 sc->sc_txfree -= txs->txs_ndesc; 691 sc->sc_txnext = nexttx; 692 693 sc->sc_txsfree--; 694 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 695 696 /* 697 * Pass the packet to any BPF listeners. 698 */ 699 if (ifp->if_bpf) 700 bpf_ops->bpf_mtap(ifp->if_bpf, m0); 701 } 702 703 if (sc->sc_txfree == 0) { 704 /* No more slots left; notify upper layer. */ 705 ifp->if_flags |= IFF_OACTIVE; 706 } 707 708 if (sc->sc_txfree != ofree) { 709 /* Set a watchdog timer in case the chip flakes out. */ 710 ifp->if_timer = 5; 711 } 712 } 713 714 static int 715 emac_init(struct ifnet *ifp) 716 { 717 struct emac_softc *sc = ifp->if_softc; 718 struct emac_rxsoft *rxs; 719 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 720 int error, i; 721 722 error = 0; 723 724 /* Cancel any pending I/O. */ 725 emac_stop(ifp, 0); 726 727 /* Reset the chip to a known state. */ 728 emac_reset(sc); 729 730 /* 731 * Initialise the transmit descriptor ring. 732 */ 733 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 734 /* set wrap on last descriptor */ 735 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 736 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 737 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 738 sc->sc_txfree = EMAC_NTXDESC; 739 sc->sc_txnext = 0; 740 741 /* 742 * Initialise the transmit job descriptors. 743 */ 744 for (i = 0; i < EMAC_TXQUEUELEN; i++) 745 sc->sc_txsoft[i].txs_mbuf = NULL; 746 sc->sc_txsfree = EMAC_TXQUEUELEN; 747 sc->sc_txsnext = 0; 748 sc->sc_txsdirty = 0; 749 750 /* 751 * Initialise the receiver descriptor and receive job 752 * descriptor rings. 753 */ 754 for (i = 0; i < EMAC_NRXDESC; i++) { 755 rxs = &sc->sc_rxsoft[i]; 756 if (rxs->rxs_mbuf == NULL) { 757 if ((error = emac_add_rxbuf(sc, i)) != 0) { 758 printf("%s: unable to allocate or map rx " 759 "buffer %d, error = %d\n", 760 sc->sc_dev.dv_xname, i, error); 761 /* 762 * XXX Should attempt to run with fewer receive 763 * XXX buffers instead of just failing. 764 */ 765 emac_rxdrain(sc); 766 goto out; 767 } 768 } else 769 EMAC_INIT_RXDESC(sc, i); 770 } 771 sc->sc_rxptr = 0; 772 773 /* 774 * Set the current media. 775 */ 776 if ((error = ether_mediachange(ifp)) != 0) 777 goto out; 778 779 /* 780 * Give the transmit and receive rings to the MAL. 781 */ 782 mtdcr(DCR_MAL0_TXCTP0R, EMAC_CDTXADDR(sc, 0)); 783 mtdcr(DCR_MAL0_RXCTP0R, EMAC_CDRXADDR(sc, 0)); 784 785 /* 786 * Load the MAC address. 787 */ 788 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 789 EMAC_WRITE(sc, EMAC_IALR, 790 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 791 792 /* 793 * Set the receive channel buffer size (in units of 16 bytes). 794 */ 795 #if MCLBYTES > (4096 - 16) /* XXX! */ 796 # error MCLBYTES > max rx channel buffer size 797 #endif 798 mtdcr(DCR_MAL0_RCBS0, MCLBYTES / 16); 799 800 /* Set fifos, media modes. */ 801 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 802 803 /* 804 * Enable Individual and (possibly) Broadcast Address modes, 805 * runt packets, and strip padding. 806 */ 807 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | 808 (ifp->if_flags & IFF_PROMISC ? RMR_PME : 0) | 809 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 810 811 /* 812 * Set multicast filter. 813 */ 814 emac_set_filter(sc); 815 816 /* 817 * Set low- and urgent-priority request thresholds. 818 */ 819 EMAC_WRITE(sc, EMAC_TMR1, 820 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 821 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 822 /* 823 * Set Transmit Request Threshold Register. 824 */ 825 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 826 827 /* 828 * Set high and low receive watermarks. 829 */ 830 EMAC_WRITE(sc, EMAC_RWMR, 831 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 832 833 /* 834 * Set frame gap. 835 */ 836 EMAC_WRITE(sc, EMAC_IPGVR, 8); 837 838 /* 839 * Set interrupt status enable bits for EMAC and MAL. 840 */ 841 EMAC_WRITE(sc, EMAC_ISER, 842 ISR_BP | ISR_SE | ISR_ALE | ISR_BFCS | ISR_PTLE | ISR_ORE | ISR_IRE); 843 mtdcr(DCR_MAL0_IER, MAL0_IER_DE | MAL0_IER_NWE | MAL0_IER_TO | 844 MAL0_IER_OPB | MAL0_IER_PLB); 845 846 /* 847 * Enable the transmit and receive channel on the MAL. 848 */ 849 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 850 mtdcr(DCR_MAL0_TXCASR, MAL0_TXCASR_CHAN0); 851 852 /* 853 * Enable the transmit and receive channel on the EMAC. 854 */ 855 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 856 857 /* 858 * Start the one second MII clock. 859 */ 860 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 861 862 /* 863 * ... all done! 864 */ 865 ifp->if_flags |= IFF_RUNNING; 866 ifp->if_flags &= ~IFF_OACTIVE; 867 868 out: 869 if (error) { 870 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 871 ifp->if_timer = 0; 872 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 873 } 874 return (error); 875 } 876 877 static int 878 emac_add_rxbuf(struct emac_softc *sc, int idx) 879 { 880 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 881 struct mbuf *m; 882 int error; 883 884 MGETHDR(m, M_DONTWAIT, MT_DATA); 885 if (m == NULL) 886 return (ENOBUFS); 887 888 MCLGET(m, M_DONTWAIT); 889 if ((m->m_flags & M_EXT) == 0) { 890 m_freem(m); 891 return (ENOBUFS); 892 } 893 894 if (rxs->rxs_mbuf != NULL) 895 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 896 897 rxs->rxs_mbuf = m; 898 899 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 900 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 901 if (error) { 902 printf("%s: can't load rx DMA map %d, error = %d\n", 903 sc->sc_dev.dv_xname, idx, error); 904 panic("emac_add_rxbuf"); /* XXX */ 905 } 906 907 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 908 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 909 910 EMAC_INIT_RXDESC(sc, idx); 911 912 return (0); 913 } 914 915 /* ifnet interface function */ 916 static void 917 emac_watchdog(struct ifnet *ifp) 918 { 919 struct emac_softc *sc = ifp->if_softc; 920 921 /* 922 * Since we're not interrupting every packet, sweep 923 * up before we report an error. 924 */ 925 emac_txreap(sc); 926 927 if (sc->sc_txfree != EMAC_NTXDESC) { 928 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 929 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 930 sc->sc_txnext); 931 ifp->if_oerrors++; 932 933 /* Reset the interface. */ 934 (void)emac_init(ifp); 935 } else if (ifp->if_flags & IFF_DEBUG) 936 printf("%s: recovered from device timeout\n", 937 sc->sc_dev.dv_xname); 938 939 /* try to get more packets going */ 940 emac_start(ifp); 941 } 942 943 static void 944 emac_rxdrain(struct emac_softc *sc) 945 { 946 struct emac_rxsoft *rxs; 947 int i; 948 949 for (i = 0; i < EMAC_NRXDESC; i++) { 950 rxs = &sc->sc_rxsoft[i]; 951 if (rxs->rxs_mbuf != NULL) { 952 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 953 m_freem(rxs->rxs_mbuf); 954 rxs->rxs_mbuf = NULL; 955 } 956 } 957 } 958 959 /* ifnet interface function */ 960 static void 961 emac_stop(struct ifnet *ifp, int disable) 962 { 963 struct emac_softc *sc = ifp->if_softc; 964 struct emac_txsoft *txs; 965 int i; 966 967 /* Stop the one second clock. */ 968 callout_stop(&sc->sc_callout); 969 970 /* Down the MII */ 971 mii_down(&sc->sc_mii); 972 973 /* Disable interrupts. */ 974 #if 0 /* Can't disable MAL interrupts without a reset... */ 975 EMAC_WRITE(sc, EMAC_ISER, 0); 976 #endif 977 mtdcr(DCR_MAL0_IER, 0); 978 979 /* Disable the receive and transmit channels. */ 980 mtdcr(DCR_MAL0_RXCARR, MAL0_RXCARR_CHAN0); 981 mtdcr(DCR_MAL0_TXCARR, MAL0_TXCARR_CHAN0 | MAL0_TXCARR_CHAN1); 982 983 /* Disable the transmit enable and receive MACs. */ 984 EMAC_WRITE(sc, EMAC_MR0, 985 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 986 987 /* Release any queued transmit buffers. */ 988 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 989 txs = &sc->sc_txsoft[i]; 990 if (txs->txs_mbuf != NULL) { 991 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 992 m_freem(txs->txs_mbuf); 993 txs->txs_mbuf = NULL; 994 } 995 } 996 997 if (disable) 998 emac_rxdrain(sc); 999 1000 /* 1001 * Mark the interface down and cancel the watchdog timer. 1002 */ 1003 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1004 ifp->if_timer = 0; 1005 } 1006 1007 /* ifnet interface function */ 1008 static int 1009 emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1010 { 1011 struct emac_softc *sc = ifp->if_softc; 1012 int s, error; 1013 1014 s = splnet(); 1015 1016 error = ether_ioctl(ifp, cmd, data); 1017 if (error == ENETRESET) { 1018 /* 1019 * Multicast list has changed; set the hardware filter 1020 * accordingly. 1021 */ 1022 if (ifp->if_flags & IFF_RUNNING) 1023 error = emac_set_filter(sc); 1024 else 1025 error = 0; 1026 } 1027 1028 /* try to get more packets going */ 1029 emac_start(ifp); 1030 1031 splx(s); 1032 return (error); 1033 } 1034 1035 static void 1036 emac_reset(struct emac_softc *sc) 1037 { 1038 1039 /* reset the MAL */ 1040 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR); 1041 1042 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1043 delay(5); 1044 1045 /* XXX: check if MR0_SRST is clear until a timeout instead? */ 1046 EMAC_WRITE(sc, EMAC_MR0, EMAC_READ(sc, EMAC_MR0) & ~MR0_SRST); 1047 1048 /* XXX clear interrupts in EMAC_ISR just to be sure?? */ 1049 1050 /* set the MAL config register */ 1051 mtdcr(DCR_MAL0_CFG, MAL0_CFG_PLBB | MAL0_CFG_OPBBL | MAL0_CFG_LEA | 1052 MAL0_CFG_SD | MAL0_CFG_PLBLT); 1053 } 1054 1055 static int 1056 emac_set_filter(struct emac_softc *sc) 1057 { 1058 struct ether_multistep step; 1059 struct ether_multi *enm; 1060 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1061 uint32_t rmr, crc, gaht[4] = {0, 0, 0, 0}; 1062 int category, cnt = 0; 1063 1064 rmr = EMAC_READ(sc, EMAC_RMR); 1065 rmr &= ~(RMR_PMME | RMR_MAE); 1066 ifp->if_flags &= ~IFF_ALLMULTI; 1067 1068 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1069 while (enm != NULL) { 1070 if (memcmp(enm->enm_addrlo, 1071 enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1072 /* 1073 * We must listen to a range of multicast addresses. 1074 * For now, just accept all multicasts, rather than 1075 * trying to set only those filter bits needed to match 1076 * the range. (At this time, the only use of address 1077 * ranges is for IP multicast routing, for which the 1078 * range is big enough to require all bits set.) 1079 */ 1080 gaht[0] = gaht[1] = gaht[2] = gaht[3] = 0xffff; 1081 break; 1082 } 1083 1084 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1085 1086 /* Just want the 6 most significant bits. */ 1087 category = crc >> 26; 1088 EMAC_SET_FILTER(gaht, category); 1089 1090 ETHER_NEXT_MULTI(step, enm); 1091 cnt++; 1092 } 1093 1094 if ((gaht[0] & gaht[1] & gaht[2] & gaht[3]) == 0xffff) { 1095 /* All categories are true. */ 1096 ifp->if_flags |= IFF_ALLMULTI; 1097 rmr |= RMR_PMME; 1098 } else if (cnt != 0) { 1099 /* Some categories are true. */ 1100 EMAC_WRITE(sc, EMAC_GAHT1, gaht[0]); 1101 EMAC_WRITE(sc, EMAC_GAHT2, gaht[1]); 1102 EMAC_WRITE(sc, EMAC_GAHT3, gaht[2]); 1103 EMAC_WRITE(sc, EMAC_GAHT4, gaht[3]); 1104 1105 rmr |= RMR_MAE; 1106 } 1107 EMAC_WRITE(sc, EMAC_RMR, rmr); 1108 1109 return 0; 1110 } 1111 1112 /* 1113 * EMAC General interrupt handler 1114 */ 1115 static int 1116 emac_intr(void *arg) 1117 { 1118 struct emac_softc *sc = arg; 1119 uint32_t status; 1120 1121 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 1122 status = EMAC_READ(sc, EMAC_ISR); 1123 1124 /* Clear the interrupt status bits. */ 1125 EMAC_WRITE(sc, EMAC_ISR, status); 1126 1127 return (0); 1128 } 1129 1130 /* 1131 * EMAC Wake-On-LAN interrupt handler 1132 */ 1133 static int 1134 emac_wol_intr(void *arg) 1135 { 1136 struct emac_softc *sc = arg; 1137 1138 EMAC_EVCNT_INCR(&sc->sc_ev_wol); 1139 printf("%s: emac_wol_intr\n", sc->sc_dev.dv_xname); 1140 return (0); 1141 } 1142 1143 /* 1144 * MAL System ERRor interrupt handler 1145 */ 1146 static int 1147 emac_serr_intr(void *arg) 1148 { 1149 #ifdef EMAC_EVENT_COUNTERS 1150 struct emac_softc *sc = arg; 1151 #endif 1152 u_int32_t esr; 1153 1154 EMAC_EVCNT_INCR(&sc->sc_ev_serr); 1155 esr = mfdcr(DCR_MAL0_ESR); 1156 1157 /* Clear the interrupt status bits. */ 1158 mtdcr(DCR_MAL0_ESR, esr); 1159 return (0); 1160 } 1161 1162 /* 1163 * MAL Transmit End-Of-Buffer interrupt handler. 1164 * NOTE: This shouldn't be called! 1165 */ 1166 static int 1167 emac_txeob_intr(void *arg) 1168 { 1169 struct emac_softc *sc = arg; 1170 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1171 int handled; 1172 1173 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1174 handled = emac_txreap(arg); 1175 1176 /* try to get more packets going */ 1177 emac_start(ifp); 1178 1179 return (handled); 1180 1181 } 1182 1183 /* 1184 * Reap completed Tx descriptors. 1185 */ 1186 static int 1187 emac_txreap(struct emac_softc *sc) 1188 { 1189 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1190 struct emac_txsoft *txs; 1191 int handled, i; 1192 u_int32_t txstat; 1193 1194 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1195 handled = 0; 1196 1197 /* Clear the interrupt */ 1198 mtdcr(DCR_MAL0_TXEOBISR, mfdcr(DCR_MAL0_TXEOBISR)); 1199 1200 ifp->if_flags &= ~IFF_OACTIVE; 1201 1202 /* 1203 * Go through our Tx list and free mbufs for those 1204 * frames that have been transmitted. 1205 */ 1206 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1207 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1208 txs = &sc->sc_txsoft[i]; 1209 1210 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1211 txs->txs_dmamap->dm_nsegs, 1212 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1213 1214 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1215 if (txstat & MAL_TX_READY) 1216 break; 1217 1218 handled = 1; 1219 1220 /* 1221 * Check for errors and collisions. 1222 */ 1223 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1224 ifp->if_oerrors++; 1225 1226 #ifdef EMAC_EVENT_COUNTERS 1227 if (txstat & EMAC_TXS_UR) 1228 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1229 #endif /* EMAC_EVENT_COUNTERS */ 1230 1231 if (txstat & (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1232 if (txstat & EMAC_TXS_EC) 1233 ifp->if_collisions += 16; 1234 else if (txstat & EMAC_TXS_MC) 1235 ifp->if_collisions += 2; /* XXX? */ 1236 else if (txstat & EMAC_TXS_SC) 1237 ifp->if_collisions++; 1238 if (txstat & EMAC_TXS_LC) 1239 ifp->if_collisions++; 1240 } else 1241 ifp->if_opackets++; 1242 1243 if (ifp->if_flags & IFF_DEBUG) { 1244 if (txstat & EMAC_TXS_ED) 1245 printf("%s: excessive deferral\n", 1246 sc->sc_dev.dv_xname); 1247 if (txstat & EMAC_TXS_EC) 1248 printf("%s: excessive collisions\n", 1249 sc->sc_dev.dv_xname); 1250 } 1251 1252 sc->sc_txfree += txs->txs_ndesc; 1253 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1254 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1255 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1256 m_freem(txs->txs_mbuf); 1257 txs->txs_mbuf = NULL; 1258 } 1259 1260 /* Update the dirty transmit buffer pointer. */ 1261 sc->sc_txsdirty = i; 1262 1263 /* 1264 * If there are no more pending transmissions, cancel the watchdog 1265 * timer. 1266 */ 1267 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1268 ifp->if_timer = 0; 1269 1270 return (handled); 1271 } 1272 1273 /* 1274 * MAL Receive End-Of-Buffer interrupt handler 1275 */ 1276 static int 1277 emac_rxeob_intr(void *arg) 1278 { 1279 struct emac_softc *sc = arg; 1280 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1281 struct emac_rxsoft *rxs; 1282 struct mbuf *m; 1283 u_int32_t rxstat; 1284 int i, len; 1285 1286 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1287 1288 /* Clear the interrupt */ 1289 mtdcr(DCR_MAL0_RXEOBISR, mfdcr(DCR_MAL0_RXEOBISR)); 1290 1291 for (i = sc->sc_rxptr;; i = EMAC_NEXTRX(i)) { 1292 rxs = &sc->sc_rxsoft[i]; 1293 1294 EMAC_CDRXSYNC(sc, i, 1295 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1296 1297 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1298 1299 if (rxstat & MAL_RX_EMPTY) 1300 /* 1301 * We have processed all of the receive buffers. 1302 */ 1303 break; 1304 1305 /* 1306 * If an error occurred, update stats, clear the status 1307 * word, and leave the packet buffer in place. It will 1308 * simply be reused the next time the ring comes around. 1309 */ 1310 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1311 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1312 EMAC_RXS_IRE)) { 1313 #define PRINTERR(bit, str) \ 1314 if (rxstat & (bit)) \ 1315 printf("%s: receive error: %s\n", \ 1316 sc->sc_dev.dv_xname, str) 1317 ifp->if_ierrors++; 1318 PRINTERR(EMAC_RXS_OE, "overrun error"); 1319 PRINTERR(EMAC_RXS_BP, "bad packet"); 1320 PRINTERR(EMAC_RXS_RP, "runt packet"); 1321 PRINTERR(EMAC_RXS_SE, "short event"); 1322 PRINTERR(EMAC_RXS_AE, "alignment error"); 1323 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1324 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1325 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1326 PRINTERR(EMAC_RXS_IRE, "in range error"); 1327 #undef PRINTERR 1328 EMAC_INIT_RXDESC(sc, i); 1329 continue; 1330 } 1331 1332 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1333 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1334 1335 /* 1336 * No errors; receive the packet. Note, the 405GP emac 1337 * includes the CRC with every packet. 1338 */ 1339 len = sc->sc_rxdescs[i].md_data_len - ETHER_CRC_LEN; 1340 1341 /* 1342 * If the packet is small enough to fit in a 1343 * single header mbuf, allocate one and copy 1344 * the data into it. This greatly reduces 1345 * memory consumption when we receive lots 1346 * of small packets. 1347 * 1348 * Otherwise, we add a new buffer to the receive 1349 * chain. If this fails, we drop the packet and 1350 * recycle the old buffer. 1351 */ 1352 if (emac_copy_small != 0 && len <= MHLEN) { 1353 MGETHDR(m, M_DONTWAIT, MT_DATA); 1354 if (m == NULL) 1355 goto dropit; 1356 memcpy(mtod(m, void *), 1357 mtod(rxs->rxs_mbuf, void *), len); 1358 EMAC_INIT_RXDESC(sc, i); 1359 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1360 rxs->rxs_dmamap->dm_mapsize, 1361 BUS_DMASYNC_PREREAD); 1362 } else { 1363 m = rxs->rxs_mbuf; 1364 if (emac_add_rxbuf(sc, i) != 0) { 1365 dropit: 1366 ifp->if_ierrors++; 1367 EMAC_INIT_RXDESC(sc, i); 1368 bus_dmamap_sync(sc->sc_dmat, 1369 rxs->rxs_dmamap, 0, 1370 rxs->rxs_dmamap->dm_mapsize, 1371 BUS_DMASYNC_PREREAD); 1372 continue; 1373 } 1374 } 1375 1376 ifp->if_ipackets++; 1377 m->m_pkthdr.rcvif = ifp; 1378 m->m_pkthdr.len = m->m_len = len; 1379 1380 /* 1381 * Pass this up to any BPF listeners, but only 1382 * pass if up the stack if it's for us. 1383 */ 1384 if (ifp->if_bpf) 1385 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1386 1387 /* Pass it on. */ 1388 (*ifp->if_input)(ifp, m); 1389 } 1390 1391 /* Update the receive pointer. */ 1392 sc->sc_rxptr = i; 1393 1394 return (0); 1395 } 1396 1397 /* 1398 * MAL Transmit Descriptor Error interrupt handler 1399 */ 1400 static int 1401 emac_txde_intr(void *arg) 1402 { 1403 struct emac_softc *sc = arg; 1404 1405 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1406 printf("%s: emac_txde_intr\n", sc->sc_dev.dv_xname); 1407 return (0); 1408 } 1409 1410 /* 1411 * MAL Receive Descriptor Error interrupt handler 1412 */ 1413 static int 1414 emac_rxde_intr(void *arg) 1415 { 1416 int i; 1417 struct emac_softc *sc = arg; 1418 1419 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1420 printf("%s: emac_rxde_intr\n", sc->sc_dev.dv_xname); 1421 /* 1422 * XXX! 1423 * This is a bit drastic; we just drop all descriptors that aren't 1424 * "clean". We should probably send any that are up the stack. 1425 */ 1426 for (i = 0; i < EMAC_NRXDESC; i++) { 1427 EMAC_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1428 1429 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) { 1430 EMAC_INIT_RXDESC(sc, i); 1431 } 1432 1433 } 1434 1435 /* Reenable the receive channel */ 1436 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 1437 1438 /* Clear the interrupt */ 1439 mtdcr(DCR_MAL0_RXDEIR, mfdcr(DCR_MAL0_RXDEIR)); 1440 1441 return (0); 1442 } 1443 1444 static uint32_t 1445 emac_mii_wait(struct emac_softc *sc) 1446 { 1447 int i; 1448 uint32_t reg; 1449 1450 /* wait for PHY data transfer to complete */ 1451 i = 0; 1452 while ((reg = EMAC_READ(sc, EMAC_STACR) & STACR_OC) == 0) { 1453 delay(7); 1454 if (i++ > 5) { 1455 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1456 return (0); 1457 } 1458 } 1459 return (reg); 1460 } 1461 1462 static int 1463 emac_mii_readreg(struct device *self, int phy, int reg) 1464 { 1465 struct emac_softc *sc = (struct emac_softc *)self; 1466 uint32_t sta_reg; 1467 1468 /* wait for PHY data transfer to complete */ 1469 if (emac_mii_wait(sc) == 0) 1470 return (0); 1471 1472 sta_reg = reg << STACR_PRASHIFT; 1473 sta_reg |= STACR_READ; 1474 sta_reg |= phy << STACR_PCDASHIFT; 1475 1476 sta_reg &= ~STACR_OPBC_MASK; 1477 sta_reg |= STACR_OPBC_50MHZ; 1478 1479 1480 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1481 1482 if ((sta_reg = emac_mii_wait(sc)) == 0) 1483 return (0); 1484 sta_reg = EMAC_READ(sc, EMAC_STACR); 1485 if ((sta_reg & STACR_PHYE) != 0) 1486 return (0); 1487 return (sta_reg >> STACR_PHYDSHIFT); 1488 } 1489 1490 static void 1491 emac_mii_writereg(struct device *self, int phy, int reg, int val) 1492 { 1493 struct emac_softc *sc = (struct emac_softc *)self; 1494 uint32_t sta_reg; 1495 1496 /* wait for PHY data transfer to complete */ 1497 if (emac_mii_wait(sc) == 0) 1498 return; 1499 1500 sta_reg = reg << STACR_PRASHIFT; 1501 sta_reg |= STACR_WRITE; 1502 sta_reg |= phy << STACR_PCDASHIFT; 1503 1504 sta_reg &= ~STACR_OPBC_MASK; 1505 sta_reg |= STACR_OPBC_50MHZ; 1506 1507 sta_reg |= val << STACR_PHYDSHIFT; 1508 1509 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1510 1511 if ((sta_reg = emac_mii_wait(sc)) == 0) 1512 return; 1513 if ((sta_reg & STACR_PHYE) != 0) 1514 /* error */ 1515 return; 1516 } 1517 1518 static void 1519 emac_mii_statchg(struct device *self) 1520 { 1521 struct emac_softc *sc = (void *)self; 1522 1523 if (sc->sc_mii.mii_media_active & IFM_FDX) 1524 sc->sc_mr1 |= MR1_FDE; 1525 else 1526 sc->sc_mr1 &= ~(MR1_FDE | MR1_EIFC); 1527 1528 /* XXX 802.1x flow-control? */ 1529 1530 /* 1531 * MR1 can only be written immediately after a reset... 1532 */ 1533 emac_reset(sc); 1534 } 1535 1536 static void 1537 emac_mii_tick(void *arg) 1538 { 1539 struct emac_softc *sc = arg; 1540 int s; 1541 1542 if (!device_is_active(&sc->sc_dev)) 1543 return; 1544 1545 s = splnet(); 1546 mii_tick(&sc->sc_mii); 1547 splx(s); 1548 1549 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1550 } 1551