1 /* $NetBSD: if_emac.c,v 1.51 2019/05/28 07:41:48 msaitoh Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * emac(4) supports following ibm4xx's EMACs. 40 * XXXX: ZMII and 'TCP Accelaration Hardware' not support yet... 41 * 42 * tested 43 * ------ 44 * 405EP - 10/100 x2 45 * 405EX/EXr o 10/100/1000 x2 (EXr x1), STA v2, 256bit hash-Table, RGMII 46 * 405GP/GPr o 10/100 47 * 440EP - 10/100 x2, ZMII 48 * 440GP - 10/100 x2, ZMII 49 * 440GX - 10/100/1000 x4, ZMII/RGMII(ch 2, 3), TAH(ch 2, 3) 50 * 440SP - 10/100/1000 51 * 440SPe - 10/100/1000, STA v2 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.51 2019/05/28 07:41:48 msaitoh Exp $"); 56 57 #include "opt_emac.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/mbuf.h> 62 #include <sys/kernel.h> 63 #include <sys/socket.h> 64 #include <sys/ioctl.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #include <net/if.h> 71 #include <net/if_dl.h> 72 #include <net/if_media.h> 73 #include <net/if_ether.h> 74 75 #include <net/bpf.h> 76 77 #include <powerpc/ibm4xx/cpu.h> 78 #include <powerpc/ibm4xx/dcr4xx.h> 79 #include <powerpc/ibm4xx/mal405gp.h> 80 #include <powerpc/ibm4xx/dev/emacreg.h> 81 #include <powerpc/ibm4xx/dev/if_emacreg.h> 82 #include <powerpc/ibm4xx/dev/if_emacvar.h> 83 #include <powerpc/ibm4xx/dev/malvar.h> 84 #include <powerpc/ibm4xx/dev/opbreg.h> 85 #include <powerpc/ibm4xx/dev/opbvar.h> 86 #include <powerpc/ibm4xx/dev/plbvar.h> 87 #if defined(EMAC_ZMII_PHY) || defined(EMAC_RGMII_PHY) 88 #include <powerpc/ibm4xx/dev/rmiivar.h> 89 #endif 90 91 #include <dev/mii/miivar.h> 92 93 #include "locators.h" 94 95 96 /* 97 * Transmit descriptor list size. There are two Tx channels, each with 98 * up to 256 hardware descriptors available. We currently use one Tx 99 * channel. We tell the upper layers that they can queue a lot of 100 * packets, and we go ahead and manage up to 64 of them at a time. We 101 * allow up to 16 DMA segments per packet. 102 */ 103 #define EMAC_NTXSEGS 16 104 #define EMAC_TXQUEUELEN 64 105 #define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 106 #define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 107 #define EMAC_NTXDESC 256 108 #define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 109 #define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 110 #define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 111 112 /* 113 * Receive descriptor list size. There is one Rx channel with up to 256 114 * hardware descriptors available. We allocate 64 receive descriptors, 115 * each with a 2k buffer (MCLBYTES). 116 */ 117 #define EMAC_NRXDESC 64 118 #define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 119 #define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 120 #define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 121 122 /* 123 * Transmit/receive descriptors that are DMA'd to the EMAC. 124 */ 125 struct emac_control_data { 126 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 127 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 128 }; 129 130 #define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 131 #define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 132 #define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 133 134 /* 135 * Software state for transmit jobs. 136 */ 137 struct emac_txsoft { 138 struct mbuf *txs_mbuf; /* head of mbuf chain */ 139 bus_dmamap_t txs_dmamap; /* our DMA map */ 140 int txs_firstdesc; /* first descriptor in packet */ 141 int txs_lastdesc; /* last descriptor in packet */ 142 int txs_ndesc; /* # of descriptors used */ 143 }; 144 145 /* 146 * Software state for receive descriptors. 147 */ 148 struct emac_rxsoft { 149 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 150 bus_dmamap_t rxs_dmamap; /* our DMA map */ 151 }; 152 153 /* 154 * Software state per device. 155 */ 156 struct emac_softc { 157 device_t sc_dev; /* generic device information */ 158 int sc_instance; /* instance no. */ 159 bus_space_tag_t sc_st; /* bus space tag */ 160 bus_space_handle_t sc_sh; /* bus space handle */ 161 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 162 struct ethercom sc_ethercom; /* ethernet common data */ 163 void *sc_sdhook; /* shutdown hook */ 164 void *sc_powerhook; /* power management hook */ 165 166 struct mii_data sc_mii; /* MII/media information */ 167 struct callout sc_callout; /* tick callout */ 168 169 uint32_t sc_mr1; /* copy of Mode Register 1 */ 170 uint32_t sc_stacr_read; /* Read opcode of STAOPC of STACR */ 171 uint32_t sc_stacr_write; /* Write opcode of STAOPC of STACR */ 172 uint32_t sc_stacr_bits; /* misc bits of STACR */ 173 bool sc_stacr_completed; /* Operation completed of STACR */ 174 int sc_htsize; /* Hash Table size */ 175 176 bus_dmamap_t sc_cddmamap; /* control data dma map */ 177 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 178 179 /* Software state for transmit/receive descriptors. */ 180 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 181 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 182 183 /* Control data structures. */ 184 struct emac_control_data *sc_control_data; 185 #define sc_txdescs sc_control_data->ecd_txdesc 186 #define sc_rxdescs sc_control_data->ecd_rxdesc 187 188 #ifdef EMAC_EVENT_COUNTERS 189 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 190 struct evcnt sc_ev_txintr; /* Tx interrupts */ 191 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 192 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 193 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 194 195 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 196 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 197 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 198 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 199 struct evcnt sc_ev_tu; /* Tx underrun */ 200 #endif /* EMAC_EVENT_COUNTERS */ 201 202 int sc_txfree; /* number of free Tx descriptors */ 203 int sc_txnext; /* next ready Tx descriptor */ 204 205 int sc_txsfree; /* number of free Tx jobs */ 206 int sc_txsnext; /* next ready Tx job */ 207 int sc_txsdirty; /* dirty Tx jobs */ 208 209 int sc_rxptr; /* next ready RX descriptor/descsoft */ 210 211 void (*sc_rmii_enable)(device_t, int); /* reduced MII enable */ 212 void (*sc_rmii_disable)(device_t, int); /* reduced MII disable*/ 213 void (*sc_rmii_speed)(device_t, int, int); /* reduced MII speed */ 214 }; 215 216 #ifdef EMAC_EVENT_COUNTERS 217 #define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 218 #else 219 #define EMAC_EVCNT_INCR(ev) /* nothing */ 220 #endif 221 222 #define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 223 #define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 224 225 #define EMAC_CDTXSYNC(sc, x, n, ops) \ 226 do { \ 227 int __x, __n; \ 228 \ 229 __x = (x); \ 230 __n = (n); \ 231 \ 232 /* If it will wrap around, sync to the end of the ring. */ \ 233 if ((__x + __n) > EMAC_NTXDESC) { \ 234 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 235 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 236 (EMAC_NTXDESC - __x), (ops)); \ 237 __n -= (EMAC_NTXDESC - __x); \ 238 __x = 0; \ 239 } \ 240 \ 241 /* Now sync whatever is left. */ \ 242 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 243 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 244 } while (/*CONSTCOND*/0) 245 246 #define EMAC_CDRXSYNC(sc, x, ops) \ 247 do { \ 248 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 249 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 250 } while (/*CONSTCOND*/0) 251 252 #define EMAC_INIT_RXDESC(sc, x) \ 253 do { \ 254 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 255 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 256 struct mbuf *__m = __rxs->rxs_mbuf; \ 257 \ 258 /* \ 259 * Note: We scoot the packet forward 2 bytes in the buffer \ 260 * so that the payload after the Ethernet header is aligned \ 261 * to a 4-byte boundary. \ 262 */ \ 263 __m->m_data = __m->m_ext.ext_buf + 2; \ 264 \ 265 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 266 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 267 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 268 /* Set wrap on last descriptor. */ \ 269 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 270 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 271 } while (/*CONSTCOND*/0) 272 273 #define EMAC_WRITE(sc, reg, val) \ 274 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 275 #define EMAC_READ(sc, reg) \ 276 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 277 278 #define EMAC_SET_FILTER(aht, crc) \ 279 do { \ 280 (aht)[3 - (((crc) >> 26) >> 4)] |= 1 << (((crc) >> 26) & 0xf); \ 281 } while (/*CONSTCOND*/0) 282 #define EMAC_SET_FILTER256(aht, crc) \ 283 do { \ 284 (aht)[7 - (((crc) >> 24) >> 5)] |= 1 << (((crc) >> 24) & 0x1f); \ 285 } while (/*CONSTCOND*/0) 286 287 static int emac_match(device_t, cfdata_t, void *); 288 static void emac_attach(device_t, device_t, void *); 289 290 static int emac_intr(void *); 291 static void emac_shutdown(void *); 292 293 static void emac_start(struct ifnet *); 294 static int emac_ioctl(struct ifnet *, u_long, void *); 295 static int emac_init(struct ifnet *); 296 static void emac_stop(struct ifnet *, int); 297 static void emac_watchdog(struct ifnet *); 298 299 static int emac_add_rxbuf(struct emac_softc *, int); 300 static void emac_rxdrain(struct emac_softc *); 301 static int emac_set_filter(struct emac_softc *); 302 static int emac_txreap(struct emac_softc *); 303 304 static void emac_soft_reset(struct emac_softc *); 305 static void emac_smart_reset(struct emac_softc *); 306 307 static int emac_mii_readreg(device_t, int, int, uint16_t *); 308 static int emac_mii_writereg(device_t, int, int, uint16_t); 309 static void emac_mii_statchg(struct ifnet *); 310 static uint32_t emac_mii_wait(struct emac_softc *); 311 static void emac_mii_tick(void *); 312 313 int emac_copy_small = 0; 314 315 CFATTACH_DECL_NEW(emac, sizeof(struct emac_softc), 316 emac_match, emac_attach, NULL, NULL); 317 318 319 static int 320 emac_match(device_t parent, cfdata_t cf, void *aux) 321 { 322 struct opb_attach_args *oaa = aux; 323 324 /* match only on-chip ethernet devices */ 325 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 326 return 1; 327 328 return 0; 329 } 330 331 static void 332 emac_attach(device_t parent, device_t self, void *aux) 333 { 334 struct opb_attach_args *oaa = aux; 335 struct emac_softc *sc = device_private(self); 336 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 337 struct mii_data *mii = &sc->sc_mii; 338 const char * xname = device_xname(self); 339 bus_dma_segment_t seg; 340 int error, i, nseg, opb_freq, opbc, mii_phy = MII_PHY_ANY; 341 const uint8_t *enaddr; 342 prop_dictionary_t dict = device_properties(self); 343 prop_data_t ea; 344 345 bus_space_map(oaa->opb_bt, oaa->opb_addr, EMAC_NREG, 0, &sc->sc_sh); 346 347 sc->sc_dev = self; 348 sc->sc_instance = oaa->opb_instance; 349 sc->sc_st = oaa->opb_bt; 350 sc->sc_dmat = oaa->opb_dmat; 351 352 callout_init(&sc->sc_callout, 0); 353 354 aprint_naive("\n"); 355 aprint_normal(": Ethernet Media Access Controller\n"); 356 357 /* Fetch the Ethernet address. */ 358 ea = prop_dictionary_get(dict, "mac-address"); 359 if (ea == NULL) { 360 aprint_error_dev(self, "unable to get mac-address property\n"); 361 return; 362 } 363 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 364 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 365 enaddr = prop_data_data_nocopy(ea); 366 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 367 368 #if defined(EMAC_ZMII_PHY) || defined(EMAC_RGMII_PHY) 369 /* Fetch the MII offset. */ 370 prop_dictionary_get_uint32(dict, "mii-phy", &mii_phy); 371 372 #ifdef EMAC_ZMII_PHY 373 if (oaa->opb_flags & OPB_FLAGS_EMAC_RMII_ZMII) 374 zmii_attach(parent, sc->sc_instance, &sc->sc_rmii_enable, 375 &sc->sc_rmii_disable, &sc->sc_rmii_speed); 376 #endif 377 #ifdef EMAC_RGMII_PHY 378 if (oaa->opb_flags & OPB_FLAGS_EMAC_RMII_RGMII) 379 rgmii_attach(parent, sc->sc_instance, &sc->sc_rmii_enable, 380 &sc->sc_rmii_disable, &sc->sc_rmii_speed); 381 #endif 382 #endif 383 384 /* 385 * Allocate the control data structures, and create and load the 386 * DMA map for it. 387 */ 388 if ((error = bus_dmamem_alloc(sc->sc_dmat, 389 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 390 aprint_error_dev(self, 391 "unable to allocate control data, error = %d\n", error); 392 goto fail_0; 393 } 394 395 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 396 sizeof(struct emac_control_data), (void **)&sc->sc_control_data, 397 BUS_DMA_COHERENT)) != 0) { 398 aprint_error_dev(self, 399 "unable to map control data, error = %d\n", error); 400 goto fail_1; 401 } 402 403 if ((error = bus_dmamap_create(sc->sc_dmat, 404 sizeof(struct emac_control_data), 1, 405 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 406 aprint_error_dev(self, 407 "unable to create control data DMA map, error = %d\n", 408 error); 409 goto fail_2; 410 } 411 412 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 413 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 414 0)) != 0) { 415 aprint_error_dev(self, 416 "unable to load control data DMA map, error = %d\n", error); 417 goto fail_3; 418 } 419 420 /* 421 * Create the transmit buffer DMA maps. 422 */ 423 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 424 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 425 EMAC_NTXSEGS, MCLBYTES, 0, 0, 426 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 427 aprint_error_dev(self, 428 "unable to create tx DMA map %d, error = %d\n", 429 i, error); 430 goto fail_4; 431 } 432 } 433 434 /* 435 * Create the receive buffer DMA maps. 436 */ 437 for (i = 0; i < EMAC_NRXDESC; i++) { 438 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 439 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 440 aprint_error_dev(self, 441 "unable to create rx DMA map %d, error = %d\n", 442 i, error); 443 goto fail_5; 444 } 445 sc->sc_rxsoft[i].rxs_mbuf = NULL; 446 } 447 448 /* Soft Reset the EMAC. The chip to a known state. */ 449 emac_soft_reset(sc); 450 451 opb_freq = opb_get_frequency(); 452 switch (opb_freq) { 453 case 50000000: opbc = STACR_OPBC_50MHZ; break; 454 case 66666666: opbc = STACR_OPBC_66MHZ; break; 455 case 83333333: opbc = STACR_OPBC_83MHZ; break; 456 case 100000000: opbc = STACR_OPBC_100MHZ; break; 457 458 default: 459 if (opb_freq > 100000000) { 460 opbc = STACR_OPBC_A100MHZ; 461 break; 462 } 463 aprint_error_dev(self, "unsupport OPB frequency %dMHz\n", 464 opb_freq / 1000 / 1000); 465 goto fail_5; 466 } 467 if (oaa->opb_flags & OPB_FLAGS_EMAC_GBE) { 468 sc->sc_mr1 = 469 MR1_RFS_GBE(MR1__FS_16KB) | 470 MR1_TFS_GBE(MR1__FS_16KB) | 471 MR1_TR0_MULTIPLE | 472 MR1_OBCI(opbc); 473 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 474 475 if (oaa->opb_flags & OPB_FLAGS_EMAC_STACV2) { 476 sc->sc_stacr_read = STACR_STAOPC_READ; 477 sc->sc_stacr_write = STACR_STAOPC_WRITE; 478 sc->sc_stacr_bits = STACR_OC; 479 sc->sc_stacr_completed = false; 480 } else { 481 sc->sc_stacr_read = STACR_READ; 482 sc->sc_stacr_write = STACR_WRITE; 483 sc->sc_stacr_completed = true; 484 } 485 } else { 486 /* 487 * Set up Mode Register 1 - set receive and transmit FIFOs to 488 * maximum size, allow transmit of multiple packets (only 489 * channel 0 is used). 490 * 491 * XXX: Allow pause packets?? 492 */ 493 sc->sc_mr1 = 494 MR1_RFS(MR1__FS_4KB) | 495 MR1_TFS(MR1__FS_2KB) | 496 MR1_TR0_MULTIPLE; 497 498 sc->sc_stacr_read = STACR_READ; 499 sc->sc_stacr_write = STACR_WRITE; 500 sc->sc_stacr_bits = STACR_OPBC(opbc); 501 sc->sc_stacr_completed = true; 502 } 503 504 intr_establish(oaa->opb_irq, IST_LEVEL, IPL_NET, emac_intr, sc); 505 mal_intr_establish(sc->sc_instance, sc); 506 507 if (oaa->opb_flags & OPB_FLAGS_EMAC_HT256) 508 sc->sc_htsize = 256; 509 else 510 sc->sc_htsize = 64; 511 512 /* Clear all interrupts */ 513 EMAC_WRITE(sc, EMAC_ISR, ISR_ALL); 514 515 /* 516 * Initialise the media structures. 517 */ 518 mii->mii_ifp = ifp; 519 mii->mii_readreg = emac_mii_readreg; 520 mii->mii_writereg = emac_mii_writereg; 521 mii->mii_statchg = emac_mii_statchg; 522 523 sc->sc_ethercom.ec_mii = mii; 524 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 525 mii_attach(self, mii, 0xffffffff, mii_phy, MII_OFFSET_ANY, 526 MIIF_DOPAUSE); 527 if (LIST_FIRST(&mii->mii_phys) == NULL) { 528 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 529 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 530 } else 531 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 532 533 ifp = &sc->sc_ethercom.ec_if; 534 strcpy(ifp->if_xname, xname); 535 ifp->if_softc = sc; 536 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 537 ifp->if_start = emac_start; 538 ifp->if_ioctl = emac_ioctl; 539 ifp->if_init = emac_init; 540 ifp->if_stop = emac_stop; 541 ifp->if_watchdog = emac_watchdog; 542 IFQ_SET_READY(&ifp->if_snd); 543 544 /* 545 * We can support 802.1Q VLAN-sized frames. 546 */ 547 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 548 549 /* 550 * Attach the interface. 551 */ 552 if_attach(ifp); 553 if_deferred_start_init(ifp, NULL); 554 ether_ifattach(ifp, enaddr); 555 556 #ifdef EMAC_EVENT_COUNTERS 557 /* 558 * Attach the event counters. 559 */ 560 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 561 NULL, xname, "txintr"); 562 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 563 NULL, xname, "rxintr"); 564 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 565 NULL, xname, "txde"); 566 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 567 NULL, xname, "rxde"); 568 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 569 NULL, xname, "intr"); 570 571 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 572 NULL, xname, "txreap"); 573 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 574 NULL, xname, "txsstall"); 575 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 576 NULL, xname, "txdstall"); 577 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 578 NULL, xname, "txdrop"); 579 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 580 NULL, xname, "tu"); 581 #endif /* EMAC_EVENT_COUNTERS */ 582 583 /* 584 * Make sure the interface is shutdown during reboot. 585 */ 586 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 587 if (sc->sc_sdhook == NULL) 588 aprint_error_dev(self, 589 "WARNING: unable to establish shutdown hook\n"); 590 591 return; 592 593 /* 594 * Free any resources we've allocated during the failed attach 595 * attempt. Do this in reverse order and fall through. 596 */ 597 fail_5: 598 for (i = 0; i < EMAC_NRXDESC; i++) { 599 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 600 bus_dmamap_destroy(sc->sc_dmat, 601 sc->sc_rxsoft[i].rxs_dmamap); 602 } 603 fail_4: 604 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 605 if (sc->sc_txsoft[i].txs_dmamap != NULL) 606 bus_dmamap_destroy(sc->sc_dmat, 607 sc->sc_txsoft[i].txs_dmamap); 608 } 609 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 610 fail_3: 611 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 612 fail_2: 613 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 614 sizeof(struct emac_control_data)); 615 fail_1: 616 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 617 fail_0: 618 return; 619 } 620 621 /* 622 * EMAC General interrupt handler 623 */ 624 static int 625 emac_intr(void *arg) 626 { 627 struct emac_softc *sc = arg; 628 uint32_t status; 629 630 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 631 status = EMAC_READ(sc, EMAC_ISR); 632 633 /* Clear the interrupt status bits. */ 634 EMAC_WRITE(sc, EMAC_ISR, status); 635 636 return 1; 637 } 638 639 static void 640 emac_shutdown(void *arg) 641 { 642 struct emac_softc *sc = arg; 643 644 emac_stop(&sc->sc_ethercom.ec_if, 0); 645 } 646 647 648 /* 649 * ifnet interface functions 650 */ 651 652 static void 653 emac_start(struct ifnet *ifp) 654 { 655 struct emac_softc *sc = ifp->if_softc; 656 struct mbuf *m0; 657 struct emac_txsoft *txs; 658 bus_dmamap_t dmamap; 659 int error, firsttx, nexttx, lasttx, ofree, seg; 660 661 lasttx = 0; /* XXX gcc */ 662 663 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 664 return; 665 666 /* 667 * Remember the previous number of free descriptors. 668 */ 669 ofree = sc->sc_txfree; 670 671 /* 672 * Loop through the send queue, setting up transmit descriptors 673 * until we drain the queue, or use up all available transmit 674 * descriptors. 675 */ 676 for (;;) { 677 /* Grab a packet off the queue. */ 678 IFQ_POLL(&ifp->if_snd, m0); 679 if (m0 == NULL) 680 break; 681 682 /* 683 * Get a work queue entry. Reclaim used Tx descriptors if 684 * we are running low. 685 */ 686 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 687 emac_txreap(sc); 688 if (sc->sc_txsfree == 0) { 689 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 690 break; 691 } 692 } 693 694 txs = &sc->sc_txsoft[sc->sc_txsnext]; 695 dmamap = txs->txs_dmamap; 696 697 /* 698 * Load the DMA map. If this fails, the packet either 699 * didn't fit in the alloted number of segments, or we 700 * were short on resources. In this case, we'll copy 701 * and try again. 702 */ 703 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 704 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 705 if (error) { 706 if (error == EFBIG) { 707 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 708 aprint_error_ifnet(ifp, 709 "Tx packet consumes too many " 710 "DMA segments, dropping...\n"); 711 IFQ_DEQUEUE(&ifp->if_snd, m0); 712 m_freem(m0); 713 continue; 714 } 715 /* Short on resources, just stop for now. */ 716 break; 717 } 718 719 /* 720 * Ensure we have enough descriptors free to describe 721 * the packet. 722 */ 723 if (dmamap->dm_nsegs > sc->sc_txfree) { 724 /* 725 * Not enough free descriptors to transmit this 726 * packet. We haven't committed anything yet, 727 * so just unload the DMA map, put the packet 728 * back on the queue, and punt. Notify the upper 729 * layer that there are not more slots left. 730 * 731 */ 732 ifp->if_flags |= IFF_OACTIVE; 733 bus_dmamap_unload(sc->sc_dmat, dmamap); 734 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 735 break; 736 } 737 738 IFQ_DEQUEUE(&ifp->if_snd, m0); 739 740 /* 741 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 742 */ 743 744 /* Sync the DMA map. */ 745 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 746 BUS_DMASYNC_PREWRITE); 747 748 /* 749 * Store a pointer to the packet so that we can free it 750 * later. 751 */ 752 txs->txs_mbuf = m0; 753 txs->txs_firstdesc = sc->sc_txnext; 754 txs->txs_ndesc = dmamap->dm_nsegs; 755 756 /* 757 * Initialize the transmit descriptor. 758 */ 759 firsttx = sc->sc_txnext; 760 for (nexttx = sc->sc_txnext, seg = 0; 761 seg < dmamap->dm_nsegs; 762 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 763 struct mal_descriptor *txdesc = 764 &sc->sc_txdescs[nexttx]; 765 766 /* 767 * If this is the first descriptor we're 768 * enqueueing, don't set the TX_READY bit just 769 * yet. That could cause a race condition. 770 * We'll do it below. 771 */ 772 txdesc->md_data = dmamap->dm_segs[seg].ds_addr; 773 txdesc->md_data_len = dmamap->dm_segs[seg].ds_len; 774 txdesc->md_stat_ctrl = 775 (txdesc->md_stat_ctrl & MAL_TX_WRAP) | 776 (nexttx == firsttx ? 0 : MAL_TX_READY) | 777 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 778 lasttx = nexttx; 779 } 780 781 /* Set the LAST bit on the last segment. */ 782 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 783 784 /* 785 * Set up last segment descriptor to send an interrupt after 786 * that descriptor is transmitted, and bypass existing Tx 787 * descriptor reaping method (for now...). 788 */ 789 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_INTERRUPT; 790 791 792 txs->txs_lastdesc = lasttx; 793 794 /* Sync the descriptors we're using. */ 795 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 796 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 797 798 /* 799 * The entire packet chain is set up. Give the 800 * first descriptor to the chip now. 801 */ 802 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 803 EMAC_CDTXSYNC(sc, firsttx, 1, 804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 805 /* 806 * Tell the EMAC that a new packet is available. 807 */ 808 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0 | TMR0_TFAE_2); 809 810 /* Advance the tx pointer. */ 811 sc->sc_txfree -= txs->txs_ndesc; 812 sc->sc_txnext = nexttx; 813 814 sc->sc_txsfree--; 815 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 816 817 /* 818 * Pass the packet to any BPF listeners. 819 */ 820 bpf_mtap(ifp, m0, BPF_D_OUT); 821 } 822 823 if (sc->sc_txfree == 0) 824 /* No more slots left; notify upper layer. */ 825 ifp->if_flags |= IFF_OACTIVE; 826 827 if (sc->sc_txfree != ofree) 828 /* Set a watchdog timer in case the chip flakes out. */ 829 ifp->if_timer = 5; 830 } 831 832 static int 833 emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 834 { 835 struct emac_softc *sc = ifp->if_softc; 836 int s, error; 837 838 s = splnet(); 839 840 switch (cmd) { 841 case SIOCSIFMTU: 842 { 843 struct ifreq *ifr = (struct ifreq *)data; 844 int maxmtu; 845 846 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) 847 maxmtu = EMAC_MAX_MTU; 848 else 849 maxmtu = ETHERMTU; 850 851 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > maxmtu) 852 error = EINVAL; 853 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 854 break; 855 else if (ifp->if_flags & IFF_UP) 856 error = emac_init(ifp); 857 else 858 error = 0; 859 break; 860 } 861 862 default: 863 error = ether_ioctl(ifp, cmd, data); 864 if (error == ENETRESET) { 865 /* 866 * Multicast list has changed; set the hardware filter 867 * accordingly. 868 */ 869 if (ifp->if_flags & IFF_RUNNING) 870 error = emac_set_filter(sc); 871 else 872 error = 0; 873 } 874 } 875 876 /* try to get more packets going */ 877 emac_start(ifp); 878 879 splx(s); 880 return error; 881 } 882 883 static int 884 emac_init(struct ifnet *ifp) 885 { 886 struct emac_softc *sc = ifp->if_softc; 887 struct emac_rxsoft *rxs; 888 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 889 int error, i; 890 891 error = 0; 892 893 /* Cancel any pending I/O. */ 894 emac_stop(ifp, 0); 895 896 /* Reset the chip to a known state. */ 897 emac_soft_reset(sc); 898 899 /* 900 * Initialise the transmit descriptor ring. 901 */ 902 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 903 /* set wrap on last descriptor */ 904 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 905 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 907 sc->sc_txfree = EMAC_NTXDESC; 908 sc->sc_txnext = 0; 909 910 /* 911 * Initialise the transmit job descriptors. 912 */ 913 for (i = 0; i < EMAC_TXQUEUELEN; i++) 914 sc->sc_txsoft[i].txs_mbuf = NULL; 915 sc->sc_txsfree = EMAC_TXQUEUELEN; 916 sc->sc_txsnext = 0; 917 sc->sc_txsdirty = 0; 918 919 /* 920 * Initialise the receiver descriptor and receive job 921 * descriptor rings. 922 */ 923 for (i = 0; i < EMAC_NRXDESC; i++) { 924 rxs = &sc->sc_rxsoft[i]; 925 if (rxs->rxs_mbuf == NULL) { 926 if ((error = emac_add_rxbuf(sc, i)) != 0) { 927 aprint_error_ifnet(ifp, 928 "unable to allocate or map rx buffer %d," 929 " error = %d\n", 930 i, error); 931 /* 932 * XXX Should attempt to run with fewer receive 933 * XXX buffers instead of just failing. 934 */ 935 emac_rxdrain(sc); 936 goto out; 937 } 938 } else 939 EMAC_INIT_RXDESC(sc, i); 940 } 941 sc->sc_rxptr = 0; 942 943 /* 944 * Set the current media. 945 */ 946 if ((error = ether_mediachange(ifp)) != 0) 947 goto out; 948 949 /* 950 * Load the MAC address. 951 */ 952 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 953 EMAC_WRITE(sc, EMAC_IALR, 954 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 955 956 /* Enable the transmit and receive channel on the MAL. */ 957 error = mal_start(sc->sc_instance, 958 EMAC_CDTXADDR(sc, 0), EMAC_CDRXADDR(sc, 0)); 959 if (error) 960 goto out; 961 962 sc->sc_mr1 &= ~MR1_JPSM; 963 if (ifp->if_mtu > ETHERMTU) 964 /* Enable Jumbo Packet Support Mode */ 965 sc->sc_mr1 |= MR1_JPSM; 966 967 /* Set fifos, media modes. */ 968 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 969 970 /* 971 * Enable Individual and (possibly) Broadcast Address modes, 972 * runt packets, and strip padding. 973 */ 974 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | RMR_TFAE_2 | 975 (ifp->if_flags & IFF_PROMISC ? RMR_PME : 0) | 976 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 977 978 /* 979 * Set multicast filter. 980 */ 981 emac_set_filter(sc); 982 983 /* 984 * Set low- and urgent-priority request thresholds. 985 */ 986 EMAC_WRITE(sc, EMAC_TMR1, 987 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 988 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 989 /* 990 * Set Transmit Request Threshold Register. 991 */ 992 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 993 994 /* 995 * Set high and low receive watermarks. 996 */ 997 EMAC_WRITE(sc, EMAC_RWMR, 998 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 999 1000 /* 1001 * Set frame gap. 1002 */ 1003 EMAC_WRITE(sc, EMAC_IPGVR, 8); 1004 1005 /* 1006 * Set interrupt status enable bits for EMAC. 1007 */ 1008 EMAC_WRITE(sc, EMAC_ISER, 1009 ISR_TXPE | /* TX Parity Error */ 1010 ISR_RXPE | /* RX Parity Error */ 1011 ISR_TXUE | /* TX Underrun Event */ 1012 ISR_RXOE | /* RX Overrun Event */ 1013 ISR_OVR | /* Overrun Error */ 1014 ISR_PP | /* Pause Packet */ 1015 ISR_BP | /* Bad Packet */ 1016 ISR_RP | /* Runt Packet */ 1017 ISR_SE | /* Short Event */ 1018 ISR_ALE | /* Alignment Error */ 1019 ISR_BFCS | /* Bad FCS */ 1020 ISR_PTLE | /* Packet Too Long Error */ 1021 ISR_ORE | /* Out of Range Error */ 1022 ISR_IRE | /* In Range Error */ 1023 ISR_SE0 | /* Signal Quality Error 0 (SQE) */ 1024 ISR_TE0 | /* Transmit Error 0 */ 1025 ISR_MOS | /* MMA Operation Succeeded */ 1026 ISR_MOF); /* MMA Operation Failed */ 1027 1028 /* 1029 * Enable the transmit and receive channel on the EMAC. 1030 */ 1031 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 1032 1033 /* 1034 * Start the one second MII clock. 1035 */ 1036 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1037 1038 /* 1039 * ... all done! 1040 */ 1041 ifp->if_flags |= IFF_RUNNING; 1042 ifp->if_flags &= ~IFF_OACTIVE; 1043 1044 out: 1045 if (error) { 1046 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1047 ifp->if_timer = 0; 1048 aprint_error_ifnet(ifp, "interface not running\n"); 1049 } 1050 return error; 1051 } 1052 1053 static void 1054 emac_stop(struct ifnet *ifp, int disable) 1055 { 1056 struct emac_softc *sc = ifp->if_softc; 1057 struct emac_txsoft *txs; 1058 int i; 1059 1060 /* Stop the one second clock. */ 1061 callout_stop(&sc->sc_callout); 1062 1063 /* Down the MII */ 1064 mii_down(&sc->sc_mii); 1065 1066 /* Disable interrupts. */ 1067 EMAC_WRITE(sc, EMAC_ISER, 0); 1068 1069 /* Disable the receive and transmit channels. */ 1070 mal_stop(sc->sc_instance); 1071 1072 /* Disable the transmit enable and receive MACs. */ 1073 EMAC_WRITE(sc, EMAC_MR0, 1074 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 1075 1076 /* Release any queued transmit buffers. */ 1077 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 1078 txs = &sc->sc_txsoft[i]; 1079 if (txs->txs_mbuf != NULL) { 1080 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1081 m_freem(txs->txs_mbuf); 1082 txs->txs_mbuf = NULL; 1083 } 1084 } 1085 1086 if (disable) 1087 emac_rxdrain(sc); 1088 1089 /* 1090 * Mark the interface down and cancel the watchdog timer. 1091 */ 1092 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1093 ifp->if_timer = 0; 1094 } 1095 1096 static void 1097 emac_watchdog(struct ifnet *ifp) 1098 { 1099 struct emac_softc *sc = ifp->if_softc; 1100 1101 /* 1102 * Since we're not interrupting every packet, sweep 1103 * up before we report an error. 1104 */ 1105 emac_txreap(sc); 1106 1107 if (sc->sc_txfree != EMAC_NTXDESC) { 1108 aprint_error_ifnet(ifp, 1109 "device timeout (txfree %d txsfree %d txnext %d)\n", 1110 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1111 ifp->if_oerrors++; 1112 1113 /* Reset the interface. */ 1114 (void)emac_init(ifp); 1115 } else if (ifp->if_flags & IFF_DEBUG) 1116 aprint_error_ifnet(ifp, "recovered from device timeout\n"); 1117 1118 /* try to get more packets going */ 1119 emac_start(ifp); 1120 } 1121 1122 static int 1123 emac_add_rxbuf(struct emac_softc *sc, int idx) 1124 { 1125 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1126 struct mbuf *m; 1127 int error; 1128 1129 MGETHDR(m, M_DONTWAIT, MT_DATA); 1130 if (m == NULL) 1131 return ENOBUFS; 1132 1133 MCLGET(m, M_DONTWAIT); 1134 if ((m->m_flags & M_EXT) == 0) { 1135 m_freem(m); 1136 return ENOBUFS; 1137 } 1138 1139 if (rxs->rxs_mbuf != NULL) 1140 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1141 1142 rxs->rxs_mbuf = m; 1143 1144 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1145 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1146 if (error) { 1147 aprint_error_dev(sc->sc_dev, 1148 "can't load rx DMA map %d, error = %d\n", idx, error); 1149 panic("emac_add_rxbuf"); /* XXX */ 1150 } 1151 1152 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1153 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1154 1155 EMAC_INIT_RXDESC(sc, idx); 1156 1157 return 0; 1158 } 1159 1160 static void 1161 emac_rxdrain(struct emac_softc *sc) 1162 { 1163 struct emac_rxsoft *rxs; 1164 int i; 1165 1166 for (i = 0; i < EMAC_NRXDESC; i++) { 1167 rxs = &sc->sc_rxsoft[i]; 1168 if (rxs->rxs_mbuf != NULL) { 1169 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1170 m_freem(rxs->rxs_mbuf); 1171 rxs->rxs_mbuf = NULL; 1172 } 1173 } 1174 } 1175 1176 static int 1177 emac_set_filter(struct emac_softc *sc) 1178 { 1179 struct ethercom *ec = &sc->sc_ethercom; 1180 struct ether_multistep step; 1181 struct ether_multi *enm; 1182 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1183 uint32_t rmr, crc, mask, tmp, reg, gaht[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1184 int regs, cnt = 0, i; 1185 1186 if (sc->sc_htsize == 256) { 1187 reg = EMAC_GAHT256(0); 1188 regs = 8; 1189 } else { 1190 reg = EMAC_GAHT64(0); 1191 regs = 4; 1192 } 1193 mask = (1ULL << (sc->sc_htsize / regs)) - 1; 1194 1195 rmr = EMAC_READ(sc, EMAC_RMR); 1196 rmr &= ~(RMR_PMME | RMR_MAE); 1197 ifp->if_flags &= ~IFF_ALLMULTI; 1198 1199 ETHER_LOCK(ec); 1200 ETHER_FIRST_MULTI(step, ec, enm); 1201 while (enm != NULL) { 1202 if (memcmp(enm->enm_addrlo, 1203 enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1204 /* 1205 * We must listen to a range of multicast addresses. 1206 * For now, just accept all multicasts, rather than 1207 * trying to set only those filter bits needed to match 1208 * the range. (At this time, the only use of address 1209 * ranges is for IP multicast routing, for which the 1210 * range is big enough to require all bits set.) 1211 */ 1212 gaht[0] = gaht[1] = gaht[2] = gaht[3] = 1213 gaht[4] = gaht[5] = gaht[6] = gaht[7] = mask; 1214 break; 1215 } 1216 1217 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1218 1219 if (sc->sc_htsize == 256) 1220 EMAC_SET_FILTER256(gaht, crc); 1221 else 1222 EMAC_SET_FILTER(gaht, crc); 1223 1224 ETHER_NEXT_MULTI(step, enm); 1225 cnt++; 1226 } 1227 ETHER_UNLOCK(ec); 1228 1229 for (i = 1, tmp = gaht[0]; i < regs; i++) 1230 tmp &= gaht[i]; 1231 if (tmp == mask) { 1232 /* All categories are true. */ 1233 ifp->if_flags |= IFF_ALLMULTI; 1234 rmr |= RMR_PMME; 1235 } else if (cnt != 0) { 1236 /* Some categories are true. */ 1237 for (i = 0; i < regs; i++) 1238 EMAC_WRITE(sc, reg + (i << 2), gaht[i]); 1239 rmr |= RMR_MAE; 1240 } 1241 EMAC_WRITE(sc, EMAC_RMR, rmr); 1242 1243 return 0; 1244 } 1245 1246 /* 1247 * Reap completed Tx descriptors. 1248 */ 1249 static int 1250 emac_txreap(struct emac_softc *sc) 1251 { 1252 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1253 struct emac_txsoft *txs; 1254 int handled, i; 1255 uint32_t txstat; 1256 1257 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1258 handled = 0; 1259 1260 ifp->if_flags &= ~IFF_OACTIVE; 1261 1262 /* 1263 * Go through our Tx list and free mbufs for those 1264 * frames that have been transmitted. 1265 */ 1266 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1267 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1268 txs = &sc->sc_txsoft[i]; 1269 1270 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1271 txs->txs_dmamap->dm_nsegs, 1272 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1273 1274 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1275 if (txstat & MAL_TX_READY) 1276 break; 1277 1278 handled = 1; 1279 1280 /* 1281 * Check for errors and collisions. 1282 */ 1283 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1284 ifp->if_oerrors++; 1285 1286 #ifdef EMAC_EVENT_COUNTERS 1287 if (txstat & EMAC_TXS_UR) 1288 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1289 #endif /* EMAC_EVENT_COUNTERS */ 1290 1291 if (txstat & 1292 (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1293 if (txstat & EMAC_TXS_EC) 1294 ifp->if_collisions += 16; 1295 else if (txstat & EMAC_TXS_MC) 1296 ifp->if_collisions += 2; /* XXX? */ 1297 else if (txstat & EMAC_TXS_SC) 1298 ifp->if_collisions++; 1299 if (txstat & EMAC_TXS_LC) 1300 ifp->if_collisions++; 1301 } else 1302 ifp->if_opackets++; 1303 1304 if (ifp->if_flags & IFF_DEBUG) { 1305 if (txstat & EMAC_TXS_ED) 1306 aprint_error_ifnet(ifp, "excessive deferral\n"); 1307 if (txstat & EMAC_TXS_EC) 1308 aprint_error_ifnet(ifp, 1309 "excessive collisions\n"); 1310 } 1311 1312 sc->sc_txfree += txs->txs_ndesc; 1313 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1314 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1315 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1316 m_freem(txs->txs_mbuf); 1317 txs->txs_mbuf = NULL; 1318 } 1319 1320 /* Update the dirty transmit buffer pointer. */ 1321 sc->sc_txsdirty = i; 1322 1323 /* 1324 * If there are no more pending transmissions, cancel the watchdog 1325 * timer. 1326 */ 1327 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1328 ifp->if_timer = 0; 1329 1330 return handled; 1331 } 1332 1333 1334 /* 1335 * Reset functions 1336 */ 1337 1338 static void 1339 emac_soft_reset(struct emac_softc *sc) 1340 { 1341 uint32_t sdr; 1342 int t = 0; 1343 1344 /* 1345 * The PHY must provide a TX Clk in order perform a soft reset the 1346 * EMAC. If none is present, select the internal clock, 1347 * SDR0_MFR[E0CS, E1CS]. After the soft reset, select the external 1348 * clock. 1349 */ 1350 1351 sdr = mfsdr(DCR_SDR0_MFR); 1352 sdr |= SDR0_MFR_ECS(sc->sc_instance); 1353 mtsdr(DCR_SDR0_MFR, sdr); 1354 1355 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1356 1357 sdr = mfsdr(DCR_SDR0_MFR); 1358 sdr &= ~SDR0_MFR_ECS(sc->sc_instance); 1359 mtsdr(DCR_SDR0_MFR, sdr); 1360 1361 delay(5); 1362 1363 /* wait finish */ 1364 while (EMAC_READ(sc, EMAC_MR0) & MR0_SRST) { 1365 if (++t == 1000000 /* 1sec XXXXX */) { 1366 aprint_error_dev(sc->sc_dev, "Soft Reset failed\n"); 1367 return; 1368 } 1369 delay(1); 1370 } 1371 } 1372 1373 static void 1374 emac_smart_reset(struct emac_softc *sc) 1375 { 1376 uint32_t mr0; 1377 int t = 0; 1378 1379 mr0 = EMAC_READ(sc, EMAC_MR0); 1380 if (mr0 & (MR0_TXE | MR0_RXE)) { 1381 mr0 &= ~(MR0_TXE | MR0_RXE); 1382 EMAC_WRITE(sc, EMAC_MR0, mr0); 1383 1384 /* wait idel state */ 1385 while ((EMAC_READ(sc, EMAC_MR0) & (MR0_TXI | MR0_RXI)) != 1386 (MR0_TXI | MR0_RXI)) { 1387 if (++t == 1000000 /* 1sec XXXXX */) { 1388 aprint_error_dev(sc->sc_dev, 1389 "Smart Reset failed\n"); 1390 return; 1391 } 1392 delay(1); 1393 } 1394 } 1395 } 1396 1397 1398 /* 1399 * MII related functions 1400 */ 1401 1402 static int 1403 emac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1404 { 1405 struct emac_softc *sc = device_private(self); 1406 uint32_t sta_reg; 1407 int rv; 1408 1409 if (sc->sc_rmii_enable) 1410 sc->sc_rmii_enable(device_parent(self), sc->sc_instance); 1411 1412 /* wait for PHY data transfer to complete */ 1413 if ((rv = emac_mii_wait(sc)) != 0) 1414 goto fail; 1415 1416 sta_reg = 1417 sc->sc_stacr_read | 1418 (reg << STACR_PRA_SHIFT) | 1419 (phy << STACR_PCDA_SHIFT) | 1420 sc->sc_stacr_bits; 1421 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1422 1423 if ((rv = emac_mii_wait(sc)) != 0) 1424 goto fail; 1425 sta_reg = EMAC_READ(sc, EMAC_STACR); 1426 1427 if (sta_reg & STACR_PHYE) { 1428 rv = -1; 1429 goto fail; 1430 } 1431 *val = sta_reg >> STACR_PHYD_SHIFT; 1432 1433 fail: 1434 if (sc->sc_rmii_disable) 1435 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 1436 return rv; 1437 } 1438 1439 static int 1440 emac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1441 { 1442 struct emac_softc *sc = device_private(self); 1443 uint32_t sta_reg; 1444 int rv; 1445 1446 if (sc->sc_rmii_enable) 1447 sc->sc_rmii_enable(device_parent(self), sc->sc_instance); 1448 1449 /* wait for PHY data transfer to complete */ 1450 if ((rv = emac_mii_wait(sc)) != 0) 1451 goto out; 1452 1453 sta_reg = 1454 (val << STACR_PHYD_SHIFT) | 1455 sc->sc_stacr_write | 1456 (reg << STACR_PRA_SHIFT) | 1457 (phy << STACR_PCDA_SHIFT) | 1458 sc->sc_stacr_bits; 1459 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1460 1461 if ((rv = emac_mii_wait(sc)) != 0) 1462 goto out; 1463 if (EMAC_READ(sc, EMAC_STACR) & STACR_PHYE) { 1464 aprint_error_dev(sc->sc_dev, "MII PHY Error\n"); 1465 rv = -1; 1466 } 1467 1468 out: 1469 if (sc->sc_rmii_disable) 1470 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 1471 1472 return rv; 1473 } 1474 1475 static void 1476 emac_mii_statchg(struct ifnet *ifp) 1477 { 1478 struct emac_softc *sc = ifp->if_softc; 1479 struct mii_data *mii = &sc->sc_mii; 1480 1481 /* 1482 * MR1 can only be written immediately after a reset... 1483 */ 1484 emac_smart_reset(sc); 1485 1486 sc->sc_mr1 &= ~(MR1_FDE | MR1_ILE | MR1_EIFC | MR1_MF_MASK | MR1_IST); 1487 if (mii->mii_media_active & IFM_FDX) 1488 sc->sc_mr1 |= (MR1_FDE | MR1_EIFC | MR1_IST); 1489 if (mii->mii_media_active & IFM_FLOW) 1490 sc->sc_mr1 |= MR1_EIFC; 1491 if (mii->mii_media_active & IFM_LOOP) 1492 sc->sc_mr1 |= MR1_ILE; 1493 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1494 case IFM_1000_T: 1495 sc->sc_mr1 |= (MR1_MF_1000MBS | MR1_IST); 1496 break; 1497 1498 case IFM_100_TX: 1499 sc->sc_mr1 |= (MR1_MF_100MBS | MR1_IST); 1500 break; 1501 1502 case IFM_10_T: 1503 sc->sc_mr1 |= MR1_MF_10MBS; 1504 break; 1505 1506 case IFM_NONE: 1507 break; 1508 1509 default: 1510 aprint_error_dev(sc->sc_dev, "unknown sub-type %d\n", 1511 IFM_SUBTYPE(mii->mii_media_active)); 1512 break; 1513 } 1514 if (sc->sc_rmii_speed) 1515 sc->sc_rmii_speed(device_parent(sc->sc_dev), sc->sc_instance, 1516 IFM_SUBTYPE(mii->mii_media_active)); 1517 1518 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 1519 1520 /* Enable TX and RX if already RUNNING */ 1521 if (ifp->if_flags & IFF_RUNNING) 1522 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 1523 } 1524 1525 static uint32_t 1526 emac_mii_wait(struct emac_softc *sc) 1527 { 1528 int i; 1529 uint32_t oc; 1530 1531 /* wait for PHY data transfer to complete */ 1532 i = 0; 1533 oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC; 1534 while ((oc == STACR_OC) != sc->sc_stacr_completed) { 1535 delay(7); 1536 if (i++ > 5) { 1537 aprint_error_dev(sc->sc_dev, "MII timed out\n"); 1538 return ETIMEDOUT; 1539 } 1540 oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC; 1541 } 1542 return 0; 1543 } 1544 1545 static void 1546 emac_mii_tick(void *arg) 1547 { 1548 struct emac_softc *sc = arg; 1549 int s; 1550 1551 if (!device_is_active(sc->sc_dev)) 1552 return; 1553 1554 s = splnet(); 1555 mii_tick(&sc->sc_mii); 1556 splx(s); 1557 1558 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1559 } 1560 1561 int 1562 emac_txeob_intr(void *arg) 1563 { 1564 struct emac_softc *sc = arg; 1565 int handled = 0; 1566 1567 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1568 handled |= emac_txreap(sc); 1569 1570 /* try to get more packets going */ 1571 if_schedule_deferred_start(&sc->sc_ethercom.ec_if); 1572 1573 return handled; 1574 } 1575 1576 int 1577 emac_rxeob_intr(void *arg) 1578 { 1579 struct emac_softc *sc = arg; 1580 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1581 struct emac_rxsoft *rxs; 1582 struct mbuf *m; 1583 uint32_t rxstat; 1584 int i, len; 1585 1586 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1587 1588 for (i = sc->sc_rxptr; ; i = EMAC_NEXTRX(i)) { 1589 rxs = &sc->sc_rxsoft[i]; 1590 1591 EMAC_CDRXSYNC(sc, i, 1592 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1593 1594 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1595 1596 if (rxstat & MAL_RX_EMPTY) { 1597 /* 1598 * We have processed all of the receive buffers. 1599 */ 1600 /* Flush current empty descriptor */ 1601 EMAC_CDRXSYNC(sc, i, 1602 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1603 break; 1604 } 1605 1606 /* 1607 * If an error occurred, update stats, clear the status 1608 * word, and leave the packet buffer in place. It will 1609 * simply be reused the next time the ring comes around. 1610 */ 1611 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1612 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1613 EMAC_RXS_IRE)) { 1614 #define PRINTERR(bit, str) \ 1615 if (rxstat & (bit)) \ 1616 aprint_error_ifnet(ifp, \ 1617 "receive error: %s\n", str) 1618 ifp->if_ierrors++; 1619 PRINTERR(EMAC_RXS_OE, "overrun error"); 1620 PRINTERR(EMAC_RXS_BP, "bad packet"); 1621 PRINTERR(EMAC_RXS_RP, "runt packet"); 1622 PRINTERR(EMAC_RXS_SE, "short event"); 1623 PRINTERR(EMAC_RXS_AE, "alignment error"); 1624 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1625 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1626 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1627 PRINTERR(EMAC_RXS_IRE, "in range error"); 1628 #undef PRINTERR 1629 EMAC_INIT_RXDESC(sc, i); 1630 continue; 1631 } 1632 1633 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1634 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1635 1636 /* 1637 * No errors; receive the packet. Note, the 405GP emac 1638 * includes the CRC with every packet. 1639 */ 1640 len = sc->sc_rxdescs[i].md_data_len - ETHER_CRC_LEN; 1641 1642 /* 1643 * If the packet is small enough to fit in a 1644 * single header mbuf, allocate one and copy 1645 * the data into it. This greatly reduces 1646 * memory consumption when we receive lots 1647 * of small packets. 1648 * 1649 * Otherwise, we add a new buffer to the receive 1650 * chain. If this fails, we drop the packet and 1651 * recycle the old buffer. 1652 */ 1653 if (emac_copy_small != 0 && len <= MHLEN) { 1654 MGETHDR(m, M_DONTWAIT, MT_DATA); 1655 if (m == NULL) 1656 goto dropit; 1657 memcpy(mtod(m, void *), 1658 mtod(rxs->rxs_mbuf, void *), len); 1659 EMAC_INIT_RXDESC(sc, i); 1660 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1661 rxs->rxs_dmamap->dm_mapsize, 1662 BUS_DMASYNC_PREREAD); 1663 } else { 1664 m = rxs->rxs_mbuf; 1665 if (emac_add_rxbuf(sc, i) != 0) { 1666 dropit: 1667 ifp->if_ierrors++; 1668 EMAC_INIT_RXDESC(sc, i); 1669 bus_dmamap_sync(sc->sc_dmat, 1670 rxs->rxs_dmamap, 0, 1671 rxs->rxs_dmamap->dm_mapsize, 1672 BUS_DMASYNC_PREREAD); 1673 continue; 1674 } 1675 } 1676 1677 m_set_rcvif(m, ifp); 1678 m->m_pkthdr.len = m->m_len = len; 1679 1680 /* Pass it on. */ 1681 if_percpuq_enqueue(ifp->if_percpuq, m); 1682 } 1683 1684 /* Update the receive pointer. */ 1685 sc->sc_rxptr = i; 1686 1687 return 1; 1688 } 1689 1690 int 1691 emac_txde_intr(void *arg) 1692 { 1693 struct emac_softc *sc = arg; 1694 1695 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1696 aprint_error_dev(sc->sc_dev, "emac_txde_intr\n"); 1697 return 1; 1698 } 1699 1700 int 1701 emac_rxde_intr(void *arg) 1702 { 1703 struct emac_softc *sc = arg; 1704 int i; 1705 1706 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1707 aprint_error_dev(sc->sc_dev, "emac_rxde_intr\n"); 1708 /* 1709 * XXX! 1710 * This is a bit drastic; we just drop all descriptors that aren't 1711 * "clean". We should probably send any that are up the stack. 1712 */ 1713 for (i = 0; i < EMAC_NRXDESC; i++) { 1714 EMAC_CDRXSYNC(sc, i, 1715 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1716 1717 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) 1718 EMAC_INIT_RXDESC(sc, i); 1719 } 1720 1721 return 1; 1722 } 1723