1 /* $NetBSD: if_emac.c,v 1.19 2004/10/30 18:08:35 thorpej Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.19 2004/10/30 18:08:35 thorpej Exp $"); 40 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 50 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #if NBPFILTER > 0 58 #include <net/bpf.h> 59 #endif 60 61 #include <powerpc/ibm4xx/dev/opbvar.h> 62 63 #include <powerpc/ibm4xx/ibm405gp.h> 64 #include <powerpc/ibm4xx/mal405gp.h> 65 #include <powerpc/ibm4xx/dcr405gp.h> 66 #include <powerpc/ibm4xx/dev/emacreg.h> 67 #include <powerpc/ibm4xx/dev/if_emacreg.h> 68 69 #include <dev/mii/miivar.h> 70 71 /* 72 * Transmit descriptor list size. There are two Tx channels, each with 73 * up to 256 hardware descriptors available. We currently use one Tx 74 * channel. We tell the upper layers that they can queue a lot of 75 * packets, and we go ahead and manage up to 64 of them at a time. We 76 * allow up to 16 DMA segments per packet. 77 */ 78 #define EMAC_NTXSEGS 16 79 #define EMAC_TXQUEUELEN 64 80 #define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 81 #define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 82 #define EMAC_NTXDESC 256 83 #define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 84 #define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 85 #define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 86 87 /* 88 * Receive descriptor list size. There is one Rx channel with up to 256 89 * hardware descriptors available. We allocate 64 receive descriptors, 90 * each with a 2k buffer (MCLBYTES). 91 */ 92 #define EMAC_NRXDESC 64 93 #define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 94 #define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 95 #define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 96 97 /* 98 * Transmit/receive descriptors that are DMA'd to the EMAC. 99 */ 100 struct emac_control_data { 101 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 102 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 103 }; 104 105 #define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 106 #define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 107 #define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 108 109 /* 110 * Software state for transmit jobs. 111 */ 112 struct emac_txsoft { 113 struct mbuf *txs_mbuf; /* head of mbuf chain */ 114 bus_dmamap_t txs_dmamap; /* our DMA map */ 115 int txs_firstdesc; /* first descriptor in packet */ 116 int txs_lastdesc; /* last descriptor in packet */ 117 int txs_ndesc; /* # of descriptors used */ 118 }; 119 120 /* 121 * Software state for receive descriptors. 122 */ 123 struct emac_rxsoft { 124 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 125 bus_dmamap_t rxs_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct emac_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 void *sc_powerhook; /* power management hook */ 139 140 struct mii_data sc_mii; /* MII/media information */ 141 struct callout sc_callout; /* tick callout */ 142 143 u_int32_t sc_mr1; /* copy of Mode Register 1 */ 144 145 bus_dmamap_t sc_cddmamap; /* control data dma map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* Software state for transmit/receive descriptors. */ 149 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 150 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 151 152 /* Control data structures. */ 153 struct emac_control_data *sc_control_data; 154 #define sc_txdescs sc_control_data->ecd_txdesc 155 #define sc_rxdescs sc_control_data->ecd_rxdesc 156 157 #ifdef EMAC_EVENT_COUNTERS 158 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 159 struct evcnt sc_ev_txintr; /* Tx interrupts */ 160 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 161 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 162 struct evcnt sc_ev_wol; /* Wake-On-Lan interrupts */ 163 struct evcnt sc_ev_serr; /* MAL system error interrupts */ 164 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 165 166 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 167 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 168 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 169 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 170 struct evcnt sc_ev_tu; /* Tx underrun */ 171 #endif /* EMAC_EVENT_COUNTERS */ 172 173 int sc_txfree; /* number of free Tx descriptors */ 174 int sc_txnext; /* next ready Tx descriptor */ 175 176 int sc_txsfree; /* number of free Tx jobs */ 177 int sc_txsnext; /* next ready Tx job */ 178 int sc_txsdirty; /* dirty Tx jobs */ 179 180 int sc_rxptr; /* next ready RX descriptor/descsoft */ 181 }; 182 183 #ifdef EMAC_EVENT_COUNTERS 184 #define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 185 #else 186 #define EMAC_EVCNT_INCR(ev) /* nothing */ 187 #endif 188 189 #define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 190 #define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 191 192 #define EMAC_CDTXSYNC(sc, x, n, ops) \ 193 do { \ 194 int __x, __n; \ 195 \ 196 __x = (x); \ 197 __n = (n); \ 198 \ 199 /* If it will wrap around, sync to the end of the ring. */ \ 200 if ((__x + __n) > EMAC_NTXDESC) { \ 201 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 202 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 203 (EMAC_NTXDESC - __x), (ops)); \ 204 __n -= (EMAC_NTXDESC - __x); \ 205 __x = 0; \ 206 } \ 207 \ 208 /* Now sync whatever is left. */ \ 209 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 210 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 211 } while (/*CONSTCOND*/0) 212 213 #define EMAC_CDRXSYNC(sc, x, ops) \ 214 do { \ 215 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 216 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 217 } while (/*CONSTCOND*/0) 218 219 #define EMAC_INIT_RXDESC(sc, x) \ 220 do { \ 221 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 222 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 223 struct mbuf *__m = __rxs->rxs_mbuf; \ 224 \ 225 /* \ 226 * Note: We scoot the packet forward 2 bytes in the buffer \ 227 * so that the payload after the Ethernet header is aligned \ 228 * to a 4-byte boundary. \ 229 */ \ 230 __m->m_data = __m->m_ext.ext_buf + 2; \ 231 \ 232 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 233 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 234 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 235 /* Set wrap on last descriptor. */ \ 236 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 237 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 238 } while (/*CONSTCOND*/0) 239 240 #define EMAC_WRITE(sc, reg, val) \ 241 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 242 #define EMAC_READ(sc, reg) \ 243 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 244 245 #define EMAC_SET_FILTER(aht, category) \ 246 do { \ 247 (aht)[3 - ((category) >> 4)] |= 1 << ((category) & 0xf); \ 248 } while (/*CONSTCOND*/0) 249 250 static int emac_match(struct device *, struct cfdata *, void *); 251 static void emac_attach(struct device *, struct device *, void *); 252 253 static int emac_add_rxbuf(struct emac_softc *, int); 254 static int emac_init(struct ifnet *); 255 static int emac_ioctl(struct ifnet *, u_long, caddr_t); 256 static void emac_reset(struct emac_softc *); 257 static void emac_rxdrain(struct emac_softc *); 258 static int emac_txreap(struct emac_softc *); 259 static void emac_shutdown(void *); 260 static void emac_start(struct ifnet *); 261 static void emac_stop(struct ifnet *, int); 262 static void emac_watchdog(struct ifnet *); 263 static int emac_set_filter(struct emac_softc *); 264 265 static int emac_wol_intr(void *); 266 static int emac_serr_intr(void *); 267 static int emac_txeob_intr(void *); 268 static int emac_rxeob_intr(void *); 269 static int emac_txde_intr(void *); 270 static int emac_rxde_intr(void *); 271 static int emac_intr(void *); 272 273 static int emac_mediachange(struct ifnet *); 274 static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 275 static int emac_mii_readreg(struct device *, int, int); 276 static void emac_mii_statchg(struct device *); 277 static void emac_mii_tick(void *); 278 static uint32_t emac_mii_wait(struct emac_softc *); 279 static void emac_mii_writereg(struct device *, int, int, int); 280 281 int emac_copy_small = 0; 282 283 CFATTACH_DECL(emac, sizeof(struct emac_softc), 284 emac_match, emac_attach, NULL, NULL); 285 286 static int 287 emac_match(struct device *parent, struct cfdata *cf, void *aux) 288 { 289 struct opb_attach_args *oaa = aux; 290 291 /* match only on-chip ethernet devices */ 292 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 293 return (1); 294 295 return (0); 296 } 297 298 static void 299 emac_attach(struct device *parent, struct device *self, void *aux) 300 { 301 struct opb_attach_args *oaa = aux; 302 struct emac_softc *sc = (struct emac_softc *)self; 303 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 304 struct mii_data *mii = &sc->sc_mii; 305 bus_dma_segment_t seg; 306 int error, i, nseg; 307 uint8_t enaddr[ETHER_ADDR_LEN]; 308 309 sc->sc_st = oaa->opb_bt; 310 sc->sc_sh = oaa->opb_addr; 311 sc->sc_dmat = oaa->opb_dmat; 312 313 printf(": 405GP EMAC\n"); 314 315 /* 316 * Set up Mode Register 1 - set receive and transmit FIFOs to maximum 317 * size, allow transmit of multiple packets (only channel 0 is used). 318 * 319 * XXX: Allow pause packets?? 320 */ 321 sc->sc_mr1 = MR1_RFS_4KB | MR1_TFS_2KB | MR1_TR0_MULTIPLE; 322 323 intr_establish(oaa->opb_irq , IST_LEVEL, IPL_NET, emac_wol_intr, sc); 324 intr_establish(oaa->opb_irq + 1, IST_LEVEL, IPL_NET, emac_serr_intr, sc); 325 intr_establish(oaa->opb_irq + 2, IST_LEVEL, IPL_NET, emac_txeob_intr, sc); 326 intr_establish(oaa->opb_irq + 3, IST_LEVEL, IPL_NET, emac_rxeob_intr, sc); 327 intr_establish(oaa->opb_irq + 4, IST_LEVEL, IPL_NET, emac_txde_intr, sc); 328 intr_establish(oaa->opb_irq + 5, IST_LEVEL, IPL_NET, emac_rxde_intr, sc); 329 intr_establish(oaa->opb_irq + 6, IST_LEVEL, IPL_NET, emac_intr, sc); 330 printf("%s: interrupting at irqs %d .. %d\n", sc->sc_dev.dv_xname, 331 oaa->opb_irq, oaa->opb_irq + 6); 332 333 /* 334 * Allocate the control data structures, and create and load the 335 * DMA map for it. 336 */ 337 if ((error = bus_dmamem_alloc(sc->sc_dmat, 338 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 339 printf("%s: unable to allocate control data, error = %d\n", 340 sc->sc_dev.dv_xname, error); 341 goto fail_0; 342 } 343 344 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 345 sizeof(struct emac_control_data), (caddr_t *)&sc->sc_control_data, 346 BUS_DMA_COHERENT)) != 0) { 347 printf("%s: unable to map control data, error = %d\n", 348 sc->sc_dev.dv_xname, error); 349 goto fail_1; 350 } 351 352 if ((error = bus_dmamap_create(sc->sc_dmat, 353 sizeof(struct emac_control_data), 1, 354 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 355 printf("%s: unable to create control data DMA map, " 356 "error = %d\n", sc->sc_dev.dv_xname, error); 357 goto fail_2; 358 } 359 360 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 361 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 362 0)) != 0) { 363 printf("%s: unable to load control data DMA map, error = %d\n", 364 sc->sc_dev.dv_xname, error); 365 goto fail_3; 366 } 367 368 /* 369 * Create the transmit buffer DMA maps. 370 */ 371 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 372 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 373 EMAC_NTXSEGS, MCLBYTES, 0, 0, 374 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 375 printf("%s: unable to create tx DMA map %d, " 376 "error = %d\n", sc->sc_dev.dv_xname, i, error); 377 goto fail_4; 378 } 379 } 380 381 /* 382 * Create the receive buffer DMA maps. 383 */ 384 for (i = 0; i < EMAC_NRXDESC; i++) { 385 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 386 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 387 printf("%s: unable to create rx DMA map %d, " 388 "error = %d\n", sc->sc_dev.dv_xname, i, error); 389 goto fail_5; 390 } 391 sc->sc_rxsoft[i].rxs_mbuf = NULL; 392 } 393 394 /* 395 * Reset the chip to a known state. 396 */ 397 emac_reset(sc); 398 399 /* Fetch the Ethernet address. */ 400 if (prop_get(dev_propdb, &sc->sc_dev, "mac-addr", enaddr, 401 sizeof(enaddr), NULL) != sizeof(enaddr)) { 402 printf("%s: unable to get mac-addr property\n", 403 sc->sc_dev.dv_xname); 404 return; 405 } 406 407 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 408 ether_sprintf(enaddr)); 409 410 /* 411 * Initialise the media structures. 412 */ 413 mii->mii_ifp = ifp; 414 mii->mii_readreg = emac_mii_readreg; 415 mii->mii_writereg = emac_mii_writereg; 416 mii->mii_statchg = emac_mii_statchg; 417 418 ifmedia_init(&mii->mii_media, 0, emac_mediachange, 419 emac_mediastatus); 420 mii_attach(&sc->sc_dev, mii, 0xffffffff, 421 MII_PHY_ANY, MII_OFFSET_ANY, 0); 422 if (LIST_FIRST(&mii->mii_phys) == NULL) { 423 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 424 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 425 } else 426 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 427 428 ifp = &sc->sc_ethercom.ec_if; 429 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 430 ifp->if_softc = sc; 431 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 432 ifp->if_ioctl = emac_ioctl; 433 ifp->if_start = emac_start; 434 ifp->if_watchdog = emac_watchdog; 435 ifp->if_init = emac_init; 436 ifp->if_stop = emac_stop; 437 IFQ_SET_READY(&ifp->if_snd); 438 439 /* 440 * We can support 802.1Q VLAN-sized frames. 441 */ 442 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 443 444 /* 445 * Attach the interface. 446 */ 447 if_attach(ifp); 448 ether_ifattach(ifp, enaddr); 449 450 #ifdef EMAC_EVENT_COUNTERS 451 /* 452 * Attach the event counters. 453 */ 454 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 455 NULL, sc->sc_dev.dv_xname, "rxintr"); 456 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 457 NULL, sc->sc_dev.dv_xname, "txintr"); 458 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 459 NULL, sc->sc_dev.dv_xname, "rxde"); 460 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 461 NULL, sc->sc_dev.dv_xname, "txde"); 462 evcnt_attach_dynamic(&sc->sc_ev_wol, EVCNT_TYPE_INTR, 463 NULL, sc->sc_dev.dv_xname, "wol"); 464 evcnt_attach_dynamic(&sc->sc_ev_serr, EVCNT_TYPE_INTR, 465 NULL, sc->sc_dev.dv_xname, "serr"); 466 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 467 NULL, sc->sc_dev.dv_xname, "intr"); 468 469 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 470 NULL, sc->sc_dev.dv_xname, "txreap"); 471 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 472 NULL, sc->sc_dev.dv_xname, "txsstall"); 473 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 474 NULL, sc->sc_dev.dv_xname, "txdstall"); 475 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 476 NULL, sc->sc_dev.dv_xname, "txdrop"); 477 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 478 NULL, sc->sc_dev.dv_xname, "tu"); 479 #endif /* EMAC_EVENT_COUNTERS */ 480 481 /* 482 * Make sure the interface is shutdown during reboot. 483 */ 484 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 485 if (sc->sc_sdhook == NULL) 486 printf("%s: WARNING: unable to establish shutdown hook\n", 487 sc->sc_dev.dv_xname); 488 489 return; 490 491 /* 492 * Free any resources we've allocated during the failed attach 493 * attempt. Do this in reverse order and fall through. 494 */ 495 fail_5: 496 for (i = 0; i < EMAC_NRXDESC; i++) { 497 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 498 bus_dmamap_destroy(sc->sc_dmat, 499 sc->sc_rxsoft[i].rxs_dmamap); 500 } 501 fail_4: 502 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 503 if (sc->sc_txsoft[i].txs_dmamap != NULL) 504 bus_dmamap_destroy(sc->sc_dmat, 505 sc->sc_txsoft[i].txs_dmamap); 506 } 507 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 508 fail_3: 509 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 510 fail_2: 511 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 512 sizeof(struct emac_control_data)); 513 fail_1: 514 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 515 fail_0: 516 return; 517 } 518 519 /* 520 * Device shutdown routine. 521 */ 522 static void 523 emac_shutdown(void *arg) 524 { 525 struct emac_softc *sc = arg; 526 527 emac_stop(&sc->sc_ethercom.ec_if, 0); 528 } 529 530 /* ifnet interface function */ 531 static void 532 emac_start(struct ifnet *ifp) 533 { 534 struct emac_softc *sc = ifp->if_softc; 535 struct mbuf *m0; 536 struct emac_txsoft *txs; 537 bus_dmamap_t dmamap; 538 int error, firsttx, nexttx, lasttx, ofree, seg; 539 540 lasttx = 0; /* XXX gcc */ 541 542 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 543 return; 544 545 /* 546 * Remember the previous number of free descriptors. 547 */ 548 ofree = sc->sc_txfree; 549 550 /* 551 * Loop through the send queue, setting up transmit descriptors 552 * until we drain the queue, or use up all available transmit 553 * descriptors. 554 */ 555 for (;;) { 556 /* Grab a packet off the queue. */ 557 IFQ_POLL(&ifp->if_snd, m0); 558 if (m0 == NULL) 559 break; 560 561 /* 562 * Get a work queue entry. Reclaim used Tx descriptors if 563 * we are running low. 564 */ 565 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 566 emac_txreap(sc); 567 if (sc->sc_txsfree == 0) { 568 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 569 break; 570 } 571 } 572 573 txs = &sc->sc_txsoft[sc->sc_txsnext]; 574 dmamap = txs->txs_dmamap; 575 576 /* 577 * Load the DMA map. If this fails, the packet either 578 * didn't fit in the alloted number of segments, or we 579 * were short on resources. In this case, we'll copy 580 * and try again. 581 */ 582 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 583 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 584 if (error) { 585 if (error == EFBIG) { 586 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 587 printf("%s: Tx packet consumes too many " 588 "DMA segments, dropping...\n", 589 sc->sc_dev.dv_xname); 590 IFQ_DEQUEUE(&ifp->if_snd, m0); 591 m_freem(m0); 592 continue; 593 } 594 /* Short on resources, just stop for now. */ 595 break; 596 } 597 598 /* 599 * Ensure we have enough descriptors free to describe 600 * the packet. 601 */ 602 if (dmamap->dm_nsegs > sc->sc_txfree) { 603 /* 604 * Not enough free descriptors to transmit this 605 * packet. We haven't committed anything yet, 606 * so just unload the DMA map, put the packet 607 * back on the queue, and punt. Notify the upper 608 * layer that there are not more slots left. 609 * 610 */ 611 ifp->if_flags |= IFF_OACTIVE; 612 bus_dmamap_unload(sc->sc_dmat, dmamap); 613 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 614 break; 615 } 616 617 IFQ_DEQUEUE(&ifp->if_snd, m0); 618 619 /* 620 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 621 */ 622 623 /* Sync the DMA map. */ 624 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 625 BUS_DMASYNC_PREWRITE); 626 627 /* 628 * Store a pointer to the packet so that we can free it 629 * later. 630 */ 631 txs->txs_mbuf = m0; 632 txs->txs_firstdesc = sc->sc_txnext; 633 txs->txs_ndesc = dmamap->dm_nsegs; 634 635 /* 636 * Initialize the transmit descriptor. 637 */ 638 firsttx = sc->sc_txnext; 639 for (nexttx = sc->sc_txnext, seg = 0; 640 seg < dmamap->dm_nsegs; 641 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 642 /* 643 * If this is the first descriptor we're 644 * enqueueing, don't set the TX_READY bit just 645 * yet. That could cause a race condition. 646 * We'll do it below. 647 */ 648 sc->sc_txdescs[nexttx].md_data = 649 dmamap->dm_segs[seg].ds_addr; 650 sc->sc_txdescs[nexttx].md_data_len = 651 dmamap->dm_segs[seg].ds_len; 652 sc->sc_txdescs[nexttx].md_stat_ctrl = 653 (sc->sc_txdescs[nexttx].md_stat_ctrl & MAL_TX_WRAP) | 654 (nexttx == firsttx ? 0 : MAL_TX_READY) | 655 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 656 lasttx = nexttx; 657 } 658 659 /* Set the LAST bit on the last segment. */ 660 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 661 662 txs->txs_lastdesc = lasttx; 663 664 /* Sync the descriptors we're using. */ 665 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 666 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 667 668 /* 669 * The entire packet chain is set up. Give the 670 * first descriptor to the chip now. 671 */ 672 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 673 EMAC_CDTXSYNC(sc, firsttx, 1, 674 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 675 /* 676 * Tell the EMAC that a new packet is available. 677 */ 678 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0); 679 680 /* Advance the tx pointer. */ 681 sc->sc_txfree -= txs->txs_ndesc; 682 sc->sc_txnext = nexttx; 683 684 sc->sc_txsfree--; 685 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 686 687 #if NBPFILTER > 0 688 /* 689 * Pass the packet to any BPF listeners. 690 */ 691 if (ifp->if_bpf) 692 bpf_mtap(ifp->if_bpf, m0); 693 #endif /* NBPFILTER > 0 */ 694 } 695 696 if (sc->sc_txfree == 0) { 697 /* No more slots left; notify upper layer. */ 698 ifp->if_flags |= IFF_OACTIVE; 699 } 700 701 if (sc->sc_txfree != ofree) { 702 /* Set a watchdog timer in case the chip flakes out. */ 703 ifp->if_timer = 5; 704 } 705 } 706 707 static int 708 emac_init(struct ifnet *ifp) 709 { 710 struct emac_softc *sc = ifp->if_softc; 711 struct emac_rxsoft *rxs; 712 uint8_t *enaddr = LLADDR(ifp->if_sadl); 713 int error, i; 714 715 error = 0; 716 717 /* Cancel any pending I/O. */ 718 emac_stop(ifp, 0); 719 720 /* Reset the chip to a known state. */ 721 emac_reset(sc); 722 723 /* 724 * Initialise the transmit descriptor ring. 725 */ 726 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 727 /* set wrap on last descriptor */ 728 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 729 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 730 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 731 sc->sc_txfree = EMAC_NTXDESC; 732 sc->sc_txnext = 0; 733 734 /* 735 * Initialise the transmit job descriptors. 736 */ 737 for (i = 0; i < EMAC_TXQUEUELEN; i++) 738 sc->sc_txsoft[i].txs_mbuf = NULL; 739 sc->sc_txsfree = EMAC_TXQUEUELEN; 740 sc->sc_txsnext = 0; 741 sc->sc_txsdirty = 0; 742 743 /* 744 * Initialise the receiver descriptor and receive job 745 * descriptor rings. 746 */ 747 for (i = 0; i < EMAC_NRXDESC; i++) { 748 rxs = &sc->sc_rxsoft[i]; 749 if (rxs->rxs_mbuf == NULL) { 750 if ((error = emac_add_rxbuf(sc, i)) != 0) { 751 printf("%s: unable to allocate or map rx " 752 "buffer %d, error = %d\n", 753 sc->sc_dev.dv_xname, i, error); 754 /* 755 * XXX Should attempt to run with fewer receive 756 * XXX buffers instead of just failing. 757 */ 758 emac_rxdrain(sc); 759 goto out; 760 } 761 } else 762 EMAC_INIT_RXDESC(sc, i); 763 } 764 sc->sc_rxptr = 0; 765 766 /* 767 * Set the current media. 768 */ 769 mii_mediachg(&sc->sc_mii); 770 771 /* 772 * Give the transmit and receive rings to the MAL. 773 */ 774 mtdcr(DCR_MAL0_TXCTP0R, EMAC_CDTXADDR(sc, 0)); 775 mtdcr(DCR_MAL0_RXCTP0R, EMAC_CDRXADDR(sc, 0)); 776 777 /* 778 * Load the MAC address. 779 */ 780 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 781 EMAC_WRITE(sc, EMAC_IALR, 782 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 783 784 /* 785 * Set the receive channel buffer size (in units of 16 bytes). 786 */ 787 #if MCLBYTES > (4096 - 16) /* XXX! */ 788 # error MCLBYTES > max rx channel buffer size 789 #endif 790 mtdcr(DCR_MAL0_RCBS0, MCLBYTES / 16); 791 792 /* Set fifos, media modes. */ 793 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 794 795 /* 796 * Enable Individual and (possibly) Broadcast Address modes, 797 * runt packets, and strip padding. 798 */ 799 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | 800 (ifp->if_flags & IFF_PROMISC ? RMR_PME : 0) | 801 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 802 803 /* 804 * Set low- and urgent-priority request thresholds. 805 */ 806 EMAC_WRITE(sc, EMAC_TMR1, 807 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 808 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 809 /* 810 * Set Transmit Request Threshold Register. 811 */ 812 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 813 814 /* 815 * Set high and low receive watermarks. 816 */ 817 EMAC_WRITE(sc, EMAC_RWMR, 818 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 819 820 /* 821 * Set frame gap. 822 */ 823 EMAC_WRITE(sc, EMAC_IPGVR, 8); 824 825 /* 826 * Set interrupt status enable bits for EMAC and MAL. 827 */ 828 EMAC_WRITE(sc, EMAC_ISER, 829 ISR_BP | ISR_SE | ISR_ALE | ISR_BFCS | ISR_PTLE | ISR_ORE | ISR_IRE); 830 mtdcr(DCR_MAL0_IER, MAL0_IER_DE | MAL0_IER_NWE | MAL0_IER_TO | 831 MAL0_IER_OPB | MAL0_IER_PLB); 832 833 /* 834 * Enable the transmit and receive channel on the MAL. 835 */ 836 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 837 mtdcr(DCR_MAL0_TXCASR, MAL0_TXCASR_CHAN0); 838 839 /* 840 * Enable the transmit and receive channel on the EMAC. 841 */ 842 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 843 844 /* 845 * Start the one second MII clock. 846 */ 847 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 848 849 /* 850 * ... all done! 851 */ 852 ifp->if_flags |= IFF_RUNNING; 853 ifp->if_flags &= ~IFF_OACTIVE; 854 855 out: 856 if (error) { 857 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 858 ifp->if_timer = 0; 859 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 860 } 861 return (error); 862 } 863 864 static int 865 emac_add_rxbuf(struct emac_softc *sc, int idx) 866 { 867 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 868 struct mbuf *m; 869 int error; 870 871 MGETHDR(m, M_DONTWAIT, MT_DATA); 872 if (m == NULL) 873 return (ENOBUFS); 874 875 MCLGET(m, M_DONTWAIT); 876 if ((m->m_flags & M_EXT) == 0) { 877 m_freem(m); 878 return (ENOBUFS); 879 } 880 881 if (rxs->rxs_mbuf != NULL) 882 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 883 884 rxs->rxs_mbuf = m; 885 886 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 887 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 888 if (error) { 889 printf("%s: can't load rx DMA map %d, error = %d\n", 890 sc->sc_dev.dv_xname, idx, error); 891 panic("emac_add_rxbuf"); /* XXX */ 892 } 893 894 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 895 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 896 897 EMAC_INIT_RXDESC(sc, idx); 898 899 return (0); 900 } 901 902 /* ifnet interface function */ 903 static void 904 emac_watchdog(struct ifnet *ifp) 905 { 906 struct emac_softc *sc = ifp->if_softc; 907 908 /* 909 * Since we're not interrupting every packet, sweep 910 * up before we report an error. 911 */ 912 emac_txreap(sc); 913 914 if (sc->sc_txfree != EMAC_NTXDESC) { 915 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 916 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 917 sc->sc_txnext); 918 ifp->if_oerrors++; 919 920 /* Reset the interface. */ 921 (void)emac_init(ifp); 922 } else if (ifp->if_flags & IFF_DEBUG) 923 printf("%s: recovered from device timeout\n", 924 sc->sc_dev.dv_xname); 925 926 /* try to get more packets going */ 927 emac_start(ifp); 928 } 929 930 static void 931 emac_rxdrain(struct emac_softc *sc) 932 { 933 struct emac_rxsoft *rxs; 934 int i; 935 936 for (i = 0; i < EMAC_NRXDESC; i++) { 937 rxs = &sc->sc_rxsoft[i]; 938 if (rxs->rxs_mbuf != NULL) { 939 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 940 m_freem(rxs->rxs_mbuf); 941 rxs->rxs_mbuf = NULL; 942 } 943 } 944 } 945 946 /* ifnet interface function */ 947 static void 948 emac_stop(struct ifnet *ifp, int disable) 949 { 950 struct emac_softc *sc = ifp->if_softc; 951 struct emac_txsoft *txs; 952 int i; 953 954 /* Stop the one second clock. */ 955 callout_stop(&sc->sc_callout); 956 957 /* Down the MII */ 958 mii_down(&sc->sc_mii); 959 960 /* Disable interrupts. */ 961 #if 0 /* Can't disable MAL interrupts without a reset... */ 962 EMAC_WRITE(sc, EMAC_ISER, 0); 963 #endif 964 mtdcr(DCR_MAL0_IER, 0); 965 966 /* Disable the receive and transmit channels. */ 967 mtdcr(DCR_MAL0_RXCARR, MAL0_RXCARR_CHAN0); 968 mtdcr(DCR_MAL0_TXCARR, MAL0_TXCARR_CHAN0 | MAL0_TXCARR_CHAN1); 969 970 /* Disable the transmit enable and receive MACs. */ 971 EMAC_WRITE(sc, EMAC_MR0, 972 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 973 974 /* Release any queued transmit buffers. */ 975 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 976 txs = &sc->sc_txsoft[i]; 977 if (txs->txs_mbuf != NULL) { 978 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 979 m_freem(txs->txs_mbuf); 980 txs->txs_mbuf = NULL; 981 } 982 } 983 984 if (disable) 985 emac_rxdrain(sc); 986 987 /* 988 * Mark the interface down and cancel the watchdog timer. 989 */ 990 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 991 ifp->if_timer = 0; 992 } 993 994 /* ifnet interface function */ 995 static int 996 emac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 997 { 998 struct emac_softc *sc = ifp->if_softc; 999 struct ifreq *ifr = (struct ifreq *)data; 1000 int s, error; 1001 1002 s = splnet(); 1003 1004 switch (cmd) { 1005 case SIOCSIFMEDIA: 1006 case SIOCGIFMEDIA: 1007 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1008 break; 1009 1010 default: 1011 error = ether_ioctl(ifp, cmd, data); 1012 if (error == ENETRESET) { 1013 /* 1014 * Multicast list has changed; set the hardware filter 1015 * accordingly. 1016 */ 1017 if (ifp->if_flags & IFF_RUNNING) 1018 error = emac_set_filter(sc); 1019 else 1020 error = 0; 1021 } 1022 break; 1023 } 1024 1025 /* try to get more packets going */ 1026 emac_start(ifp); 1027 1028 splx(s); 1029 return (error); 1030 } 1031 1032 static void 1033 emac_reset(struct emac_softc *sc) 1034 { 1035 1036 /* reset the MAL */ 1037 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR); 1038 1039 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1040 delay(5); 1041 1042 /* XXX: check if MR0_SRST is clear until a timeout instead? */ 1043 EMAC_WRITE(sc, EMAC_MR0, EMAC_READ(sc, EMAC_MR0) & ~MR0_SRST); 1044 1045 /* XXX clear interrupts in EMAC_ISR just to be sure?? */ 1046 1047 /* set the MAL config register */ 1048 mtdcr(DCR_MAL0_CFG, MAL0_CFG_PLBB | MAL0_CFG_OPBBL | MAL0_CFG_LEA | 1049 MAL0_CFG_SD | MAL0_CFG_PLBLT); 1050 } 1051 1052 static int 1053 emac_set_filter(struct emac_softc *sc) 1054 { 1055 struct ether_multistep step; 1056 struct ether_multi *enm; 1057 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1058 uint32_t rmr, crc, gaht[4] = {0, 0, 0, 0}; 1059 int category, cnt = 0; 1060 1061 rmr = EMAC_READ(sc, EMAC_RMR); 1062 rmr &= ~(RMR_PMME | RMR_MAE); 1063 ifp->if_flags &= ~IFF_ALLMULTI; 1064 1065 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1066 while (enm != NULL) { 1067 if (memcmp(enm->enm_addrlo, 1068 enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1069 /* 1070 * We must listen to a range of multicast addresses. 1071 * For now, just accept all multicasts, rather than 1072 * trying to set only those filter bits needed to match 1073 * the range. (At this time, the only use of address 1074 * ranges is for IP multicast routing, for which the 1075 * range is big enough to require all bits set.) 1076 */ 1077 gaht[0] = gaht[1] = gaht[2] = gaht[3] = 0xffff; 1078 break; 1079 } 1080 1081 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1082 1083 /* Just want the 6 most significant bits. */ 1084 category = crc >> 26; 1085 EMAC_SET_FILTER(gaht, category); 1086 1087 ETHER_NEXT_MULTI(step, enm); 1088 cnt++; 1089 } 1090 1091 if ((gaht[0] & gaht[1] & gaht[2] & gaht[3]) == 0xffff) { 1092 /* All categories are true. */ 1093 ifp->if_flags |= IFF_ALLMULTI; 1094 rmr |= RMR_PMME; 1095 } else if (cnt != 0) { 1096 /* Some categories are true. */ 1097 EMAC_WRITE(sc, EMAC_GAHT1, gaht[0]); 1098 EMAC_WRITE(sc, EMAC_GAHT2, gaht[1]); 1099 EMAC_WRITE(sc, EMAC_GAHT3, gaht[2]); 1100 EMAC_WRITE(sc, EMAC_GAHT4, gaht[3]); 1101 1102 rmr |= RMR_MAE; 1103 } 1104 EMAC_WRITE(sc, EMAC_RMR, rmr); 1105 1106 return 0; 1107 } 1108 1109 /* 1110 * EMAC General interrupt handler 1111 */ 1112 static int 1113 emac_intr(void *arg) 1114 { 1115 struct emac_softc *sc = arg; 1116 uint32_t status; 1117 1118 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 1119 status = EMAC_READ(sc, EMAC_ISR); 1120 1121 /* Clear the interrupt status bits. */ 1122 EMAC_WRITE(sc, EMAC_ISR, status); 1123 1124 return (0); 1125 } 1126 1127 /* 1128 * EMAC Wake-On-LAN interrupt handler 1129 */ 1130 static int 1131 emac_wol_intr(void *arg) 1132 { 1133 struct emac_softc *sc = arg; 1134 1135 EMAC_EVCNT_INCR(&sc->sc_ev_wol); 1136 printf("%s: emac_wol_intr\n", sc->sc_dev.dv_xname); 1137 return (0); 1138 } 1139 1140 /* 1141 * MAL System ERRor interrupt handler 1142 */ 1143 static int 1144 emac_serr_intr(void *arg) 1145 { 1146 #ifdef EMAC_EVENT_COUNTERS 1147 struct emac_softc *sc = arg; 1148 #endif 1149 u_int32_t esr; 1150 1151 EMAC_EVCNT_INCR(&sc->sc_ev_serr); 1152 esr = mfdcr(DCR_MAL0_ESR); 1153 1154 /* Clear the interrupt status bits. */ 1155 mtdcr(DCR_MAL0_ESR, esr); 1156 return (0); 1157 } 1158 1159 /* 1160 * MAL Transmit End-Of-Buffer interrupt handler. 1161 * NOTE: This shouldn't be called! 1162 */ 1163 static int 1164 emac_txeob_intr(void *arg) 1165 { 1166 #ifdef EMAC_EVENT_COUNTERS 1167 struct emac_softc *sc = arg; 1168 #endif 1169 1170 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1171 emac_txreap(arg); 1172 1173 return (0); 1174 1175 } 1176 1177 /* 1178 * Reap completed Tx descriptors. 1179 */ 1180 static int 1181 emac_txreap(struct emac_softc *sc) 1182 { 1183 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1184 struct emac_txsoft *txs; 1185 int i; 1186 u_int32_t txstat; 1187 1188 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1189 1190 /* Clear the interrupt */ 1191 mtdcr(DCR_MAL0_TXEOBISR, mfdcr(DCR_MAL0_TXEOBISR)); 1192 1193 ifp->if_flags &= ~IFF_OACTIVE; 1194 1195 /* 1196 * Go through our Tx list and free mbufs for those 1197 * frames that have been transmitted. 1198 */ 1199 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1200 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1201 txs = &sc->sc_txsoft[i]; 1202 1203 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1204 txs->txs_dmamap->dm_nsegs, 1205 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1206 1207 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1208 if (txstat & MAL_TX_READY) 1209 break; 1210 1211 /* 1212 * Check for errors and collisions. 1213 */ 1214 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1215 ifp->if_oerrors++; 1216 1217 #ifdef EMAC_EVENT_COUNTERS 1218 if (txstat & EMAC_TXS_UR) 1219 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1220 #endif /* EMAC_EVENT_COUNTERS */ 1221 1222 if (txstat & (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1223 if (txstat & EMAC_TXS_EC) 1224 ifp->if_collisions += 16; 1225 else if (txstat & EMAC_TXS_MC) 1226 ifp->if_collisions += 2; /* XXX? */ 1227 else if (txstat & EMAC_TXS_SC) 1228 ifp->if_collisions++; 1229 if (txstat & EMAC_TXS_LC) 1230 ifp->if_collisions++; 1231 } else 1232 ifp->if_opackets++; 1233 1234 if (ifp->if_flags & IFF_DEBUG) { 1235 if (txstat & EMAC_TXS_ED) 1236 printf("%s: excessive deferral\n", 1237 sc->sc_dev.dv_xname); 1238 if (txstat & EMAC_TXS_EC) 1239 printf("%s: excessive collisions\n", 1240 sc->sc_dev.dv_xname); 1241 } 1242 1243 sc->sc_txfree += txs->txs_ndesc; 1244 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1245 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1246 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1247 m_freem(txs->txs_mbuf); 1248 txs->txs_mbuf = NULL; 1249 } 1250 1251 /* Update the dirty transmit buffer pointer. */ 1252 sc->sc_txsdirty = i; 1253 1254 /* 1255 * If there are no more pending transmissions, cancel the watchdog 1256 * timer. 1257 */ 1258 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1259 ifp->if_timer = 0; 1260 1261 return (0); 1262 } 1263 1264 /* 1265 * MAL Receive End-Of-Buffer interrupt handler 1266 */ 1267 static int 1268 emac_rxeob_intr(void *arg) 1269 { 1270 struct emac_softc *sc = arg; 1271 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1272 struct emac_rxsoft *rxs; 1273 struct mbuf *m; 1274 u_int32_t rxstat; 1275 int i, len; 1276 1277 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1278 1279 /* Clear the interrupt */ 1280 mtdcr(DCR_MAL0_RXEOBISR, mfdcr(DCR_MAL0_RXEOBISR)); 1281 1282 for (i = sc->sc_rxptr;; i = EMAC_NEXTRX(i)) { 1283 rxs = &sc->sc_rxsoft[i]; 1284 1285 EMAC_CDRXSYNC(sc, i, 1286 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1287 1288 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1289 1290 if (rxstat & MAL_RX_EMPTY) 1291 /* 1292 * We have processed all of the receive buffers. 1293 */ 1294 break; 1295 1296 /* 1297 * If an error occurred, update stats, clear the status 1298 * word, and leave the packet buffer in place. It will 1299 * simply be reused the next time the ring comes around. 1300 */ 1301 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1302 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1303 EMAC_RXS_IRE)) { 1304 #define PRINTERR(bit, str) \ 1305 if (rxstat & (bit)) \ 1306 printf("%s: receive error: %s\n", \ 1307 sc->sc_dev.dv_xname, str) 1308 ifp->if_ierrors++; 1309 PRINTERR(EMAC_RXS_OE, "overrun error"); 1310 PRINTERR(EMAC_RXS_BP, "bad packet"); 1311 PRINTERR(EMAC_RXS_RP, "runt packet"); 1312 PRINTERR(EMAC_RXS_SE, "short event"); 1313 PRINTERR(EMAC_RXS_AE, "alignment error"); 1314 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1315 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1316 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1317 PRINTERR(EMAC_RXS_IRE, "in range error"); 1318 #undef PRINTERR 1319 EMAC_INIT_RXDESC(sc, i); 1320 continue; 1321 } 1322 1323 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1324 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1325 1326 /* 1327 * No errors; receive the packet. Note, the 405GP emac 1328 * includes the CRC with every packet. 1329 */ 1330 len = sc->sc_rxdescs[i].md_data_len; 1331 1332 /* 1333 * If the packet is small enough to fit in a 1334 * single header mbuf, allocate one and copy 1335 * the data into it. This greatly reduces 1336 * memory consumption when we receive lots 1337 * of small packets. 1338 * 1339 * Otherwise, we add a new buffer to the receive 1340 * chain. If this fails, we drop the packet and 1341 * recycle the old buffer. 1342 */ 1343 if (emac_copy_small != 0 && len <= MHLEN) { 1344 MGETHDR(m, M_DONTWAIT, MT_DATA); 1345 if (m == NULL) 1346 goto dropit; 1347 memcpy(mtod(m, caddr_t), 1348 mtod(rxs->rxs_mbuf, caddr_t), len); 1349 EMAC_INIT_RXDESC(sc, i); 1350 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1351 rxs->rxs_dmamap->dm_mapsize, 1352 BUS_DMASYNC_PREREAD); 1353 } else { 1354 m = rxs->rxs_mbuf; 1355 if (emac_add_rxbuf(sc, i) != 0) { 1356 dropit: 1357 ifp->if_ierrors++; 1358 EMAC_INIT_RXDESC(sc, i); 1359 bus_dmamap_sync(sc->sc_dmat, 1360 rxs->rxs_dmamap, 0, 1361 rxs->rxs_dmamap->dm_mapsize, 1362 BUS_DMASYNC_PREREAD); 1363 continue; 1364 } 1365 } 1366 1367 ifp->if_ipackets++; 1368 m->m_flags |= M_HASFCS; 1369 m->m_pkthdr.rcvif = ifp; 1370 m->m_pkthdr.len = m->m_len = len; 1371 1372 #if NBPFILTER > 0 1373 /* 1374 * Pass this up to any BPF listeners, but only 1375 * pass if up the stack if it's for us. 1376 */ 1377 if (ifp->if_bpf) 1378 bpf_mtap(ifp->if_bpf, m); 1379 #endif /* NBPFILTER > 0 */ 1380 1381 /* Pass it on. */ 1382 (*ifp->if_input)(ifp, m); 1383 } 1384 1385 /* Update the receive pointer. */ 1386 sc->sc_rxptr = i; 1387 1388 return (0); 1389 } 1390 1391 /* 1392 * MAL Transmit Descriptor Error interrupt handler 1393 */ 1394 static int 1395 emac_txde_intr(void *arg) 1396 { 1397 struct emac_softc *sc = arg; 1398 1399 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1400 printf("%s: emac_txde_intr\n", sc->sc_dev.dv_xname); 1401 return (0); 1402 } 1403 1404 /* 1405 * MAL Receive Descriptor Error interrupt handler 1406 */ 1407 static int 1408 emac_rxde_intr(void *arg) 1409 { 1410 int i; 1411 struct emac_softc *sc = arg; 1412 1413 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1414 printf("%s: emac_rxde_intr\n", sc->sc_dev.dv_xname); 1415 /* 1416 * XXX! 1417 * This is a bit drastic; we just drop all descriptors that aren't 1418 * "clean". We should probably send any that are up the stack. 1419 */ 1420 for (i = 0; i < EMAC_NRXDESC; i++) { 1421 EMAC_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1422 1423 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) { 1424 EMAC_INIT_RXDESC(sc, i); 1425 } 1426 1427 } 1428 1429 /* Reenable the receive channel */ 1430 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 1431 1432 /* Clear the interrupt */ 1433 mtdcr(DCR_MAL0_RXDEIR, mfdcr(DCR_MAL0_RXDEIR)); 1434 1435 return (0); 1436 } 1437 1438 static uint32_t 1439 emac_mii_wait(struct emac_softc *sc) 1440 { 1441 int i; 1442 uint32_t reg; 1443 1444 /* wait for PHY data transfer to complete */ 1445 i = 0; 1446 while ((reg = EMAC_READ(sc, EMAC_STACR) & STACR_OC) == 0) { 1447 delay(7); 1448 if (i++ > 5) { 1449 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1450 return (0); 1451 } 1452 } 1453 return (reg); 1454 } 1455 1456 static int 1457 emac_mii_readreg(struct device *self, int phy, int reg) 1458 { 1459 struct emac_softc *sc = (struct emac_softc *)self; 1460 uint32_t sta_reg; 1461 1462 /* wait for PHY data transfer to complete */ 1463 if (emac_mii_wait(sc) == 0) 1464 return (0); 1465 1466 sta_reg = reg << STACR_PRASHIFT; 1467 sta_reg |= STACR_READ; 1468 sta_reg |= phy << STACR_PCDASHIFT; 1469 1470 sta_reg &= ~STACR_OPBC_MASK; 1471 sta_reg |= STACR_OPBC_50MHZ; 1472 1473 1474 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1475 1476 if ((sta_reg = emac_mii_wait(sc)) == 0) 1477 return (0); 1478 sta_reg = EMAC_READ(sc, EMAC_STACR); 1479 if ((sta_reg & STACR_PHYE) != 0) 1480 return (0); 1481 return (sta_reg >> STACR_PHYDSHIFT); 1482 } 1483 1484 static void 1485 emac_mii_writereg(struct device *self, int phy, int reg, int val) 1486 { 1487 struct emac_softc *sc = (struct emac_softc *)self; 1488 uint32_t sta_reg; 1489 1490 /* wait for PHY data transfer to complete */ 1491 if (emac_mii_wait(sc) == 0) 1492 return; 1493 1494 sta_reg = reg << STACR_PRASHIFT; 1495 sta_reg |= STACR_WRITE; 1496 sta_reg |= phy << STACR_PCDASHIFT; 1497 1498 sta_reg &= ~STACR_OPBC_MASK; 1499 sta_reg |= STACR_OPBC_50MHZ; 1500 1501 sta_reg |= val << STACR_PHYDSHIFT; 1502 1503 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1504 1505 if ((sta_reg = emac_mii_wait(sc)) == 0) 1506 return; 1507 if ((sta_reg & STACR_PHYE) != 0) 1508 /* error */ 1509 return; 1510 } 1511 1512 static void 1513 emac_mii_statchg(struct device *self) 1514 { 1515 struct emac_softc *sc = (void *)self; 1516 1517 if (sc->sc_mii.mii_media_active & IFM_FDX) 1518 sc->sc_mr1 |= MR1_FDE; 1519 else 1520 sc->sc_mr1 &= ~(MR1_FDE | MR1_EIFC); 1521 1522 /* XXX 802.1x flow-control? */ 1523 1524 /* 1525 * MR1 can only be written immediately after a reset... 1526 */ 1527 emac_reset(sc); 1528 } 1529 1530 static void 1531 emac_mii_tick(void *arg) 1532 { 1533 struct emac_softc *sc = arg; 1534 int s; 1535 1536 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1537 return; 1538 1539 s = splnet(); 1540 mii_tick(&sc->sc_mii); 1541 splx(s); 1542 1543 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1544 } 1545 1546 /* ifmedia interface function */ 1547 static void 1548 emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1549 { 1550 struct emac_softc *sc = ifp->if_softc; 1551 1552 mii_pollstat(&sc->sc_mii); 1553 1554 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1555 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1556 } 1557 1558 /* ifmedia interface function */ 1559 static int 1560 emac_mediachange(struct ifnet *ifp) 1561 { 1562 struct emac_softc *sc = ifp->if_softc; 1563 1564 if (ifp->if_flags & IFF_UP) 1565 mii_mediachg(&sc->sc_mii); 1566 return (0); 1567 } 1568