1 /* $NetBSD: if_emac.c,v 1.36 2010/03/18 13:47:04 kiyohara Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * emac(4) supports following ibm4xx's EMACs. 40 * XXXX: ZMII and 'TCP Accelaration Hardware' not support yet... 41 * 42 * tested 43 * ------ 44 * 405EP - 10/100 x2 45 * 405EX/EXr o 10/100/1000 x2 (EXr x1), STA v2, 256bit hash-Table, RGMII 46 * 405GP/GPr o 10/100 47 * 440EP - 10/100 x2, ZMII 48 * 440GP - 10/100 x2, ZMII 49 * 440GX - 10/100/1000 x4, ZMII/RGMII(ch 2, 3), TAH(ch 2, 3) 50 * 440SP - 10/100/1000 51 * 440SPe - 10/100/1000, STA v2 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.36 2010/03/18 13:47:04 kiyohara Exp $"); 56 57 #include "opt_emac.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/mbuf.h> 62 #include <sys/kernel.h> 63 #include <sys/socket.h> 64 #include <sys/ioctl.h> 65 66 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #include <net/bpf.h> 74 75 #include <powerpc/ibm4xx/dcr4xx.h> 76 #include <powerpc/ibm4xx/mal405gp.h> 77 #include <powerpc/ibm4xx/dev/emacreg.h> 78 #include <powerpc/ibm4xx/dev/if_emacreg.h> 79 #include <powerpc/ibm4xx/dev/if_emacvar.h> 80 #include <powerpc/ibm4xx/dev/malvar.h> 81 #include <powerpc/ibm4xx/dev/opbreg.h> 82 #include <powerpc/ibm4xx/dev/opbvar.h> 83 #include <powerpc/ibm4xx/dev/plbvar.h> 84 #if defined(EMAC_ZMII_PHY) || defined(EMAC_RGMII_PHY) 85 #include <powerpc/ibm4xx/dev/rmiivar.h> 86 #endif 87 88 #include <dev/mii/miivar.h> 89 90 #include "locators.h" 91 92 93 /* 94 * Transmit descriptor list size. There are two Tx channels, each with 95 * up to 256 hardware descriptors available. We currently use one Tx 96 * channel. We tell the upper layers that they can queue a lot of 97 * packets, and we go ahead and manage up to 64 of them at a time. We 98 * allow up to 16 DMA segments per packet. 99 */ 100 #define EMAC_NTXSEGS 16 101 #define EMAC_TXQUEUELEN 64 102 #define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 103 #define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 104 #define EMAC_NTXDESC 256 105 #define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 106 #define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 107 #define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 108 109 /* 110 * Receive descriptor list size. There is one Rx channel with up to 256 111 * hardware descriptors available. We allocate 64 receive descriptors, 112 * each with a 2k buffer (MCLBYTES). 113 */ 114 #define EMAC_NRXDESC 64 115 #define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 116 #define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 117 #define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 118 119 /* 120 * Transmit/receive descriptors that are DMA'd to the EMAC. 121 */ 122 struct emac_control_data { 123 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 124 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 125 }; 126 127 #define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 128 #define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 129 #define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 130 131 /* 132 * Software state for transmit jobs. 133 */ 134 struct emac_txsoft { 135 struct mbuf *txs_mbuf; /* head of mbuf chain */ 136 bus_dmamap_t txs_dmamap; /* our DMA map */ 137 int txs_firstdesc; /* first descriptor in packet */ 138 int txs_lastdesc; /* last descriptor in packet */ 139 int txs_ndesc; /* # of descriptors used */ 140 }; 141 142 /* 143 * Software state for receive descriptors. 144 */ 145 struct emac_rxsoft { 146 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 147 bus_dmamap_t rxs_dmamap; /* our DMA map */ 148 }; 149 150 /* 151 * Software state per device. 152 */ 153 struct emac_softc { 154 device_t sc_dev; /* generic device information */ 155 int sc_instance; /* instance no. */ 156 bus_space_tag_t sc_st; /* bus space tag */ 157 bus_space_handle_t sc_sh; /* bus space handle */ 158 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 159 struct ethercom sc_ethercom; /* ethernet common data */ 160 void *sc_sdhook; /* shutdown hook */ 161 void *sc_powerhook; /* power management hook */ 162 163 struct mii_data sc_mii; /* MII/media information */ 164 struct callout sc_callout; /* tick callout */ 165 166 uint32_t sc_mr1; /* copy of Mode Register 1 */ 167 uint32_t sc_stacr_read; /* Read opcode of STAOPC of STACR */ 168 uint32_t sc_stacr_write; /* Write opcode of STAOPC of STACR */ 169 uint32_t sc_stacr_bits; /* misc bits of STACR */ 170 bool sc_stacr_completed; /* Operation completed of STACR */ 171 int sc_htsize; /* Hash Table size */ 172 173 bus_dmamap_t sc_cddmamap; /* control data dma map */ 174 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 175 176 /* Software state for transmit/receive descriptors. */ 177 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 178 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 179 180 /* Control data structures. */ 181 struct emac_control_data *sc_control_data; 182 #define sc_txdescs sc_control_data->ecd_txdesc 183 #define sc_rxdescs sc_control_data->ecd_rxdesc 184 185 #ifdef EMAC_EVENT_COUNTERS 186 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 187 struct evcnt sc_ev_txintr; /* Tx interrupts */ 188 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 189 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 190 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 191 192 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 193 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 194 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 195 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 196 struct evcnt sc_ev_tu; /* Tx underrun */ 197 #endif /* EMAC_EVENT_COUNTERS */ 198 199 int sc_txfree; /* number of free Tx descriptors */ 200 int sc_txnext; /* next ready Tx descriptor */ 201 202 int sc_txsfree; /* number of free Tx jobs */ 203 int sc_txsnext; /* next ready Tx job */ 204 int sc_txsdirty; /* dirty Tx jobs */ 205 206 int sc_rxptr; /* next ready RX descriptor/descsoft */ 207 208 void (*sc_rmii_enable)(device_t, int); /* reduced MII enable */ 209 void (*sc_rmii_disable)(device_t, int); /* reduced MII disable*/ 210 void (*sc_rmii_speed)(device_t, int, int); /* reduced MII speed */ 211 }; 212 213 #ifdef EMAC_EVENT_COUNTERS 214 #define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 215 #else 216 #define EMAC_EVCNT_INCR(ev) /* nothing */ 217 #endif 218 219 #define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 220 #define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 221 222 #define EMAC_CDTXSYNC(sc, x, n, ops) \ 223 do { \ 224 int __x, __n; \ 225 \ 226 __x = (x); \ 227 __n = (n); \ 228 \ 229 /* If it will wrap around, sync to the end of the ring. */ \ 230 if ((__x + __n) > EMAC_NTXDESC) { \ 231 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 232 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 233 (EMAC_NTXDESC - __x), (ops)); \ 234 __n -= (EMAC_NTXDESC - __x); \ 235 __x = 0; \ 236 } \ 237 \ 238 /* Now sync whatever is left. */ \ 239 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 240 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 241 } while (/*CONSTCOND*/0) 242 243 #define EMAC_CDRXSYNC(sc, x, ops) \ 244 do { \ 245 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 246 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 247 } while (/*CONSTCOND*/0) 248 249 #define EMAC_INIT_RXDESC(sc, x) \ 250 do { \ 251 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 252 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 253 struct mbuf *__m = __rxs->rxs_mbuf; \ 254 \ 255 /* \ 256 * Note: We scoot the packet forward 2 bytes in the buffer \ 257 * so that the payload after the Ethernet header is aligned \ 258 * to a 4-byte boundary. \ 259 */ \ 260 __m->m_data = __m->m_ext.ext_buf + 2; \ 261 \ 262 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 263 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 264 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 265 /* Set wrap on last descriptor. */ \ 266 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 267 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 268 } while (/*CONSTCOND*/0) 269 270 #define EMAC_WRITE(sc, reg, val) \ 271 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 272 #define EMAC_READ(sc, reg) \ 273 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 274 275 #define EMAC_SET_FILTER(aht, crc) \ 276 do { \ 277 (aht)[3 - (((crc) >> 26) >> 4)] |= 1 << (((crc) >> 26) & 0xf); \ 278 } while (/*CONSTCOND*/0) 279 #define EMAC_SET_FILTER256(aht, crc) \ 280 do { \ 281 (aht)[7 - (((crc) >> 24) >> 5)] |= 1 << (((crc) >> 24) & 0x1f); \ 282 } while (/*CONSTCOND*/0) 283 284 static int emac_match(device_t, cfdata_t, void *); 285 static void emac_attach(device_t, device_t, void *); 286 287 static int emac_intr(void *); 288 static void emac_shutdown(void *); 289 290 static void emac_start(struct ifnet *); 291 static int emac_ioctl(struct ifnet *, u_long, void *); 292 static int emac_init(struct ifnet *); 293 static void emac_stop(struct ifnet *, int); 294 static void emac_watchdog(struct ifnet *); 295 296 static int emac_add_rxbuf(struct emac_softc *, int); 297 static void emac_rxdrain(struct emac_softc *); 298 static int emac_set_filter(struct emac_softc *); 299 static int emac_txreap(struct emac_softc *); 300 301 static void emac_soft_reset(struct emac_softc *); 302 static void emac_smart_reset(struct emac_softc *); 303 304 static int emac_mii_readreg(device_t, int, int); 305 static void emac_mii_writereg(device_t, int, int, int); 306 static void emac_mii_statchg(device_t); 307 static uint32_t emac_mii_wait(struct emac_softc *); 308 static void emac_mii_tick(void *); 309 310 int emac_copy_small = 0; 311 312 CFATTACH_DECL_NEW(emac, sizeof(struct emac_softc), 313 emac_match, emac_attach, NULL, NULL); 314 315 316 static int 317 emac_match(device_t parent, cfdata_t cf, void *aux) 318 { 319 struct opb_attach_args *oaa = aux; 320 321 /* match only on-chip ethernet devices */ 322 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 323 return 1; 324 325 return 0; 326 } 327 328 static void 329 emac_attach(device_t parent, device_t self, void *aux) 330 { 331 struct opb_attach_args *oaa = aux; 332 struct emac_softc *sc = device_private(self); 333 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 334 struct mii_data *mii = &sc->sc_mii; 335 bus_dma_segment_t seg; 336 int error, i, nseg, opb_freq, opbc, mii_phy = MII_PHY_ANY; 337 const uint8_t *enaddr; 338 prop_dictionary_t dict = device_properties(self); 339 prop_data_t ea; 340 341 bus_space_map(oaa->opb_bt, oaa->opb_addr, EMAC_NREG, 0, &sc->sc_sh); 342 343 sc->sc_dev = self; 344 sc->sc_instance = oaa->opb_instance; 345 sc->sc_st = oaa->opb_bt; 346 sc->sc_dmat = oaa->opb_dmat; 347 348 callout_init(&sc->sc_callout, 0); 349 350 aprint_naive("\n"); 351 aprint_normal(": Ethernet Media Access Controller\n"); 352 353 /* Fetch the Ethernet address. */ 354 ea = prop_dictionary_get(dict, "mac-address"); 355 if (ea == NULL) { 356 aprint_error_dev(self, "unable to get mac-address property\n"); 357 return; 358 } 359 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 360 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 361 enaddr = prop_data_data_nocopy(ea); 362 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 363 364 #if defined(EMAC_ZMII_PHY) || defined(EMAC_RGMII_PHY) 365 /* Fetch the MII offset. */ 366 prop_dictionary_get_uint32(dict, "mii-phy", &mii_phy); 367 368 #ifdef EMAC_ZMII_PHY 369 if (oaa->opb_flags & OPB_FLAGS_EMAC_RMII_ZMII) 370 zmii_attach(parent, sc->sc_instance, &sc->sc_rmii_enable, 371 &sc->sc_rmii_disable, &sc->sc_rmii_speed); 372 #endif 373 #ifdef EMAC_RGMII_PHY 374 if (oaa->opb_flags & OPB_FLAGS_EMAC_RMII_RGMII) 375 rgmii_attach(parent, sc->sc_instance, &sc->sc_rmii_enable, 376 &sc->sc_rmii_disable, &sc->sc_rmii_speed); 377 #endif 378 #endif 379 380 /* 381 * Allocate the control data structures, and create and load the 382 * DMA map for it. 383 */ 384 if ((error = bus_dmamem_alloc(sc->sc_dmat, 385 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 386 aprint_error_dev(self, 387 "unable to allocate control data, error = %d\n", error); 388 goto fail_0; 389 } 390 391 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 392 sizeof(struct emac_control_data), (void **)&sc->sc_control_data, 393 BUS_DMA_COHERENT)) != 0) { 394 aprint_error_dev(self, 395 "unable to map control data, error = %d\n", error); 396 goto fail_1; 397 } 398 399 if ((error = bus_dmamap_create(sc->sc_dmat, 400 sizeof(struct emac_control_data), 1, 401 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 402 aprint_error_dev(self, 403 "unable to create control data DMA map, error = %d\n", 404 error); 405 goto fail_2; 406 } 407 408 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 409 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 410 0)) != 0) { 411 aprint_error_dev(self, 412 "unable to load control data DMA map, error = %d\n", error); 413 goto fail_3; 414 } 415 416 /* 417 * Create the transmit buffer DMA maps. 418 */ 419 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 420 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 421 EMAC_NTXSEGS, MCLBYTES, 0, 0, 422 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 423 aprint_error_dev(self, 424 "unable to create tx DMA map %d, error = %d\n", 425 i, error); 426 goto fail_4; 427 } 428 } 429 430 /* 431 * Create the receive buffer DMA maps. 432 */ 433 for (i = 0; i < EMAC_NRXDESC; i++) { 434 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 435 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 436 aprint_error_dev(self, 437 "unable to create rx DMA map %d, error = %d\n", 438 i, error); 439 goto fail_5; 440 } 441 sc->sc_rxsoft[i].rxs_mbuf = NULL; 442 } 443 444 /* Soft Reset the EMAC. The chip to a known state. */ 445 emac_soft_reset(sc); 446 447 opb_freq = opb_get_frequency(); 448 switch (opb_freq) { 449 case 50000000: opbc = STACR_OPBC_50MHZ; break; 450 case 66666666: opbc = STACR_OPBC_66MHZ; break; 451 case 83333333: opbc = STACR_OPBC_83MHZ; break; 452 case 100000000: opbc = STACR_OPBC_100MHZ; break; 453 454 default: 455 if (opb_freq > 100000000) { 456 opbc = STACR_OPBC_A100MHZ; 457 break; 458 } 459 aprint_error_dev(self, "unsupport OPB frequency %dMHz\n", 460 opb_freq / 1000 / 1000); 461 goto fail_5; 462 } 463 if (oaa->opb_flags & OPB_FLAGS_EMAC_GBE) { 464 sc->sc_mr1 = 465 MR1_RFS_GBE(MR1__FS_16KB) | 466 MR1_TFS_GBE(MR1__FS_16KB) | 467 MR1_TR0_MULTIPLE | 468 MR1_OBCI(opbc); 469 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 470 471 if (oaa->opb_flags & OPB_FLAGS_EMAC_STACV2) { 472 sc->sc_stacr_read = STACR_STAOPC_READ; 473 sc->sc_stacr_write = STACR_STAOPC_WRITE; 474 sc->sc_stacr_bits = STACR_OC; 475 sc->sc_stacr_completed = false; 476 } else { 477 sc->sc_stacr_read = STACR_READ; 478 sc->sc_stacr_write = STACR_WRITE; 479 sc->sc_stacr_completed = true; 480 } 481 } else { 482 /* 483 * Set up Mode Register 1 - set receive and transmit FIFOs to 484 * maximum size, allow transmit of multiple packets (only 485 * channel 0 is used). 486 * 487 * XXX: Allow pause packets?? 488 */ 489 sc->sc_mr1 = 490 MR1_RFS(MR1__FS_4KB) | 491 MR1_TFS(MR1__FS_2KB) | 492 MR1_TR0_MULTIPLE; 493 494 sc->sc_stacr_read = STACR_READ; 495 sc->sc_stacr_write = STACR_WRITE; 496 sc->sc_stacr_bits = STACR_OPBC(opbc); 497 sc->sc_stacr_completed = true; 498 } 499 500 intr_establish(oaa->opb_irq, IST_LEVEL, IPL_NET, emac_intr, sc); 501 mal_intr_establish(sc->sc_instance, sc); 502 503 if (oaa->opb_flags & OPB_FLAGS_EMAC_HT256) 504 sc->sc_htsize = 256; 505 else 506 sc->sc_htsize = 64; 507 508 /* Clear all interrupts */ 509 EMAC_WRITE(sc, EMAC_ISR, ISR_ALL); 510 511 /* 512 * Initialise the media structures. 513 */ 514 mii->mii_ifp = ifp; 515 mii->mii_readreg = emac_mii_readreg; 516 mii->mii_writereg = emac_mii_writereg; 517 mii->mii_statchg = emac_mii_statchg; 518 519 sc->sc_ethercom.ec_mii = mii; 520 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 521 mii_attach(self, mii, 0xffffffff, mii_phy, MII_OFFSET_ANY, 0); 522 if (LIST_FIRST(&mii->mii_phys) == NULL) { 523 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 524 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 525 } else 526 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 527 528 ifp = &sc->sc_ethercom.ec_if; 529 strcpy(ifp->if_xname, self->dv_xname); 530 ifp->if_softc = sc; 531 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 532 ifp->if_start = emac_start; 533 ifp->if_ioctl = emac_ioctl; 534 ifp->if_init = emac_init; 535 ifp->if_stop = emac_stop; 536 ifp->if_watchdog = emac_watchdog; 537 IFQ_SET_READY(&ifp->if_snd); 538 539 /* 540 * We can support 802.1Q VLAN-sized frames. 541 */ 542 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 543 544 /* 545 * Attach the interface. 546 */ 547 if_attach(ifp); 548 ether_ifattach(ifp, enaddr); 549 550 #ifdef EMAC_EVENT_COUNTERS 551 /* 552 * Attach the event counters. 553 */ 554 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 555 NULL, self->dv_xname, "txintr"); 556 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 557 NULL, self->dv_xname, "rxintr"); 558 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 559 NULL, self->dv_xname, "txde"); 560 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 561 NULL, self->dv_xname, "rxde"); 562 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 563 NULL, self->dv_xname, "intr"); 564 565 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 566 NULL, self->dv_xname, "txreap"); 567 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 568 NULL, self->dv_xname, "txsstall"); 569 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 570 NULL, self->dv_xname, "txdstall"); 571 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 572 NULL, self->dv_xname, "txdrop"); 573 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 574 NULL, self->dv_xname, "tu"); 575 #endif /* EMAC_EVENT_COUNTERS */ 576 577 /* 578 * Make sure the interface is shutdown during reboot. 579 */ 580 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 581 if (sc->sc_sdhook == NULL) 582 aprint_error_dev(self, 583 "WARNING: unable to establish shutdown hook\n"); 584 585 return; 586 587 /* 588 * Free any resources we've allocated during the failed attach 589 * attempt. Do this in reverse order and fall through. 590 */ 591 fail_5: 592 for (i = 0; i < EMAC_NRXDESC; i++) { 593 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 594 bus_dmamap_destroy(sc->sc_dmat, 595 sc->sc_rxsoft[i].rxs_dmamap); 596 } 597 fail_4: 598 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 599 if (sc->sc_txsoft[i].txs_dmamap != NULL) 600 bus_dmamap_destroy(sc->sc_dmat, 601 sc->sc_txsoft[i].txs_dmamap); 602 } 603 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 604 fail_3: 605 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 606 fail_2: 607 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 608 sizeof(struct emac_control_data)); 609 fail_1: 610 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 611 fail_0: 612 return; 613 } 614 615 /* 616 * EMAC General interrupt handler 617 */ 618 static int 619 emac_intr(void *arg) 620 { 621 struct emac_softc *sc = arg; 622 uint32_t status; 623 624 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 625 status = EMAC_READ(sc, EMAC_ISR); 626 627 /* Clear the interrupt status bits. */ 628 EMAC_WRITE(sc, EMAC_ISR, status); 629 630 return 1; 631 } 632 633 static void 634 emac_shutdown(void *arg) 635 { 636 struct emac_softc *sc = arg; 637 638 emac_stop(&sc->sc_ethercom.ec_if, 0); 639 } 640 641 642 /* 643 * ifnet interface functions 644 */ 645 646 static void 647 emac_start(struct ifnet *ifp) 648 { 649 struct emac_softc *sc = ifp->if_softc; 650 struct mbuf *m0; 651 struct emac_txsoft *txs; 652 bus_dmamap_t dmamap; 653 int error, firsttx, nexttx, lasttx, ofree, seg; 654 655 lasttx = 0; /* XXX gcc */ 656 657 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 658 return; 659 660 /* 661 * Remember the previous number of free descriptors. 662 */ 663 ofree = sc->sc_txfree; 664 665 /* 666 * Loop through the send queue, setting up transmit descriptors 667 * until we drain the queue, or use up all available transmit 668 * descriptors. 669 */ 670 for (;;) { 671 /* Grab a packet off the queue. */ 672 IFQ_POLL(&ifp->if_snd, m0); 673 if (m0 == NULL) 674 break; 675 676 /* 677 * Get a work queue entry. Reclaim used Tx descriptors if 678 * we are running low. 679 */ 680 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 681 emac_txreap(sc); 682 if (sc->sc_txsfree == 0) { 683 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 684 break; 685 } 686 } 687 688 txs = &sc->sc_txsoft[sc->sc_txsnext]; 689 dmamap = txs->txs_dmamap; 690 691 /* 692 * Load the DMA map. If this fails, the packet either 693 * didn't fit in the alloted number of segments, or we 694 * were short on resources. In this case, we'll copy 695 * and try again. 696 */ 697 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 698 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 699 if (error) { 700 if (error == EFBIG) { 701 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 702 aprint_error_ifnet(ifp, 703 "Tx packet consumes too many " 704 "DMA segments, dropping...\n"); 705 IFQ_DEQUEUE(&ifp->if_snd, m0); 706 m_freem(m0); 707 continue; 708 } 709 /* Short on resources, just stop for now. */ 710 break; 711 } 712 713 /* 714 * Ensure we have enough descriptors free to describe 715 * the packet. 716 */ 717 if (dmamap->dm_nsegs > sc->sc_txfree) { 718 /* 719 * Not enough free descriptors to transmit this 720 * packet. We haven't committed anything yet, 721 * so just unload the DMA map, put the packet 722 * back on the queue, and punt. Notify the upper 723 * layer that there are not more slots left. 724 * 725 */ 726 ifp->if_flags |= IFF_OACTIVE; 727 bus_dmamap_unload(sc->sc_dmat, dmamap); 728 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 729 break; 730 } 731 732 IFQ_DEQUEUE(&ifp->if_snd, m0); 733 734 /* 735 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 736 */ 737 738 /* Sync the DMA map. */ 739 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 740 BUS_DMASYNC_PREWRITE); 741 742 /* 743 * Store a pointer to the packet so that we can free it 744 * later. 745 */ 746 txs->txs_mbuf = m0; 747 txs->txs_firstdesc = sc->sc_txnext; 748 txs->txs_ndesc = dmamap->dm_nsegs; 749 750 /* 751 * Initialize the transmit descriptor. 752 */ 753 firsttx = sc->sc_txnext; 754 for (nexttx = sc->sc_txnext, seg = 0; 755 seg < dmamap->dm_nsegs; 756 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 757 struct mal_descriptor *txdesc = 758 &sc->sc_txdescs[nexttx]; 759 760 /* 761 * If this is the first descriptor we're 762 * enqueueing, don't set the TX_READY bit just 763 * yet. That could cause a race condition. 764 * We'll do it below. 765 */ 766 txdesc->md_data = dmamap->dm_segs[seg].ds_addr; 767 txdesc->md_data_len = dmamap->dm_segs[seg].ds_len; 768 txdesc->md_stat_ctrl = 769 (txdesc->md_stat_ctrl & MAL_TX_WRAP) | 770 (nexttx == firsttx ? 0 : MAL_TX_READY) | 771 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 772 lasttx = nexttx; 773 } 774 775 /* Set the LAST bit on the last segment. */ 776 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 777 778 /* 779 * Set up last segment descriptor to send an interrupt after 780 * that descriptor is transmitted, and bypass existing Tx 781 * descriptor reaping method (for now...). 782 */ 783 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_INTERRUPT; 784 785 786 txs->txs_lastdesc = lasttx; 787 788 /* Sync the descriptors we're using. */ 789 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 790 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 791 792 /* 793 * The entire packet chain is set up. Give the 794 * first descriptor to the chip now. 795 */ 796 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 797 EMAC_CDTXSYNC(sc, firsttx, 1, 798 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 799 /* 800 * Tell the EMAC that a new packet is available. 801 */ 802 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0 | TMR0_TFAE_2); 803 804 /* Advance the tx pointer. */ 805 sc->sc_txfree -= txs->txs_ndesc; 806 sc->sc_txnext = nexttx; 807 808 sc->sc_txsfree--; 809 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 810 811 /* 812 * Pass the packet to any BPF listeners. 813 */ 814 if (ifp->if_bpf) 815 bpf_ops->bpf_mtap(ifp->if_bpf, m0); 816 } 817 818 if (sc->sc_txfree == 0) 819 /* No more slots left; notify upper layer. */ 820 ifp->if_flags |= IFF_OACTIVE; 821 822 if (sc->sc_txfree != ofree) 823 /* Set a watchdog timer in case the chip flakes out. */ 824 ifp->if_timer = 5; 825 } 826 827 static int 828 emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 829 { 830 struct emac_softc *sc = ifp->if_softc; 831 int s, error; 832 833 s = splnet(); 834 835 switch (cmd) { 836 case SIOCSIFMTU: 837 { 838 struct ifreq *ifr = (struct ifreq *)data; 839 int maxmtu; 840 841 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) 842 maxmtu = EMAC_MAX_MTU; 843 else 844 maxmtu = ETHERMTU; 845 846 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > maxmtu) 847 error = EINVAL; 848 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 849 break; 850 else if (ifp->if_flags & IFF_UP) 851 error = emac_init(ifp); 852 else 853 error = 0; 854 break; 855 } 856 857 default: 858 error = ether_ioctl(ifp, cmd, data); 859 if (error == ENETRESET) { 860 /* 861 * Multicast list has changed; set the hardware filter 862 * accordingly. 863 */ 864 if (ifp->if_flags & IFF_RUNNING) 865 error = emac_set_filter(sc); 866 else 867 error = 0; 868 } 869 } 870 871 /* try to get more packets going */ 872 emac_start(ifp); 873 874 splx(s); 875 return error; 876 } 877 878 static int 879 emac_init(struct ifnet *ifp) 880 { 881 struct emac_softc *sc = ifp->if_softc; 882 struct emac_rxsoft *rxs; 883 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 884 int error, i; 885 886 error = 0; 887 888 /* Cancel any pending I/O. */ 889 emac_stop(ifp, 0); 890 891 /* Reset the chip to a known state. */ 892 emac_soft_reset(sc); 893 894 /* 895 * Initialise the transmit descriptor ring. 896 */ 897 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 898 /* set wrap on last descriptor */ 899 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 900 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 901 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 902 sc->sc_txfree = EMAC_NTXDESC; 903 sc->sc_txnext = 0; 904 905 /* 906 * Initialise the transmit job descriptors. 907 */ 908 for (i = 0; i < EMAC_TXQUEUELEN; i++) 909 sc->sc_txsoft[i].txs_mbuf = NULL; 910 sc->sc_txsfree = EMAC_TXQUEUELEN; 911 sc->sc_txsnext = 0; 912 sc->sc_txsdirty = 0; 913 914 /* 915 * Initialise the receiver descriptor and receive job 916 * descriptor rings. 917 */ 918 for (i = 0; i < EMAC_NRXDESC; i++) { 919 rxs = &sc->sc_rxsoft[i]; 920 if (rxs->rxs_mbuf == NULL) { 921 if ((error = emac_add_rxbuf(sc, i)) != 0) { 922 aprint_error_ifnet(ifp, 923 "unable to allocate or map rx buffer %d," 924 " error = %d\n", 925 i, error); 926 /* 927 * XXX Should attempt to run with fewer receive 928 * XXX buffers instead of just failing. 929 */ 930 emac_rxdrain(sc); 931 goto out; 932 } 933 } else 934 EMAC_INIT_RXDESC(sc, i); 935 } 936 sc->sc_rxptr = 0; 937 938 /* 939 * Set the current media. 940 */ 941 if ((error = ether_mediachange(ifp)) != 0) 942 goto out; 943 944 /* 945 * Load the MAC address. 946 */ 947 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 948 EMAC_WRITE(sc, EMAC_IALR, 949 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 950 951 /* Enable the transmit and receive channel on the MAL. */ 952 error = mal_start(sc->sc_instance, 953 EMAC_CDTXADDR(sc, 0), EMAC_CDRXADDR(sc, 0)); 954 if (error) 955 goto out; 956 957 sc->sc_mr1 &= ~MR1_JPSM; 958 if (ifp->if_mtu > ETHERMTU) 959 /* Enable Jumbo Packet Support Mode */ 960 sc->sc_mr1 |= MR1_JPSM; 961 962 /* Set fifos, media modes. */ 963 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 964 965 /* 966 * Enable Individual and (possibly) Broadcast Address modes, 967 * runt packets, and strip padding. 968 */ 969 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | RMR_TFAE_2 | 970 (ifp->if_flags & IFF_PROMISC ? RMR_PME : 0) | 971 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 972 973 /* 974 * Set multicast filter. 975 */ 976 emac_set_filter(sc); 977 978 /* 979 * Set low- and urgent-priority request thresholds. 980 */ 981 EMAC_WRITE(sc, EMAC_TMR1, 982 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 983 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 984 /* 985 * Set Transmit Request Threshold Register. 986 */ 987 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 988 989 /* 990 * Set high and low receive watermarks. 991 */ 992 EMAC_WRITE(sc, EMAC_RWMR, 993 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 994 995 /* 996 * Set frame gap. 997 */ 998 EMAC_WRITE(sc, EMAC_IPGVR, 8); 999 1000 /* 1001 * Set interrupt status enable bits for EMAC. 1002 */ 1003 EMAC_WRITE(sc, EMAC_ISER, 1004 ISR_TXPE | /* TX Parity Error */ 1005 ISR_RXPE | /* RX Parity Error */ 1006 ISR_TXUE | /* TX Underrun Event */ 1007 ISR_RXOE | /* RX Overrun Event */ 1008 ISR_OVR | /* Overrun Error */ 1009 ISR_PP | /* Pause Packet */ 1010 ISR_BP | /* Bad Packet */ 1011 ISR_RP | /* Runt Packet */ 1012 ISR_SE | /* Short Event */ 1013 ISR_ALE | /* Alignment Error */ 1014 ISR_BFCS | /* Bad FCS */ 1015 ISR_PTLE | /* Packet Too Long Error */ 1016 ISR_ORE | /* Out of Range Error */ 1017 ISR_IRE | /* In Range Error */ 1018 ISR_SE0 | /* Signal Quality Error 0 (SQE) */ 1019 ISR_TE0 | /* Transmit Error 0 */ 1020 ISR_MOS | /* MMA Operation Succeeded */ 1021 ISR_MOF); /* MMA Operation Failed */ 1022 1023 /* 1024 * Enable the transmit and receive channel on the EMAC. 1025 */ 1026 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 1027 1028 /* 1029 * Start the one second MII clock. 1030 */ 1031 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1032 1033 /* 1034 * ... all done! 1035 */ 1036 ifp->if_flags |= IFF_RUNNING; 1037 ifp->if_flags &= ~IFF_OACTIVE; 1038 1039 out: 1040 if (error) { 1041 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1042 ifp->if_timer = 0; 1043 aprint_error_ifnet(ifp, "interface not running\n"); 1044 } 1045 return error; 1046 } 1047 1048 static void 1049 emac_stop(struct ifnet *ifp, int disable) 1050 { 1051 struct emac_softc *sc = ifp->if_softc; 1052 struct emac_txsoft *txs; 1053 int i; 1054 1055 /* Stop the one second clock. */ 1056 callout_stop(&sc->sc_callout); 1057 1058 /* Down the MII */ 1059 mii_down(&sc->sc_mii); 1060 1061 /* Disable interrupts. */ 1062 EMAC_WRITE(sc, EMAC_ISER, 0); 1063 1064 /* Disable the receive and transmit channels. */ 1065 mal_stop(sc->sc_instance); 1066 1067 /* Disable the transmit enable and receive MACs. */ 1068 EMAC_WRITE(sc, EMAC_MR0, 1069 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 1070 1071 /* Release any queued transmit buffers. */ 1072 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 1073 txs = &sc->sc_txsoft[i]; 1074 if (txs->txs_mbuf != NULL) { 1075 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1076 m_freem(txs->txs_mbuf); 1077 txs->txs_mbuf = NULL; 1078 } 1079 } 1080 1081 if (disable) 1082 emac_rxdrain(sc); 1083 1084 /* 1085 * Mark the interface down and cancel the watchdog timer. 1086 */ 1087 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1088 ifp->if_timer = 0; 1089 } 1090 1091 static void 1092 emac_watchdog(struct ifnet *ifp) 1093 { 1094 struct emac_softc *sc = ifp->if_softc; 1095 1096 /* 1097 * Since we're not interrupting every packet, sweep 1098 * up before we report an error. 1099 */ 1100 emac_txreap(sc); 1101 1102 if (sc->sc_txfree != EMAC_NTXDESC) { 1103 aprint_error_ifnet(ifp, 1104 "device timeout (txfree %d txsfree %d txnext %d)\n", 1105 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1106 ifp->if_oerrors++; 1107 1108 /* Reset the interface. */ 1109 (void)emac_init(ifp); 1110 } else if (ifp->if_flags & IFF_DEBUG) 1111 aprint_error_ifnet(ifp, "recovered from device timeout\n"); 1112 1113 /* try to get more packets going */ 1114 emac_start(ifp); 1115 } 1116 1117 static int 1118 emac_add_rxbuf(struct emac_softc *sc, int idx) 1119 { 1120 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1121 struct mbuf *m; 1122 int error; 1123 1124 MGETHDR(m, M_DONTWAIT, MT_DATA); 1125 if (m == NULL) 1126 return ENOBUFS; 1127 1128 MCLGET(m, M_DONTWAIT); 1129 if ((m->m_flags & M_EXT) == 0) { 1130 m_freem(m); 1131 return ENOBUFS; 1132 } 1133 1134 if (rxs->rxs_mbuf != NULL) 1135 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1136 1137 rxs->rxs_mbuf = m; 1138 1139 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1140 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1141 if (error) { 1142 aprint_error_dev(sc->sc_dev, 1143 "can't load rx DMA map %d, error = %d\n", idx, error); 1144 panic("emac_add_rxbuf"); /* XXX */ 1145 } 1146 1147 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1148 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1149 1150 EMAC_INIT_RXDESC(sc, idx); 1151 1152 return 0; 1153 } 1154 1155 static void 1156 emac_rxdrain(struct emac_softc *sc) 1157 { 1158 struct emac_rxsoft *rxs; 1159 int i; 1160 1161 for (i = 0; i < EMAC_NRXDESC; i++) { 1162 rxs = &sc->sc_rxsoft[i]; 1163 if (rxs->rxs_mbuf != NULL) { 1164 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1165 m_freem(rxs->rxs_mbuf); 1166 rxs->rxs_mbuf = NULL; 1167 } 1168 } 1169 } 1170 1171 static int 1172 emac_set_filter(struct emac_softc *sc) 1173 { 1174 struct ether_multistep step; 1175 struct ether_multi *enm; 1176 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1177 uint32_t rmr, crc, mask, tmp, reg, gaht[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1178 int regs, cnt = 0, i; 1179 1180 if (sc->sc_htsize == 256) { 1181 reg = EMAC_GAHT256(0); 1182 regs = 8; 1183 } else { 1184 reg = EMAC_GAHT64(0); 1185 regs = 4; 1186 } 1187 mask = (1ULL << (sc->sc_htsize / regs)) - 1; 1188 1189 rmr = EMAC_READ(sc, EMAC_RMR); 1190 rmr &= ~(RMR_PMME | RMR_MAE); 1191 ifp->if_flags &= ~IFF_ALLMULTI; 1192 1193 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1194 while (enm != NULL) { 1195 if (memcmp(enm->enm_addrlo, 1196 enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1197 /* 1198 * We must listen to a range of multicast addresses. 1199 * For now, just accept all multicasts, rather than 1200 * trying to set only those filter bits needed to match 1201 * the range. (At this time, the only use of address 1202 * ranges is for IP multicast routing, for which the 1203 * range is big enough to require all bits set.) 1204 */ 1205 gaht[0] = gaht[1] = gaht[2] = gaht[3] = 1206 gaht[4] = gaht[5] = gaht[6] = gaht[7] = mask; 1207 break; 1208 } 1209 1210 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1211 1212 if (sc->sc_htsize == 256) 1213 EMAC_SET_FILTER256(gaht, crc); 1214 else 1215 EMAC_SET_FILTER(gaht, crc); 1216 1217 ETHER_NEXT_MULTI(step, enm); 1218 cnt++; 1219 } 1220 1221 for (i = 1, tmp = gaht[0]; i < regs; i++) 1222 tmp &= gaht[i]; 1223 if (tmp == mask) { 1224 /* All categories are true. */ 1225 ifp->if_flags |= IFF_ALLMULTI; 1226 rmr |= RMR_PMME; 1227 } else if (cnt != 0) { 1228 /* Some categories are true. */ 1229 for (i = 0; i < regs; i++) 1230 EMAC_WRITE(sc, reg + (i << 2), gaht[i]); 1231 rmr |= RMR_MAE; 1232 } 1233 EMAC_WRITE(sc, EMAC_RMR, rmr); 1234 1235 return 0; 1236 } 1237 1238 /* 1239 * Reap completed Tx descriptors. 1240 */ 1241 static int 1242 emac_txreap(struct emac_softc *sc) 1243 { 1244 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1245 struct emac_txsoft *txs; 1246 int handled, i; 1247 uint32_t txstat; 1248 1249 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1250 handled = 0; 1251 1252 ifp->if_flags &= ~IFF_OACTIVE; 1253 1254 /* 1255 * Go through our Tx list and free mbufs for those 1256 * frames that have been transmitted. 1257 */ 1258 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1259 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1260 txs = &sc->sc_txsoft[i]; 1261 1262 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1263 txs->txs_dmamap->dm_nsegs, 1264 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1265 1266 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1267 if (txstat & MAL_TX_READY) 1268 break; 1269 1270 handled = 1; 1271 1272 /* 1273 * Check for errors and collisions. 1274 */ 1275 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1276 ifp->if_oerrors++; 1277 1278 #ifdef EMAC_EVENT_COUNTERS 1279 if (txstat & EMAC_TXS_UR) 1280 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1281 #endif /* EMAC_EVENT_COUNTERS */ 1282 1283 if (txstat & 1284 (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1285 if (txstat & EMAC_TXS_EC) 1286 ifp->if_collisions += 16; 1287 else if (txstat & EMAC_TXS_MC) 1288 ifp->if_collisions += 2; /* XXX? */ 1289 else if (txstat & EMAC_TXS_SC) 1290 ifp->if_collisions++; 1291 if (txstat & EMAC_TXS_LC) 1292 ifp->if_collisions++; 1293 } else 1294 ifp->if_opackets++; 1295 1296 if (ifp->if_flags & IFF_DEBUG) { 1297 if (txstat & EMAC_TXS_ED) 1298 aprint_error_ifnet(ifp, "excessive deferral\n"); 1299 if (txstat & EMAC_TXS_EC) 1300 aprint_error_ifnet(ifp, 1301 "excessive collisions\n"); 1302 } 1303 1304 sc->sc_txfree += txs->txs_ndesc; 1305 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1306 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1307 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1308 m_freem(txs->txs_mbuf); 1309 txs->txs_mbuf = NULL; 1310 } 1311 1312 /* Update the dirty transmit buffer pointer. */ 1313 sc->sc_txsdirty = i; 1314 1315 /* 1316 * If there are no more pending transmissions, cancel the watchdog 1317 * timer. 1318 */ 1319 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1320 ifp->if_timer = 0; 1321 1322 return handled; 1323 } 1324 1325 1326 /* 1327 * Reset functions 1328 */ 1329 1330 static void 1331 emac_soft_reset(struct emac_softc *sc) 1332 { 1333 uint32_t sdr; 1334 int t = 0; 1335 1336 /* 1337 * The PHY must provide a TX Clk in order perform a soft reset the 1338 * EMAC. If none is present, select the internal clock, 1339 * SDR0_MFR[E0CS,E1CS]. After the soft reset, select the external 1340 * clock. 1341 */ 1342 1343 sdr = mfsdr(DCR_SDR0_MFR); 1344 sdr |= SDR0_MFR_ECS(sc->sc_instance); 1345 mtsdr(DCR_SDR0_MFR, sdr); 1346 1347 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1348 1349 sdr = mfsdr(DCR_SDR0_MFR); 1350 sdr &= ~SDR0_MFR_ECS(sc->sc_instance); 1351 mtsdr(DCR_SDR0_MFR, sdr); 1352 1353 delay(5); 1354 1355 /* wait finish */ 1356 while (EMAC_READ(sc, EMAC_MR0) & MR0_SRST) { 1357 if (++t == 1000000 /* 1sec XXXXX */) { 1358 aprint_error_dev(sc->sc_dev, "Soft Reset failed\n"); 1359 return; 1360 } 1361 delay(1); 1362 } 1363 } 1364 1365 static void 1366 emac_smart_reset(struct emac_softc *sc) 1367 { 1368 uint32_t mr0; 1369 int t = 0; 1370 1371 mr0 = EMAC_READ(sc, EMAC_MR0); 1372 if (mr0 & (MR0_TXE | MR0_RXE)) { 1373 mr0 &= ~(MR0_TXE | MR0_RXE); 1374 EMAC_WRITE(sc, EMAC_MR0, mr0); 1375 1376 /* wait idel state */ 1377 while ((EMAC_READ(sc, EMAC_MR0) & (MR0_TXI | MR0_RXI)) != 1378 (MR0_TXI | MR0_RXI)) { 1379 if (++t == 1000000 /* 1sec XXXXX */) { 1380 aprint_error_dev(sc->sc_dev, 1381 "Smart Reset failed\n"); 1382 return; 1383 } 1384 delay(1); 1385 } 1386 } 1387 } 1388 1389 1390 /* 1391 * MII related functions 1392 */ 1393 1394 static int 1395 emac_mii_readreg(device_t self, int phy, int reg) 1396 { 1397 struct emac_softc *sc = device_private(self); 1398 uint32_t sta_reg; 1399 1400 if (sc->sc_rmii_enable) 1401 sc->sc_rmii_enable(device_parent(self), sc->sc_instance); 1402 1403 /* wait for PHY data transfer to complete */ 1404 if (emac_mii_wait(sc)) 1405 goto fail; 1406 1407 sta_reg = 1408 sc->sc_stacr_read | 1409 (reg << STACR_PRA_SHIFT) | 1410 (phy << STACR_PCDA_SHIFT) | 1411 sc->sc_stacr_bits; 1412 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1413 1414 if (emac_mii_wait(sc)) 1415 goto fail; 1416 sta_reg = EMAC_READ(sc, EMAC_STACR); 1417 1418 if (sc->sc_rmii_disable) 1419 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 1420 1421 if (sta_reg & STACR_PHYE) 1422 return 0; 1423 return sta_reg >> STACR_PHYD_SHIFT; 1424 1425 fail: 1426 if (sc->sc_rmii_disable) 1427 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 1428 return 0; 1429 } 1430 1431 static void 1432 emac_mii_writereg(device_t self, int phy, int reg, int val) 1433 { 1434 struct emac_softc *sc = device_private(self); 1435 uint32_t sta_reg; 1436 1437 if (sc->sc_rmii_enable) 1438 sc->sc_rmii_enable(device_parent(self), sc->sc_instance); 1439 1440 /* wait for PHY data transfer to complete */ 1441 if (emac_mii_wait(sc)) 1442 goto out; 1443 1444 sta_reg = 1445 (val << STACR_PHYD_SHIFT) | 1446 sc->sc_stacr_write | 1447 (reg << STACR_PRA_SHIFT) | 1448 (phy << STACR_PCDA_SHIFT) | 1449 sc->sc_stacr_bits; 1450 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1451 1452 if (emac_mii_wait(sc)) 1453 goto out; 1454 if (EMAC_READ(sc, EMAC_STACR) & STACR_PHYE) 1455 aprint_error_dev(sc->sc_dev, "MII PHY Error\n"); 1456 1457 out: 1458 if (sc->sc_rmii_disable) 1459 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 1460 } 1461 1462 static void 1463 emac_mii_statchg(device_t self) 1464 { 1465 struct emac_softc *sc = device_private(self); 1466 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1467 struct mii_data *mii = &sc->sc_mii; 1468 1469 /* 1470 * MR1 can only be written immediately after a reset... 1471 */ 1472 emac_smart_reset(sc); 1473 1474 sc->sc_mr1 &= ~(MR1_FDE | MR1_ILE | MR1_EIFC | MR1_MF_MASK | MR1_IST); 1475 if (mii->mii_media_active & IFM_FDX) 1476 sc->sc_mr1 |= (MR1_FDE | MR1_EIFC | MR1_IST); 1477 if (mii->mii_media_active & IFM_FLOW) 1478 sc->sc_mr1 |= MR1_EIFC; 1479 if (mii->mii_media_active & IFM_LOOP) 1480 sc->sc_mr1 |= MR1_ILE; 1481 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1482 case IFM_1000_T: 1483 sc->sc_mr1 |= (MR1_MF_1000MBS | MR1_IST); 1484 break; 1485 1486 case IFM_100_TX: 1487 sc->sc_mr1 |= (MR1_MF_100MBS | MR1_IST); 1488 break; 1489 1490 case IFM_10_T: 1491 sc->sc_mr1 |= MR1_MF_10MBS; 1492 break; 1493 1494 case IFM_NONE: 1495 break; 1496 1497 default: 1498 aprint_error_dev(self, "unknown sub-type %d\n", 1499 IFM_SUBTYPE(mii->mii_media_active)); 1500 break; 1501 } 1502 if (sc->sc_rmii_speed) 1503 sc->sc_rmii_speed(device_parent(self), sc->sc_instance, 1504 IFM_SUBTYPE(mii->mii_media_active)); 1505 1506 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 1507 1508 /* Enable TX and RX if already RUNNING */ 1509 if (ifp->if_flags & IFF_RUNNING) 1510 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 1511 } 1512 1513 static uint32_t 1514 emac_mii_wait(struct emac_softc *sc) 1515 { 1516 int i; 1517 uint32_t oc; 1518 1519 /* wait for PHY data transfer to complete */ 1520 i = 0; 1521 oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC; 1522 while ((oc == STACR_OC) != sc->sc_stacr_completed) { 1523 delay(7); 1524 if (i++ > 5) { 1525 aprint_error_dev(sc->sc_dev, "MII timed out\n"); 1526 return -1; 1527 } 1528 oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC; 1529 } 1530 return 0; 1531 } 1532 1533 static void 1534 emac_mii_tick(void *arg) 1535 { 1536 struct emac_softc *sc = arg; 1537 int s; 1538 1539 if (!device_is_active(sc->sc_dev)) 1540 return; 1541 1542 s = splnet(); 1543 mii_tick(&sc->sc_mii); 1544 splx(s); 1545 1546 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1547 } 1548 1549 int 1550 emac_txeob_intr(void *arg) 1551 { 1552 struct emac_softc *sc = arg; 1553 int handled = 0; 1554 1555 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1556 handled |= emac_txreap(sc); 1557 1558 /* try to get more packets going */ 1559 emac_start(&sc->sc_ethercom.ec_if); 1560 1561 return handled; 1562 } 1563 1564 int 1565 emac_rxeob_intr(void *arg) 1566 { 1567 struct emac_softc *sc = arg; 1568 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1569 struct emac_rxsoft *rxs; 1570 struct mbuf *m; 1571 uint32_t rxstat; 1572 int i, len; 1573 1574 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1575 1576 for (i = sc->sc_rxptr; ; i = EMAC_NEXTRX(i)) { 1577 rxs = &sc->sc_rxsoft[i]; 1578 1579 EMAC_CDRXSYNC(sc, i, 1580 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1581 1582 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1583 1584 if (rxstat & MAL_RX_EMPTY) 1585 /* 1586 * We have processed all of the receive buffers. 1587 */ 1588 break; 1589 1590 /* 1591 * If an error occurred, update stats, clear the status 1592 * word, and leave the packet buffer in place. It will 1593 * simply be reused the next time the ring comes around. 1594 */ 1595 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1596 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1597 EMAC_RXS_IRE)) { 1598 #define PRINTERR(bit, str) \ 1599 if (rxstat & (bit)) \ 1600 aprint_error_ifnet(ifp, \ 1601 "receive error: %s\n", str) 1602 ifp->if_ierrors++; 1603 PRINTERR(EMAC_RXS_OE, "overrun error"); 1604 PRINTERR(EMAC_RXS_BP, "bad packet"); 1605 PRINTERR(EMAC_RXS_RP, "runt packet"); 1606 PRINTERR(EMAC_RXS_SE, "short event"); 1607 PRINTERR(EMAC_RXS_AE, "alignment error"); 1608 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1609 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1610 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1611 PRINTERR(EMAC_RXS_IRE, "in range error"); 1612 #undef PRINTERR 1613 EMAC_INIT_RXDESC(sc, i); 1614 continue; 1615 } 1616 1617 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1618 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1619 1620 /* 1621 * No errors; receive the packet. Note, the 405GP emac 1622 * includes the CRC with every packet. 1623 */ 1624 len = sc->sc_rxdescs[i].md_data_len - ETHER_CRC_LEN; 1625 1626 /* 1627 * If the packet is small enough to fit in a 1628 * single header mbuf, allocate one and copy 1629 * the data into it. This greatly reduces 1630 * memory consumption when we receive lots 1631 * of small packets. 1632 * 1633 * Otherwise, we add a new buffer to the receive 1634 * chain. If this fails, we drop the packet and 1635 * recycle the old buffer. 1636 */ 1637 if (emac_copy_small != 0 && len <= MHLEN) { 1638 MGETHDR(m, M_DONTWAIT, MT_DATA); 1639 if (m == NULL) 1640 goto dropit; 1641 memcpy(mtod(m, void *), 1642 mtod(rxs->rxs_mbuf, void *), len); 1643 EMAC_INIT_RXDESC(sc, i); 1644 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1645 rxs->rxs_dmamap->dm_mapsize, 1646 BUS_DMASYNC_PREREAD); 1647 } else { 1648 m = rxs->rxs_mbuf; 1649 if (emac_add_rxbuf(sc, i) != 0) { 1650 dropit: 1651 ifp->if_ierrors++; 1652 EMAC_INIT_RXDESC(sc, i); 1653 bus_dmamap_sync(sc->sc_dmat, 1654 rxs->rxs_dmamap, 0, 1655 rxs->rxs_dmamap->dm_mapsize, 1656 BUS_DMASYNC_PREREAD); 1657 continue; 1658 } 1659 } 1660 1661 ifp->if_ipackets++; 1662 m->m_pkthdr.rcvif = ifp; 1663 m->m_pkthdr.len = m->m_len = len; 1664 1665 /* 1666 * Pass this up to any BPF listeners, but only 1667 * pass if up the stack if it's for us. 1668 */ 1669 if (ifp->if_bpf) 1670 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1671 1672 /* Pass it on. */ 1673 (*ifp->if_input)(ifp, m); 1674 } 1675 1676 /* Update the receive pointer. */ 1677 sc->sc_rxptr = i; 1678 1679 return 1; 1680 } 1681 1682 int 1683 emac_txde_intr(void *arg) 1684 { 1685 struct emac_softc *sc = arg; 1686 1687 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1688 aprint_error_dev(sc->sc_dev, "emac_txde_intr\n"); 1689 return 1; 1690 } 1691 1692 int 1693 emac_rxde_intr(void *arg) 1694 { 1695 struct emac_softc *sc = arg; 1696 int i; 1697 1698 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1699 aprint_error_dev(sc->sc_dev, "emac_rxde_intr\n"); 1700 /* 1701 * XXX! 1702 * This is a bit drastic; we just drop all descriptors that aren't 1703 * "clean". We should probably send any that are up the stack. 1704 */ 1705 for (i = 0; i < EMAC_NRXDESC; i++) { 1706 EMAC_CDRXSYNC(sc, i, 1707 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1708 1709 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) 1710 EMAC_INIT_RXDESC(sc, i); 1711 } 1712 1713 return 1; 1714 } 1715