xref: /netbsd-src/sys/arch/powerpc/ibm4xx/dev/gpiic_opb.c (revision bdc22b2e01993381dcefeff2bc9b56ca75a4235c)
1 /*	$NetBSD: gpiic_opb.c,v 1.9 2011/06/18 06:41:42 matt Exp $	*/
2 
3 /*
4  * Copyright 2002, 2003 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Steve C. Woodford for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *      This product includes software developed for the NetBSD Project by
20  *      Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #include "locators.h"
39 
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/device.h>
43 #include <sys/errno.h>
44 #include <sys/mutex.h>
45 #include <sys/cpu.h>
46 
47 #include <dev/i2c/i2cvar.h>
48 #include <dev/i2c/i2c_bitbang.h>
49 
50 #include <powerpc/ibm4xx/cpu.h>
51 #include <powerpc/ibm4xx/dev/opbvar.h>
52 #include <powerpc/ibm4xx/dev/gpiicreg.h>
53 
54 struct gpiic_softc {
55 	device_t sc_dev;
56 	bus_space_tag_t sc_bust;
57 	bus_space_handle_t sc_bush;
58 	uint8_t sc_txen;
59 	uint8_t sc_tx;
60 	struct i2c_controller sc_i2c;
61 	struct i2c_bitbang_ops sc_bops;
62 	kmutex_t sc_buslock;
63 };
64 
65 static int	gpiic_match(device_t, cfdata_t, void *);
66 static void	gpiic_attach(device_t, device_t, void *);
67 
68 CFATTACH_DECL_NEW(gpiic, sizeof(struct gpiic_softc),
69     gpiic_match, gpiic_attach, NULL, NULL);
70 
71 static int	gpiic_acquire_bus(void *, int);
72 static void	gpiic_release_bus(void *, int);
73 static int	gpiic_send_start(void *, int);
74 static int	gpiic_send_stop(void *, int);
75 static int	gpiic_initiate_xfer(void *, i2c_addr_t, int);
76 static int	gpiic_read_byte(void *, uint8_t *, int);
77 static int	gpiic_write_byte(void *, uint8_t, int);
78 static void	gpiic_set_dir(void *, uint32_t);
79 static void	gpiic_set_bits(void *, uint32_t);
80 static uint32_t	gpiic_read_bits(void *);
81 
82 static int
83 gpiic_match(device_t parent, cfdata_t cf, void *args)
84 {
85 	struct opb_attach_args * const oaa = args;
86 
87 	if (strcmp(oaa->opb_name, cf->cf_name) != 0)
88 		return 0;
89 
90 	return (1);
91 }
92 
93 static void
94 gpiic_attach(device_t parent, device_t self, void *args)
95 {
96 	struct gpiic_softc * const sc = device_private(self);
97 	struct opb_attach_args * const oaa = args;
98 	struct i2cbus_attach_args iba;
99 
100 	aprint_naive(": IIC controller\n");
101 	aprint_normal(": On-Chip IIC controller\n");
102 
103 	sc->sc_dev = self;
104 	sc->sc_bust = oaa->opb_bt;
105 
106 	bus_space_map(sc->sc_bust, oaa->opb_addr, IIC_NREG, 0, &sc->sc_bush);
107 
108 	mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE);
109 
110 	sc->sc_txen = 0;
111 	sc->sc_tx = IIC_DIRECTCNTL_SCC | IIC_DIRECTCNTL_SDAC;
112 	sc->sc_i2c.ic_cookie = sc;
113 	sc->sc_i2c.ic_acquire_bus = gpiic_acquire_bus;
114 	sc->sc_i2c.ic_release_bus = gpiic_release_bus;
115 	sc->sc_i2c.ic_exec = NULL;
116 	sc->sc_i2c.ic_send_start = gpiic_send_start;
117 	sc->sc_i2c.ic_send_stop = gpiic_send_stop;
118 	sc->sc_i2c.ic_initiate_xfer = gpiic_initiate_xfer;
119 	sc->sc_i2c.ic_read_byte = gpiic_read_byte;
120 	sc->sc_i2c.ic_write_byte = gpiic_write_byte;
121 
122 	sc->sc_bops.ibo_set_dir = gpiic_set_dir;
123 	sc->sc_bops.ibo_set_bits = gpiic_set_bits;
124 	sc->sc_bops.ibo_read_bits = gpiic_read_bits;
125 	sc->sc_bops.ibo_bits[I2C_BIT_SDA] = IIC_DIRECTCNTL_SDAC;
126 	sc->sc_bops.ibo_bits[I2C_BIT_SCL] = IIC_DIRECTCNTL_SCC;
127 	sc->sc_bops.ibo_bits[I2C_BIT_OUTPUT] = 1;
128 	sc->sc_bops.ibo_bits[I2C_BIT_INPUT] = 0;
129 
130 	/*
131 	 * Put the controller into Soft Reset. This allows us to
132 	 * manually bit-bang the I2C clock/data lines.
133 	 */
134 	bus_space_write_1(sc->sc_bust, sc->sc_bush, IIC_XTCNTLSS,
135 	    IIC_XTCNTLSS_SRST);
136 	delay(10);
137 	bus_space_write_1(sc->sc_bust, sc->sc_bush, IIC_DIRECTCNTL,
138 	    IIC_DIRECTCNTL_SCC | IIC_DIRECTCNTL_SDAC);
139 
140 	memset(&iba, 0, sizeof(iba));
141 	iba.iba_tag = &sc->sc_i2c;
142 	(void) config_found_ia(self, "i2cbus", &iba, iicbus_print);
143 }
144 
145 static int
146 gpiic_acquire_bus(void *arg, int flags)
147 {
148 	struct gpiic_softc * const sc = arg;
149 
150 	if (flags & I2C_F_POLL)
151 		return (0);
152 
153 	mutex_enter(&sc->sc_buslock);
154 	return (0);
155 }
156 
157 static void
158 gpiic_release_bus(void *arg, int flags)
159 {
160 	struct gpiic_softc * const sc = arg;
161 
162 	if (flags & I2C_F_POLL)
163 		return;
164 
165 	mutex_exit(&sc->sc_buslock);
166 }
167 
168 static int
169 gpiic_send_start(void *arg, int flags)
170 {
171 	struct gpiic_softc * const sc = arg;
172 
173 	return (i2c_bitbang_send_start(sc, flags, &sc->sc_bops));
174 }
175 
176 static int
177 gpiic_send_stop(void *arg, int flags)
178 {
179 	struct gpiic_softc * const sc = arg;
180 
181 	return (i2c_bitbang_send_stop(sc, flags, &sc->sc_bops));
182 }
183 
184 static int
185 gpiic_initiate_xfer(void *arg, i2c_addr_t addr, int flags)
186 {
187 	struct gpiic_softc * const sc = arg;
188 
189 	return (i2c_bitbang_initiate_xfer(sc, addr, flags, &sc->sc_bops));
190 }
191 
192 static int
193 gpiic_read_byte(void *arg, uint8_t *vp, int flags)
194 {
195 	struct gpiic_softc * const sc = arg;
196 
197 	return (i2c_bitbang_read_byte(sc, vp, flags, &sc->sc_bops));
198 }
199 
200 static int
201 gpiic_write_byte(void *arg, uint8_t v, int flags)
202 {
203 	struct gpiic_softc * const sc = arg;
204 
205 	return (i2c_bitbang_write_byte(sc, v, flags, &sc->sc_bops));
206 }
207 
208 static void
209 gpiic_set_dir(void *arg, uint32_t bits)
210 {
211 	struct gpiic_softc * const sc = arg;
212 	uint8_t tx, txen;
213 
214 	txen = (uint8_t)bits;
215 	if (sc->sc_txen == txen)
216 		return;
217 
218 	sc->sc_txen = txen;
219 
220 	tx = sc->sc_tx;
221 	if (sc->sc_txen == 0)
222 		tx |= IIC_DIRECTCNTL_SDAC;
223 	bus_space_write_1(sc->sc_bust, sc->sc_bush, IIC_DIRECTCNTL, tx);
224 }
225 
226 static void
227 gpiic_set_bits(void *arg, uint32_t bits)
228 {
229 	struct gpiic_softc * const sc = arg;
230 
231 	sc->sc_tx = (uint8_t)bits;
232 	if (sc->sc_txen == 0)
233 		bits |= IIC_DIRECTCNTL_SDAC;
234 
235 	bus_space_write_1(sc->sc_bust, sc->sc_bush, IIC_DIRECTCNTL, bits);
236 }
237 
238 static uint32_t
239 gpiic_read_bits(void *arg)
240 {
241 	struct gpiic_softc * const sc = arg;
242 	uint8_t rv;
243 
244 	rv = bus_space_read_1(sc->sc_bust, sc->sc_bush, IIC_DIRECTCNTL) << 2;
245 	rv &= (IIC_DIRECTCNTL_SCC | IIC_DIRECTCNTL_SDAC);
246 
247 	return ((uint32_t)rv);
248 }
249