1 /* $NetBSD: cpu.c,v 1.26 2007/11/19 02:18:33 ad Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.26 2007/11/19 02:18:33 ad Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/evcnt.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <prop/proplib.h> 49 50 #include <machine/cpu.h> 51 #include <powerpc/ibm4xx/dev/plbvar.h> 52 53 struct cputab { 54 u_int version; 55 u_int mask; 56 const char *name; 57 }; 58 static struct cputab models[] = { 59 { PVR_401A1, 0xffff0000, "401A1" }, 60 { PVR_401B2, 0xffff0000, "401B21" }, 61 { PVR_401C2, 0xffff0000, "401C2" }, 62 { PVR_401D2, 0xffff0000, "401D2" }, 63 { PVR_401E2, 0xffff0000, "401E2" }, 64 { PVR_401F2, 0xffff0000, "401F2" }, 65 { PVR_401G2, 0xffff0000, "401G2" }, 66 { PVR_403, 0xffff0000, "403" }, 67 { PVR_405GP, 0xffff0000, "405GP" }, 68 { PVR_405GPR, 0xffff0000, "405GPr" }, 69 { PVR_405D5X1, 0xfffff000, "Xilinx Virtex II Pro" }, 70 { PVR_405D5X2, 0xfffff000, "Xilinx Virtex 4 FX" }, 71 { 0, 0, NULL } 72 }; 73 74 static int cpumatch(struct device *, struct cfdata *, void *); 75 static void cpuattach(struct device *, struct device *, void *); 76 77 CFATTACH_DECL(cpu, sizeof(struct device), 78 cpumatch, cpuattach, NULL, NULL); 79 80 int ncpus; 81 82 struct cpu_info cpu_info[1] = { 83 { 84 /* XXX add more ci_ev_* as we teach 4xx about them */ 85 .ci_ev_clock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 86 NULL, "cpu0", "clock"), 87 .ci_ev_statclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 88 NULL, "cpu0", "stat clock"), 89 .ci_ev_softclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 90 NULL, "cpu0", "soft clock"), 91 .ci_ev_softnet = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 92 NULL, "cpu0", "soft net"), 93 .ci_ev_softserial = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 94 NULL, "cpu0", "soft serial"), 95 .ci_curlwp = &lwp0, 96 } 97 }; 98 99 char cpu_model[80]; 100 101 int cpufound = 0; 102 103 static int 104 cpumatch(struct device *parent, struct cfdata *cf, void *aux) 105 { 106 struct plb_attach_args *paa = aux; 107 108 /* make sure that we're looking for a CPU */ 109 if (strcmp(paa->plb_name, cf->cf_name) != 0) 110 return (0); 111 112 return !cpufound; 113 } 114 115 static void 116 cpuattach(struct device *parent, struct device *self, void *aux) 117 { 118 struct cputab *cp = models; 119 u_int pvr; 120 u_int processor_freq; 121 prop_number_t freq; 122 123 freq = prop_dictionary_get(board_properties, "processor-frequency"); 124 KASSERT(freq != NULL); 125 processor_freq = (unsigned int) prop_number_integer_value(freq); 126 127 cpufound++; 128 ncpus++; 129 130 pvr = mfpvr(); 131 while (cp->name) { 132 if ((pvr & cp->mask) == cp->version) 133 break; 134 cp++; 135 } 136 if (cp->name) 137 strcpy(cpu_model, cp->name); 138 else 139 sprintf(cpu_model, "Version 0x%x", pvr); 140 141 printf(": %dMHz %s (PVR 0x%x)\n", processor_freq / 1000 / 1000, 142 cp->name ? cp->name : "unknown model", pvr); 143 144 cpu_probe_cache(); 145 146 /* We would crash later on anyway so just make the reason obvious */ 147 if (curcpu()->ci_ci.icache_size == 0 && 148 curcpu()->ci_ci.dcache_size == 0) 149 panic("%s could not detect cache size", device_xname(self)); 150 151 printf("%s: Instruction cache size %d line size %d\n", 152 device_xname(self), 153 curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 154 printf("%s: Data cache size %d line size %d\n", 155 device_xname(self), 156 curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 157 } 158 159 /* 160 * This routine must be explicitly called to initialize the 161 * CPU cache information so cache flushe and memcpy operation 162 * work. 163 */ 164 void 165 cpu_probe_cache() 166 { 167 /* 168 * First we need to identify the CPU and determine the 169 * cache line size, or things like memset/memcpy may lose 170 * badly. 171 */ 172 switch (mfpvr() & 0xffff0000) { 173 case PVR_401A1: 174 curcpu()->ci_ci.dcache_size = 1024; 175 curcpu()->ci_ci.dcache_line_size = 16; 176 curcpu()->ci_ci.icache_size = 2848; 177 curcpu()->ci_ci.icache_line_size = 16; 178 break; 179 case PVR_401B2: 180 curcpu()->ci_ci.dcache_size = 8192; 181 curcpu()->ci_ci.dcache_line_size = 16; 182 curcpu()->ci_ci.icache_size = 16384; 183 curcpu()->ci_ci.icache_line_size = 16; 184 break; 185 case PVR_401C2: 186 curcpu()->ci_ci.dcache_size = 8192; 187 curcpu()->ci_ci.dcache_line_size = 16; 188 curcpu()->ci_ci.icache_size = 0; 189 curcpu()->ci_ci.icache_line_size = 16; 190 break; 191 case PVR_401D2: 192 curcpu()->ci_ci.dcache_size = 2848; 193 curcpu()->ci_ci.dcache_line_size = 16; 194 curcpu()->ci_ci.icache_size = 4096; 195 curcpu()->ci_ci.icache_line_size = 16; 196 break; 197 case PVR_401E2: 198 curcpu()->ci_ci.dcache_size = 0; 199 curcpu()->ci_ci.dcache_line_size = 16; 200 curcpu()->ci_ci.icache_size = 0; 201 curcpu()->ci_ci.icache_line_size = 16; 202 break; 203 case PVR_401F2: 204 curcpu()->ci_ci.dcache_size = 2048; 205 curcpu()->ci_ci.dcache_line_size = 16; 206 curcpu()->ci_ci.icache_size = 2848; 207 curcpu()->ci_ci.icache_line_size = 16; 208 break; 209 case PVR_401G2: 210 curcpu()->ci_ci.dcache_size = 2848; 211 curcpu()->ci_ci.dcache_line_size = 16; 212 curcpu()->ci_ci.icache_size = 8192; 213 curcpu()->ci_ci.icache_line_size = 16; 214 break; 215 case PVR_403: 216 curcpu()->ci_ci.dcache_size = 8192; 217 curcpu()->ci_ci.dcache_line_size = 16; 218 curcpu()->ci_ci.icache_size = 16384; 219 curcpu()->ci_ci.icache_line_size = 16; 220 break; 221 case PVR_405GP: 222 curcpu()->ci_ci.dcache_size = 8192; 223 curcpu()->ci_ci.dcache_line_size = 32; 224 curcpu()->ci_ci.icache_size = 8192; 225 curcpu()->ci_ci.icache_line_size = 32; 226 break; 227 case PVR_405GPR: 228 case PVR_405D5X1: 229 case PVR_405D5X2: 230 curcpu()->ci_ci.dcache_size = 16384; 231 curcpu()->ci_ci.dcache_line_size = 32; 232 curcpu()->ci_ci.icache_size = 16384; 233 curcpu()->ci_ci.icache_line_size = 32; 234 break; 235 default: 236 /* 237 * Unknown CPU type. For safety we'll specify a 238 * cache with a 4-byte line size. That way cache 239 * flush routines won't miss any lines. 240 */ 241 curcpu()->ci_ci.dcache_line_size = 4; 242 curcpu()->ci_ci.icache_line_size = 4; 243 break; 244 } 245 246 } 247 248 /* 249 * These small routines may have to be replaced, 250 * if/when we support processors other that the 604. 251 */ 252 253 void 254 dcache_flush_page(vaddr_t va) 255 { 256 int i; 257 258 if (curcpu()->ci_ci.dcache_line_size) 259 for (i = 0; i < PAGE_SIZE; 260 i += curcpu()->ci_ci.dcache_line_size) 261 __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 262 __asm volatile("sync;isync" : : ); 263 } 264 265 void 266 icache_flush_page(vaddr_t va) 267 { 268 int i; 269 270 if (curcpu()->ci_ci.icache_line_size) 271 for (i = 0; i < PAGE_SIZE; 272 i += curcpu()->ci_ci.icache_line_size) 273 __asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 274 __asm volatile("sync;isync" : : ); 275 } 276 277 void 278 dcache_flush(vaddr_t va, vsize_t len) 279 { 280 int i; 281 282 if (len == 0) 283 return; 284 285 /* Make sure we flush all cache lines */ 286 len += va & (curcpu()->ci_ci.dcache_line_size-1); 287 if (curcpu()->ci_ci.dcache_line_size) 288 for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 289 __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 290 __asm volatile("sync;isync" : : ); 291 } 292 293 void 294 icache_flush(vaddr_t va, vsize_t len) 295 { 296 int i; 297 298 if (len == 0) 299 return; 300 301 /* Make sure we flush all cache lines */ 302 len += va & (curcpu()->ci_ci.icache_line_size-1); 303 if (curcpu()->ci_ci.icache_line_size) 304 for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 305 __asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 306 __asm volatile("sync;isync" : : ); 307 } 308