1 /* $NetBSD: fpu_explode.c,v 1.3 2003/08/07 16:29:18 agc Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * FPU subroutines: `explode' the machine's `packed binary' format numbers 45 * into our internal format. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.3 2003/08/07 16:29:18 agc Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 54 #include <machine/ieee.h> 55 #include <powerpc/instr.h> 56 #include <machine/reg.h> 57 #include <machine/fpu.h> 58 59 #include <powerpc/fpu/fpu_arith.h> 60 #include <powerpc/fpu/fpu_emu.h> 61 #include <powerpc/fpu/fpu_extern.h> 62 63 /* 64 * N.B.: in all of the following, we assume the FP format is 65 * 66 * --------------------------- 67 * | s | exponent | fraction | 68 * --------------------------- 69 * 70 * (which represents -1**s * 1.fraction * 2**exponent), so that the 71 * sign bit is way at the top (bit 31), the exponent is next, and 72 * then the remaining bits mark the fraction. A zero exponent means 73 * zero or denormalized (0.fraction rather than 1.fraction), and the 74 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 75 * 76 * Since the sign bit is always the topmost bit---this holds even for 77 * integers---we set that outside all the *tof functions. Each function 78 * returns the class code for the new number (but note that we use 79 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 80 */ 81 82 /* 83 * int -> fpn. 84 */ 85 int 86 fpu_itof(struct fpn *fp, u_int i) 87 { 88 89 if (i == 0) 90 return (FPC_ZERO); 91 /* 92 * The value FP_1 represents 2^FP_LG, so set the exponent 93 * there and let normalization fix it up. Convert negative 94 * numbers to sign-and-magnitude. Note that this relies on 95 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 96 */ 97 fp->fp_exp = FP_LG; 98 fp->fp_mant[0] = (int)i < 0 ? -i : i; 99 fp->fp_mant[1] = 0; 100 fp->fp_mant[2] = 0; 101 fp->fp_mant[3] = 0; 102 fpu_norm(fp); 103 return (FPC_NUM); 104 } 105 106 /* 107 * 64-bit int -> fpn. 108 */ 109 int 110 fpu_xtof(struct fpn *fp, u_int64_t i) 111 { 112 113 if (i == 0) 114 return (FPC_ZERO); 115 /* 116 * The value FP_1 represents 2^FP_LG, so set the exponent 117 * there and let normalization fix it up. Convert negative 118 * numbers to sign-and-magnitude. Note that this relies on 119 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 120 */ 121 fp->fp_exp = FP_LG2; 122 *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i; 123 fp->fp_mant[2] = 0; 124 fp->fp_mant[3] = 0; 125 fpu_norm(fp); 126 return (FPC_NUM); 127 } 128 129 #define mask(nbits) ((1L << (nbits)) - 1) 130 131 /* 132 * All external floating formats convert to internal in the same manner, 133 * as defined here. Note that only normals get an implied 1.0 inserted. 134 */ 135 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 136 if (exp == 0) { \ 137 if (allfrac == 0) \ 138 return (FPC_ZERO); \ 139 fp->fp_exp = 1 - expbias; \ 140 fp->fp_mant[0] = f0; \ 141 fp->fp_mant[1] = f1; \ 142 fp->fp_mant[2] = f2; \ 143 fp->fp_mant[3] = f3; \ 144 fpu_norm(fp); \ 145 return (FPC_NUM); \ 146 } \ 147 if (exp == (2 * expbias + 1)) { \ 148 if (allfrac == 0) \ 149 return (FPC_INF); \ 150 fp->fp_mant[0] = f0; \ 151 fp->fp_mant[1] = f1; \ 152 fp->fp_mant[2] = f2; \ 153 fp->fp_mant[3] = f3; \ 154 return (FPC_QNAN); \ 155 } \ 156 fp->fp_exp = exp - expbias; \ 157 fp->fp_mant[0] = FP_1 | f0; \ 158 fp->fp_mant[1] = f1; \ 159 fp->fp_mant[2] = f2; \ 160 fp->fp_mant[3] = f3; \ 161 return (FPC_NUM) 162 163 /* 164 * 32-bit single precision -> fpn. 165 * We assume a single occupies at most (64-FP_LG) bits in the internal 166 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 167 */ 168 int 169 fpu_stof(struct fpn *fp, u_int i) 170 { 171 int exp; 172 u_int frac, f0, f1; 173 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 174 175 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 176 frac = i & mask(SNG_FRACBITS); 177 f0 = frac >> SNG_SHIFT; 178 f1 = frac << (32 - SNG_SHIFT); 179 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 180 } 181 182 /* 183 * 64-bit double -> fpn. 184 * We assume this uses at most (96-FP_LG) bits. 185 */ 186 int 187 fpu_dtof(struct fpn *fp, u_int i, u_int j) 188 { 189 int exp; 190 u_int frac, f0, f1, f2; 191 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 192 193 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 194 frac = i & mask(DBL_FRACBITS - 32); 195 f0 = frac >> DBL_SHIFT; 196 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 197 f2 = j << (32 - DBL_SHIFT); 198 frac |= j; 199 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 200 } 201 202 /* 203 * 128-bit extended -> fpn. 204 */ 205 int 206 fpu_qtof(struct fpn *fp, u_int i, u_int j, u_int k, u_int l) 207 { 208 int exp; 209 u_int frac, f0, f1, f2, f3; 210 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */ 211 212 /* 213 * Note that ext and fpn `line up', hence no shifting needed. 214 */ 215 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 216 frac = i & mask(EXT_FRACBITS - 3 * 32); 217 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT)); 218 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT)); 219 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT)); 220 f3 = l << EXT_SHIFT; 221 frac |= j | k | l; 222 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3); 223 } 224 225 /* 226 * Explode the contents of a register / regpair / regquad. 227 * If the input is a signalling NaN, an NV (invalid) exception 228 * will be set. (Note that nothing but NV can occur until ALU 229 * operations are performed.) 230 */ 231 void 232 fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg) 233 { 234 u_int s, *space; 235 u_int64_t l, *xspace; 236 237 xspace = (u_int64_t *)&fe->fe_fpstate->fpreg[reg]; 238 l = xspace[0]; 239 space = (u_int *)&fe->fe_fpstate->fpreg[reg]; 240 s = space[0]; 241 fp->fp_sign = s >> 31; 242 fp->fp_sticky = 0; 243 switch (type) { 244 245 case FTYPE_LNG: 246 s = fpu_xtof(fp, l); 247 break; 248 249 case FTYPE_INT: 250 s = fpu_itof(fp, space[1]); 251 break; 252 253 case FTYPE_SNG: 254 s = fpu_stof(fp, s); 255 break; 256 257 case FTYPE_DBL: 258 s = fpu_dtof(fp, s, space[1]); 259 break; 260 261 case FTYPE_EXT: 262 s = fpu_qtof(fp, s, space[1], space[2], space[3]); 263 break; 264 265 default: 266 panic("fpu_explode"); 267 } 268 269 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 270 /* 271 * Input is a signalling NaN. All operations that return 272 * an input NaN operand put it through a ``NaN conversion'', 273 * which basically just means ``turn on the quiet bit''. 274 * We do this here so that all NaNs internally look quiet 275 * (we can tell signalling ones by their class). 276 */ 277 fp->fp_mant[0] |= FP_QUIETBIT; 278 fe->fe_cx = FPSCR_VXSNAN; /* assert invalid operand */ 279 s = FPC_SNAN; 280 } 281 fp->fp_class = s; 282 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' : 283 ((type == FTYPE_INT) ? 'i' : 284 ((type == FTYPE_SNG) ? 's' : 285 ((type == FTYPE_DBL) ? 'd' : 286 ((type == FTYPE_EXT) ? 'q' : '?')))), 287 reg)); 288 DUMPFPN(FPE_REG, fp); 289 DPRINTF(FPE_REG, ("\n")); 290 } 291