1 /* $NetBSD: fpu_explode.c,v 1.14 2022/09/07 06:51:58 rin Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * FPU subroutines: `explode' the machine's `packed binary' format numbers 45 * into our internal format. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.14 2022/09/07 06:51:58 rin Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 54 #include <powerpc/instr.h> 55 #include <machine/fpu.h> 56 #include <machine/ieee.h> 57 #include <machine/reg.h> 58 59 #include <powerpc/fpu/fpu_arith.h> 60 #include <powerpc/fpu/fpu_emu.h> 61 #include <powerpc/fpu/fpu_extern.h> 62 63 static int fpu_itof(struct fpn *, u_int); 64 static int fpu_xtof(struct fpn *, uint64_t); 65 static int fpu_stof(struct fpn *, u_int); 66 static int fpu_dtof(struct fpn *, u_int, u_int); 67 68 /* 69 * N.B.: in all of the following, we assume the FP format is 70 * 71 * --------------------------- 72 * | s | exponent | fraction | 73 * --------------------------- 74 * 75 * (which represents -1**s * 1.fraction * 2**exponent), so that the 76 * sign bit is way at the top (bit 31), the exponent is next, and 77 * then the remaining bits mark the fraction. A zero exponent means 78 * zero or denormalized (0.fraction rather than 1.fraction), and the 79 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 80 * 81 * Since the sign bit is always the topmost bit---this holds even for 82 * integers---we set that outside all the *tof functions. Each function 83 * returns the class code for the new number (but note that we use 84 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 85 */ 86 87 /* 88 * int -> fpn. 89 */ 90 static int 91 fpu_itof(struct fpn *fp, u_int lo) 92 { 93 94 if (lo == 0) 95 return (FPC_ZERO); 96 /* 97 * The value FP_1 represents 2^FP_LG, so set the exponent 98 * there and let normalization fix it up. Convert negative 99 * numbers to sign-and-magnitude. Note that this relies on 100 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 101 */ 102 fp->fp_exp = FP_LG; 103 fp->fp_mant[0] = (int)lo < 0 ? -lo : lo; 104 fp->fp_mant[1] = 0; 105 fp->fp_mant[2] = 0; 106 fp->fp_mant[3] = 0; 107 fpu_norm(fp); 108 return (FPC_NUM); 109 } 110 111 /* 112 * 64-bit int -> fpn. 113 */ 114 static int 115 fpu_xtof(struct fpn *fp, uint64_t i) 116 { 117 118 if (i == 0) 119 return (FPC_ZERO); 120 /* 121 * The value FP_1 represents 2^FP_LG, so set the exponent 122 * there and let normalization fix it up. Convert negative 123 * numbers to sign-and-magnitude. Note that this relies on 124 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 125 */ 126 fp->fp_exp = FP_LG2; 127 *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i; 128 fp->fp_mant[2] = 0; 129 fp->fp_mant[3] = 0; 130 fpu_norm(fp); 131 return (FPC_NUM); 132 } 133 134 #define mask(nbits) ((1L << (nbits)) - 1) 135 136 /* 137 * All external floating formats convert to internal in the same manner, 138 * as defined here. Note that only normals get an implied 1.0 inserted. 139 */ 140 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 141 if (exp == 0) { \ 142 if (allfrac == 0) \ 143 return (FPC_ZERO); \ 144 fp->fp_exp = 1 - expbias; \ 145 fp->fp_mant[0] = f0; \ 146 fp->fp_mant[1] = f1; \ 147 fp->fp_mant[2] = f2; \ 148 fp->fp_mant[3] = f3; \ 149 fpu_norm(fp); \ 150 return (FPC_NUM); \ 151 } \ 152 if (exp == (2 * expbias + 1)) { \ 153 if (allfrac == 0) \ 154 return (FPC_INF); \ 155 fp->fp_mant[0] = f0; \ 156 fp->fp_mant[1] = f1; \ 157 fp->fp_mant[2] = f2; \ 158 fp->fp_mant[3] = f3; \ 159 return (FPC_QNAN); \ 160 } \ 161 fp->fp_exp = exp - expbias; \ 162 fp->fp_mant[0] = FP_1 | f0; \ 163 fp->fp_mant[1] = f1; \ 164 fp->fp_mant[2] = f2; \ 165 fp->fp_mant[3] = f3; \ 166 return (FPC_NUM) 167 168 /* 169 * 32-bit single precision -> fpn. 170 * We assume a single occupies at most (64-FP_LG) bits in the internal 171 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 172 */ 173 static int 174 fpu_stof(struct fpn *fp, u_int hi) 175 { 176 int exp; 177 u_int frac, f0, f1; 178 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 179 180 exp = (hi >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 181 frac = hi & mask(SNG_FRACBITS); 182 f0 = frac >> SNG_SHIFT; 183 f1 = frac << (32 - SNG_SHIFT); 184 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 185 } 186 187 /* 188 * 64-bit double -> fpn. 189 * We assume this uses at most (96-FP_LG) bits. 190 */ 191 static int 192 fpu_dtof(struct fpn *fp, u_int hi, u_int lo) 193 { 194 int exp; 195 u_int frac, f0, f1, f2; 196 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 197 198 exp = (hi >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 199 frac = hi & mask(DBL_FRACBITS - 32); 200 f0 = frac >> DBL_SHIFT; 201 f1 = (frac << (32 - DBL_SHIFT)) | (lo >> DBL_SHIFT); 202 f2 = lo << (32 - DBL_SHIFT); 203 frac |= lo; 204 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 205 } 206 207 /* 208 * Explode the contents of a register / regpair / regquad. 209 * If the input is a signalling NaN, an NV (invalid) exception 210 * will be set. (Note that nothing but NV can occur until ALU 211 * operations are performed.) 212 */ 213 void 214 fpu_explode(struct fpemu *fe, struct fpn *fp, int type, uint64_t i) 215 { 216 u_int hi, lo; 217 int class; 218 219 hi = (u_int)(i >> 32); 220 lo = (u_int)i; 221 fp->fp_sign = hi >> 31; 222 fp->fp_sticky = 0; 223 switch (type) { 224 225 case FTYPE_LNG: 226 class = fpu_xtof(fp, i); 227 break; 228 229 case FTYPE_INT: 230 fp->fp_sign = lo >> 31; 231 class = fpu_itof(fp, lo); 232 break; 233 234 case FTYPE_SNG: 235 class = fpu_stof(fp, hi); 236 break; 237 238 case FTYPE_DBL: 239 class = fpu_dtof(fp, hi, lo); 240 break; 241 242 default: 243 panic("fpu_explode: invalid type %d", type); 244 } 245 246 if (class == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 247 /* 248 * Input is a signalling NaN. All operations that return 249 * an input NaN operand put it through a ``NaN conversion'', 250 * which basically just means ``turn on the quiet bit''. 251 * We do this here so that all NaNs internally look quiet 252 * (we can tell signalling ones by their class). 253 */ 254 fp->fp_mant[0] |= FP_QUIETBIT; 255 fe->fe_cx = FPSCR_VXSNAN; /* assert invalid operand */ 256 class = FPC_SNAN; 257 } 258 fp->fp_class = class; 259 DUMPFPN(FPE_REG, fp); 260 } 261