1 /* $NetBSD: fpu_emu.c,v 1.33 2020/07/15 09:42:43 rin Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.33 2020/07/15 09:42:43 rin Exp $"); 80 81 #ifdef _KERNEL_OPT 82 #include "opt_ddb.h" 83 #endif 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/evcnt.h> 88 #include <sys/proc.h> 89 #include <sys/siginfo.h> 90 #include <sys/signal.h> 91 #include <sys/signalvar.h> 92 #include <sys/syslog.h> 93 94 #include <powerpc/instr.h> 95 #include <powerpc/psl.h> 96 97 #include <machine/fpu.h> 98 #include <machine/reg.h> 99 #include <machine/trap.h> 100 101 #include <powerpc/fpu/fpu_emu.h> 102 #include <powerpc/fpu/fpu_extern.h> 103 104 #define FPU_EMU_EVCNT_DECL(name) \ 105 static struct evcnt fpu_emu_ev_##name = \ 106 EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "fpemu", #name); \ 107 EVCNT_ATTACH_STATIC(fpu_emu_ev_##name) 108 109 #define FPU_EMU_EVCNT_INCR(name) \ 110 fpu_emu_ev_##name.ev_count++ 111 112 FPU_EMU_EVCNT_DECL(stfiwx); 113 FPU_EMU_EVCNT_DECL(fpstore); 114 FPU_EMU_EVCNT_DECL(fpload); 115 FPU_EMU_EVCNT_DECL(fcmpu); 116 FPU_EMU_EVCNT_DECL(frsp); 117 FPU_EMU_EVCNT_DECL(fctiw); 118 FPU_EMU_EVCNT_DECL(fcmpo); 119 FPU_EMU_EVCNT_DECL(mtfsb1); 120 FPU_EMU_EVCNT_DECL(fnegabs); 121 FPU_EMU_EVCNT_DECL(mcrfs); 122 FPU_EMU_EVCNT_DECL(mtfsb0); 123 FPU_EMU_EVCNT_DECL(fmr); 124 FPU_EMU_EVCNT_DECL(mtfsfi); 125 FPU_EMU_EVCNT_DECL(fnabs); 126 FPU_EMU_EVCNT_DECL(fabs); 127 FPU_EMU_EVCNT_DECL(mffs); 128 FPU_EMU_EVCNT_DECL(mtfsf); 129 FPU_EMU_EVCNT_DECL(fctid); 130 FPU_EMU_EVCNT_DECL(fcfid); 131 FPU_EMU_EVCNT_DECL(fdiv); 132 FPU_EMU_EVCNT_DECL(fsub); 133 FPU_EMU_EVCNT_DECL(fadd); 134 FPU_EMU_EVCNT_DECL(fsqrt); 135 FPU_EMU_EVCNT_DECL(fsel); 136 FPU_EMU_EVCNT_DECL(fpres); 137 FPU_EMU_EVCNT_DECL(fmul); 138 FPU_EMU_EVCNT_DECL(frsqrte); 139 FPU_EMU_EVCNT_DECL(fmulsub); 140 FPU_EMU_EVCNT_DECL(fmuladd); 141 FPU_EMU_EVCNT_DECL(fnmsub); 142 FPU_EMU_EVCNT_DECL(fnmadd); 143 144 /* FPSR exception masks */ 145 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 146 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 147 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 148 FPSCR_VXSQRT|FPSCR_VXCVI) 149 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 150 #define FPSR_INV (FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 151 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 152 FPSCR_VXSQRT|FPSCR_VXCVI) 153 154 155 int fpe_debug = 0; 156 157 #ifdef DDB 158 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 159 #endif 160 161 #ifdef DEBUG 162 /* 163 * Dump a `fpn' structure. 164 */ 165 void 166 fpu_dumpfpn(struct fpn *fp) 167 { 168 static const char *class[] = { 169 "SNAN", "QNAN", "ZERO", "NUM", "INF" 170 }; 171 172 KASSERT(fp != NULL); 173 174 printf("%s %c.%x %x %x %xE%d\n", class[fp->fp_class + 2], 175 fp->fp_sign ? '-' : ' ', 176 fp->fp_mant[0], fp->fp_mant[1], 177 fp->fp_mant[2], fp->fp_mant[3], 178 fp->fp_exp); 179 } 180 #endif 181 182 /* 183 * fpu_execute returns the following error numbers (0 = no error): 184 */ 185 #define FPE 1 /* take a floating point exception */ 186 #define NOTFPU 2 /* not an FPU instruction */ 187 #define FAULT 3 188 189 190 /* 191 * Emulate a floating-point instruction. 192 * Return zero for success, else signal number. 193 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 194 */ 195 bool 196 fpu_emulate(struct trapframe *tf, struct fpreg *fpf, ksiginfo_t *ksi) 197 { 198 struct pcb *pcb; 199 union instr insn; 200 struct fpemu fe; 201 202 KSI_INIT_TRAP(ksi); 203 ksi->ksi_signo = 0; 204 ksi->ksi_addr = (void *)tf->tf_srr0; 205 206 /* initialize insn.is_datasize to tell it is *not* initialized */ 207 fe.fe_fpstate = fpf; 208 fe.fe_cx = 0; 209 210 /* always set this (to avoid a warning) */ 211 212 if (copyin((void *) (tf->tf_srr0), &insn.i_int, sizeof (insn.i_int))) { 213 #ifdef DEBUG 214 printf("fpu_emulate: fault reading opcode\n"); 215 #endif 216 ksi->ksi_signo = SIGSEGV; 217 ksi->ksi_trap = EXC_ISI; 218 ksi->ksi_code = SEGV_MAPERR; 219 return true; 220 } 221 222 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 223 insn.i_int, (void *)tf->tf_srr0)); 224 225 if ((insn.i_any.i_opcd == OPC_TWI) || 226 ((insn.i_any.i_opcd == OPC_integer_31) && 227 (insn.i_x.i_xo == OPC31_TW))) { 228 /* Check for the two trap insns. */ 229 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 230 ksi->ksi_signo = SIGTRAP; 231 ksi->ksi_trap = EXC_PGM; 232 ksi->ksi_code = TRAP_BRKPT; 233 return true; 234 } 235 switch (fpu_execute(tf, &fe, &insn)) { 236 case 0: 237 success: 238 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 239 tf->tf_srr0 += 4; 240 return true; 241 242 case FPE: 243 pcb = lwp_getpcb(curlwp); 244 if ((pcb->pcb_flags & PSL_FE_PREC) == 0) 245 goto success; 246 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 247 ksi->ksi_signo = SIGFPE; 248 ksi->ksi_trap = EXC_PGM; 249 ksi->ksi_code = fpu_get_fault_code(); 250 return true; 251 252 case FAULT: 253 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 254 ksi->ksi_signo = SIGSEGV; 255 ksi->ksi_trap = EXC_DSI; 256 ksi->ksi_code = SEGV_MAPERR; 257 ksi->ksi_addr = (void *)fe.fe_addr; 258 return true; 259 260 case NOTFPU: 261 default: 262 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 263 #if defined(DDB) && defined(DEBUG) 264 if (fpe_debug & FPE_EX) { 265 printf("fpu_emulate: illegal insn %x at %p:", 266 insn.i_int, (void *) (tf->tf_srr0)); 267 opc_disasm((vaddr_t)(tf->tf_srr0), insn.i_int); 268 } 269 #endif 270 return false; 271 } 272 } 273 274 /* 275 * Execute an FPU instruction (one that runs entirely in the FPU; not 276 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 277 * modified to reflect the setting the hardware would have left. 278 * 279 * Note that we do not catch all illegal opcodes, so you can, for instance, 280 * multiply two integers this way. 281 */ 282 int 283 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 284 { 285 struct fpn *fp; 286 union instr instr = *insn; 287 int *a; 288 vaddr_t addr; 289 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr; 290 unsigned int cond; 291 struct fpreg *fs; 292 int mtfsf = 0; 293 294 /* Setup work. */ 295 fp = NULL; 296 fs = fe->fe_fpstate; 297 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 298 299 /* 300 * On PowerPC all floating point values are stored in registers 301 * as doubles, even when used for single precision operations. 302 */ 303 type = FTYPE_DBL; 304 cond = instr.i_any.i_rc; 305 setcr = 0; 306 bf = 0; /* XXX gcc */ 307 308 #if defined(DDB) && defined(DEBUG) 309 if (fpe_debug & FPE_EX) { 310 vaddr_t loc = tf->tf_srr0; 311 312 printf("Trying to emulate: %p ", (void *)loc); 313 opc_disasm(loc, instr.i_int); 314 } 315 #endif 316 317 /* 318 * `Decode' and execute instruction. 319 */ 320 321 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 322 instr.i_any.i_opcd == OPC_integer_31) { 323 /* 324 * Handle load/store insns: 325 * 326 * Convert to/from single if needed, calculate addr, 327 * and update index reg if needed. 328 */ 329 uint64_t buf; 330 size_t size = sizeof(float); 331 int store, update; 332 333 cond = 0; /* ld/st never set condition codes */ 334 335 336 if (instr.i_any.i_opcd == OPC_integer_31) { 337 if (instr.i_x.i_xo == OPC31_STFIWX) { 338 FPU_EMU_EVCNT_INCR(stfiwx); 339 340 /* Store as integer */ 341 ra = instr.i_x.i_ra; 342 rb = instr.i_x.i_rb; 343 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 344 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 345 346 addr = tf->tf_fixreg[rb]; 347 if (ra != 0) 348 addr += tf->tf_fixreg[ra]; 349 rt = instr.i_x.i_rt; 350 a = (int *)&fs->fpreg[rt]; 351 DPRINTF(FPE_INSN, 352 ("fpu_execute: Store INT %x at %p\n", 353 a[1], (void *)addr)); 354 if (copyout(&a[1], (void *)addr, sizeof(int))) { 355 fe->fe_addr = addr; 356 return (FAULT); 357 } 358 return (0); 359 } 360 361 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 362 /* Not an indexed FP load/store op */ 363 return (NOTFPU); 364 365 store = (instr.i_x.i_xo & 0x80); 366 if (instr.i_x.i_xo & 0x40) 367 size = sizeof(double); 368 else 369 type = FTYPE_SNG; 370 update = (instr.i_x.i_xo & 0x20); 371 372 /* calculate EA of load/store */ 373 ra = instr.i_x.i_ra; 374 rb = instr.i_x.i_rb; 375 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 376 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 377 addr = tf->tf_fixreg[rb]; 378 if (ra != 0) 379 addr += tf->tf_fixreg[ra]; 380 rt = instr.i_x.i_rt; 381 } else { 382 store = instr.i_d.i_opcd & 0x4; 383 if (instr.i_d.i_opcd & 0x2) 384 size = sizeof(double); 385 else 386 type = FTYPE_SNG; 387 update = instr.i_d.i_opcd & 0x1; 388 389 /* calculate EA of load/store */ 390 ra = instr.i_d.i_ra; 391 addr = instr.i_d.i_d; 392 DPRINTF(FPE_INSN, ("reg %d has %lx displ %lx\n", 393 ra, tf->tf_fixreg[ra], addr)); 394 if (ra != 0) 395 addr += tf->tf_fixreg[ra]; 396 rt = instr.i_d.i_rt; 397 } 398 399 if (update && ra == 0) 400 return (NOTFPU); 401 402 if (store) { 403 /* Store */ 404 FPU_EMU_EVCNT_INCR(fpstore); 405 if (type != FTYPE_DBL) { 406 DPRINTF(FPE_INSN, 407 ("fpu_execute: Store SNG at %p\n", 408 (void *)addr)); 409 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 410 fpu_implode(fe, fp, type, (void *)&buf); 411 if (copyout(&buf, (void *)addr, size)) { 412 fe->fe_addr = addr; 413 return (FAULT); 414 } 415 } else { 416 DPRINTF(FPE_INSN, 417 ("fpu_execute: Store DBL at %p\n", 418 (void *)addr)); 419 if (copyout(&fs->fpreg[rt], (void *)addr, size)) { 420 fe->fe_addr = addr; 421 return (FAULT); 422 } 423 } 424 } else { 425 /* Load */ 426 FPU_EMU_EVCNT_INCR(fpload); 427 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 428 (void *)addr)); 429 if (copyin((const void *)addr, &fs->fpreg[rt], size)) { 430 fe->fe_addr = addr; 431 return (FAULT); 432 } 433 if (type != FTYPE_DBL) { 434 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 435 fpu_implode(fe, fp, FTYPE_DBL, 436 (u_int *)&fs->fpreg[rt]); 437 } 438 } 439 if (update) 440 tf->tf_fixreg[ra] = addr; 441 /* Complete. */ 442 return (0); 443 #ifdef notyet 444 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 445 /* These are 64-bit extenstions */ 446 return (NOTFPU); 447 #endif 448 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 449 instr.i_any.i_opcd == OPC_dp_fp_63) { 450 451 452 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 453 !(instr.i_a.i_xo & OPC63M_MASK)) { 454 /* Format X */ 455 rt = instr.i_x.i_rt; 456 ra = instr.i_x.i_ra; 457 rb = instr.i_x.i_rb; 458 459 460 /* One of the special opcodes.... */ 461 switch (instr.i_x.i_xo) { 462 case OPC63_FCMPU: 463 FPU_EMU_EVCNT_INCR(fcmpu); 464 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 465 rt >>= 2; 466 fpu_explode(fe, &fe->fe_f1, type, ra); 467 fpu_explode(fe, &fe->fe_f2, type, rb); 468 fpu_compare(fe, 0); 469 /* Make sure we do the condition regs. */ 470 cond = 0; 471 /* N.B.: i_rs is already left shifted by two. */ 472 bf = instr.i_x.i_rs & 0xfc; 473 setcr = 1; 474 break; 475 476 case OPC63_FRSP: 477 /* 478 * Convert to single: 479 * 480 * PowerPC uses this to round a double 481 * precision value to single precision, 482 * but values in registers are always 483 * stored in double precision format. 484 */ 485 FPU_EMU_EVCNT_INCR(frsp); 486 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 487 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 488 fpu_implode(fe, fp, FTYPE_SNG, 489 (u_int *)&fs->fpreg[rt]); 490 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 491 type = FTYPE_DBL; 492 break; 493 case OPC63_FCTIW: 494 case OPC63_FCTIWZ: 495 FPU_EMU_EVCNT_INCR(fctiw); 496 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 497 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 498 type = FTYPE_INT; 499 break; 500 case OPC63_FCMPO: 501 FPU_EMU_EVCNT_INCR(fcmpo); 502 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 503 rt >>= 2; 504 fpu_explode(fe, &fe->fe_f1, type, ra); 505 fpu_explode(fe, &fe->fe_f2, type, rb); 506 fpu_compare(fe, 1); 507 /* Make sure we do the condition regs. */ 508 cond = 0; 509 /* N.B.: i_rs is already left shifted by two. */ 510 bf = instr.i_x.i_rs & 0xfc; 511 setcr = 1; 512 break; 513 case OPC63_MTFSB1: 514 FPU_EMU_EVCNT_INCR(mtfsb1); 515 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 516 fe->fe_fpscr |= 517 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 518 break; 519 case OPC63_FNEG: 520 FPU_EMU_EVCNT_INCR(fnegabs); 521 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 522 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 523 sizeof(double)); 524 a = (int *)&fs->fpreg[rt]; 525 *a ^= (1 << 31); 526 break; 527 case OPC63_MCRFS: 528 FPU_EMU_EVCNT_INCR(mcrfs); 529 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 530 cond = 0; 531 rt &= 0x1c; 532 ra &= 0x1c; 533 /* Extract the bits we want */ 534 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 535 /* Clear the bits we copied. */ 536 fe->fe_cx = 537 (FPSR_EX_MSK | (0xf << (28 - ra))); 538 fe->fe_fpscr &= fe->fe_cx; 539 /* Now shove them in the right part of cr */ 540 tf->tf_cr &= ~(0xf << (28 - rt)); 541 tf->tf_cr |= (mask << (28 - rt)); 542 break; 543 case OPC63_MTFSB0: 544 FPU_EMU_EVCNT_INCR(mtfsb0); 545 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 546 fe->fe_fpscr &= 547 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 548 break; 549 case OPC63_FMR: 550 FPU_EMU_EVCNT_INCR(fmr); 551 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 552 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 553 sizeof(double)); 554 break; 555 case OPC63_MTFSFI: 556 mtfsf = 1; 557 FPU_EMU_EVCNT_INCR(mtfsfi); 558 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 559 rb >>= 1; 560 rt &= 0x1c; /* Already left-shifted 4 */ 561 fe->fe_cx = rb << (28 - rt); 562 mask = 0xf<<(28 - rt); 563 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 564 fe->fe_cx; 565 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 566 break; 567 case OPC63_FNABS: 568 FPU_EMU_EVCNT_INCR(fnabs); 569 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 570 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 571 sizeof(double)); 572 a = (int *)&fs->fpreg[rt]; 573 *a |= (1 << 31); 574 break; 575 case OPC63_FABS: 576 FPU_EMU_EVCNT_INCR(fabs); 577 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 578 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 579 sizeof(double)); 580 a = (int *)&fs->fpreg[rt]; 581 *a &= ~(1 << 31); 582 break; 583 case OPC63_MFFS: 584 FPU_EMU_EVCNT_INCR(mffs); 585 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 586 /* XXX FEX is not sticky */ 587 fs->fpscr &= ~FPSCR_FEX; 588 memcpy(&fs->fpreg[rt], &fs->fpscr, 589 sizeof(fs->fpscr)); 590 break; 591 case OPC63_MTFSF: 592 mtfsf = 1; 593 FPU_EMU_EVCNT_INCR(mtfsf); 594 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 595 if ((rt = instr.i_xfl.i_flm) == -1) 596 mask = -1; 597 else { 598 mask = 0; 599 /* Convert 1 bit -> 4 bits */ 600 for (ra = 0; ra < 8; ra ++) 601 if (rt & (1<<ra)) 602 mask |= (0xf<<(4*ra)); 603 } 604 a = (int *)&fs->fpreg[rb]; 605 fe->fe_cx = mask & a[1]; 606 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 607 (fe->fe_cx); 608 /* 609 * XXX 610 * Forbidden to set FEX and VX, also for 611 * mcrfs, mtfsfi, and mtfsb[01]. 612 * 613 * XXX 614 * Handle invalid operation differently, 615 * depending on VE. 616 */ 617 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 618 break; 619 case OPC63_FCTID: 620 case OPC63_FCTIDZ: 621 FPU_EMU_EVCNT_INCR(fctid); 622 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 623 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 624 type = FTYPE_LNG; 625 break; 626 case OPC63_FCFID: 627 FPU_EMU_EVCNT_INCR(fcfid); 628 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 629 type = FTYPE_LNG; 630 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 631 type = FTYPE_DBL; 632 break; 633 default: 634 return (NOTFPU); 635 break; 636 } 637 } else { 638 /* Format A */ 639 rt = instr.i_a.i_frt; 640 ra = instr.i_a.i_fra; 641 rb = instr.i_a.i_frb; 642 rc = instr.i_a.i_frc; 643 644 /* 645 * All arithmetic operations work on registers, which 646 * are stored as doubles. 647 */ 648 type = FTYPE_DBL; 649 switch ((unsigned int)instr.i_a.i_xo) { 650 case OPC59_FDIVS: 651 FPU_EMU_EVCNT_INCR(fdiv); 652 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 653 fpu_explode(fe, &fe->fe_f1, type, ra); 654 fpu_explode(fe, &fe->fe_f2, type, rb); 655 fp = fpu_div(fe); 656 break; 657 case OPC59_FSUBS: 658 FPU_EMU_EVCNT_INCR(fsub); 659 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 660 fpu_explode(fe, &fe->fe_f1, type, ra); 661 fpu_explode(fe, &fe->fe_f2, type, rb); 662 fp = fpu_sub(fe); 663 break; 664 case OPC59_FADDS: 665 FPU_EMU_EVCNT_INCR(fadd); 666 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 667 fpu_explode(fe, &fe->fe_f1, type, ra); 668 fpu_explode(fe, &fe->fe_f2, type, rb); 669 fp = fpu_add(fe); 670 break; 671 case OPC59_FSQRTS: 672 FPU_EMU_EVCNT_INCR(fsqrt); 673 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 674 fpu_explode(fe, &fe->fe_f1, type, rb); 675 fp = fpu_sqrt(fe); 676 break; 677 case OPC63M_FSEL: 678 FPU_EMU_EVCNT_INCR(fsel); 679 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 680 a = (int *)&fe->fe_fpstate->fpreg[ra]; 681 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 682 /* fra < 0 */ 683 rc = rb; 684 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 685 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 686 sizeof(double)); 687 break; 688 case OPC59_FRES: 689 FPU_EMU_EVCNT_INCR(fpres); 690 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 691 fpu_explode(fe, &fe->fe_f1, type, rb); 692 fp = fpu_sqrt(fe); 693 /* now we've gotta overwrite the dest reg */ 694 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 695 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 696 fpu_div(fe); 697 break; 698 case OPC59_FMULS: 699 FPU_EMU_EVCNT_INCR(fmul); 700 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 701 fpu_explode(fe, &fe->fe_f1, type, ra); 702 fpu_explode(fe, &fe->fe_f2, type, rc); 703 fp = fpu_mul(fe); 704 break; 705 case OPC63M_FRSQRTE: 706 /* Reciprocal sqrt() estimate */ 707 FPU_EMU_EVCNT_INCR(frsqrte); 708 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 709 fpu_explode(fe, &fe->fe_f1, type, rb); 710 fp = fpu_sqrt(fe); 711 fe->fe_f2 = *fp; 712 /* now we've gotta overwrite the dest reg */ 713 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 714 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 715 fpu_div(fe); 716 break; 717 case OPC59_FMSUBS: 718 FPU_EMU_EVCNT_INCR(fmulsub); 719 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 720 fpu_explode(fe, &fe->fe_f1, type, ra); 721 fpu_explode(fe, &fe->fe_f2, type, rc); 722 fp = fpu_mul(fe); 723 fe->fe_f1 = *fp; 724 fpu_explode(fe, &fe->fe_f2, type, rb); 725 fp = fpu_sub(fe); 726 break; 727 case OPC59_FMADDS: 728 FPU_EMU_EVCNT_INCR(fmuladd); 729 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 730 fpu_explode(fe, &fe->fe_f1, type, ra); 731 fpu_explode(fe, &fe->fe_f2, type, rc); 732 fp = fpu_mul(fe); 733 fe->fe_f1 = *fp; 734 fpu_explode(fe, &fe->fe_f2, type, rb); 735 fp = fpu_add(fe); 736 break; 737 case OPC59_FNMSUBS: 738 FPU_EMU_EVCNT_INCR(fnmsub); 739 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 740 fpu_explode(fe, &fe->fe_f1, type, ra); 741 fpu_explode(fe, &fe->fe_f2, type, rc); 742 fp = fpu_mul(fe); 743 fe->fe_f1 = *fp; 744 fpu_explode(fe, &fe->fe_f2, type, rb); 745 fp = fpu_sub(fe); 746 /* Negate */ 747 fp->fp_sign ^= 1; 748 break; 749 case OPC59_FNMADDS: 750 FPU_EMU_EVCNT_INCR(fnmadd); 751 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 752 fpu_explode(fe, &fe->fe_f1, type, ra); 753 fpu_explode(fe, &fe->fe_f2, type, rc); 754 fp = fpu_mul(fe); 755 fe->fe_f1 = *fp; 756 fpu_explode(fe, &fe->fe_f2, type, rb); 757 fp = fpu_add(fe); 758 /* Negate */ 759 fp->fp_sign ^= 1; 760 break; 761 default: 762 return (NOTFPU); 763 break; 764 } 765 766 /* If the instruction was single precision, round */ 767 if (!(instr.i_any.i_opcd & 0x4)) { 768 fpu_implode(fe, fp, FTYPE_SNG, 769 (u_int *)&fs->fpreg[rt]); 770 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 771 } 772 } 773 } else { 774 return (NOTFPU); 775 } 776 777 /* 778 * ALU operation is complete. Collapse the result and then check 779 * for exceptions. If we got any, and they are enabled, do not 780 * alter the destination register, just stop with an exception. 781 * Otherwise set new current exceptions and accrue. 782 */ 783 if (fp) 784 fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]); 785 cx = fe->fe_cx; 786 fsr = fe->fe_fpscr & ~(FPSCR_FEX|FPSCR_VX); 787 if (cx != 0) { 788 if (cx & FPSR_INV) 789 cx |= FPSCR_VX; 790 mask = fsr & FPSR_EX; 791 mask <<= (25-3); 792 if (cx & mask) 793 fsr |= FPSCR_FEX; 794 if (cx & FPSCR_FPRF) { 795 /* Need to replace CC */ 796 fsr &= ~FPSCR_FPRF; 797 } 798 fsr |= cx; 799 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 800 } 801 if (fsr & FPSR_INV) 802 fsr |= FPSCR_VX; 803 if (mtfsf == 0 && ((fsr ^ fe->fe_fpscr) & FPSR_EX_MSK)) 804 fsr |= FPSCR_FX; 805 806 if (cond) { 807 cond = fsr & 0xf0000000; 808 /* Isolate condition codes */ 809 cond >>= 28; 810 /* Move fpu condition codes to cr[1] */ 811 tf->tf_cr &= (0x0f000000); 812 tf->tf_cr |= (cond<<24); 813 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 814 } 815 816 if (setcr) { 817 cond = fsr & FPSCR_FPCC; 818 /* Isolate condition codes */ 819 cond <<= 16; 820 /* Move fpu condition codes to cr[1] */ 821 tf->tf_cr &= ~(0xf0000000>>bf); 822 tf->tf_cr |= (cond>>bf); 823 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->tf_cr, cond)); 824 } 825 826 ((int *)&fs->fpscr)[1] = fsr; 827 if (fsr & FPSCR_FEX) 828 return(FPE); 829 return (0); /* success */ 830 } 831