xref: /netbsd-src/sys/arch/powerpc/fpu/fpu_add.c (revision 5e4c038a45edbc7d63b7c2daa76e29f88b64a4e3)
1 /*	$NetBSD: fpu_add.c,v 1.1 2001/06/13 06:01:46 simonb Exp $ */
2 
3 /*
4  * Copyright (c) 1992, 1993
5  *	The Regents of the University of California.  All rights reserved.
6  *
7  * This software was developed by the Computer Systems Engineering group
8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9  * contributed to Berkeley.
10  *
11  * All advertising materials mentioning features or use of this software
12  * must display the following acknowledgement:
13  *	This product includes software developed by the University of
14  *	California, Lawrence Berkeley Laboratory.
15  *
16  * Redistribution and use in source and binary forms, with or without
17  * modification, are permitted provided that the following conditions
18  * are met:
19  * 1. Redistributions of source code must retain the above copyright
20  *    notice, this list of conditions and the following disclaimer.
21  * 2. Redistributions in binary form must reproduce the above copyright
22  *    notice, this list of conditions and the following disclaimer in the
23  *    documentation and/or other materials provided with the distribution.
24  * 3. All advertising materials mentioning features or use of this software
25  *    must display the following acknowledgement:
26  *	This product includes software developed by the University of
27  *	California, Berkeley and its contributors.
28  * 4. Neither the name of the University nor the names of its contributors
29  *    may be used to endorse or promote products derived from this software
30  *    without specific prior written permission.
31  *
32  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
36  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42  * SUCH DAMAGE.
43  *
44  *	@(#)fpu_add.c	8.1 (Berkeley) 6/11/93
45  */
46 
47 /*
48  * Perform an FPU add (return x + y).
49  *
50  * To subtract, negate y and call add.
51  */
52 
53 #include <sys/types.h>
54 #if defined(DIAGNOSTIC)||defined(DEBUG)
55 #include <sys/systm.h>
56 #endif
57 
58 #include <machine/reg.h>
59 #include <powerpc/instr.h>
60 #include <machine/fpu.h>
61 
62 #include <powerpc/fpu/fpu_arith.h>
63 #include <powerpc/fpu/fpu_emu.h>
64 #include <powerpc/fpu/fpu_extern.h>
65 
66 struct fpn *
67 fpu_add(struct fpemu *fe)
68 {
69 	struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2, *r;
70 	u_int r0, r1, r2, r3;
71 	int rd;
72 
73 	/*
74 	 * Put the `heavier' operand on the right (see fpu_emu.h).
75 	 * Then we will have one of the following cases, taken in the
76 	 * following order:
77 	 *
78 	 *  - y = NaN.  Implied: if only one is a signalling NaN, y is.
79 	 *	The result is y.
80 	 *  - y = Inf.  Implied: x != NaN (is 0, number, or Inf: the NaN
81 	 *    case was taken care of earlier).
82 	 *	If x = -y, the result is NaN.  Otherwise the result
83 	 *	is y (an Inf of whichever sign).
84 	 *  - y is 0.  Implied: x = 0.
85 	 *	If x and y differ in sign (one positive, one negative),
86 	 *	the result is +0 except when rounding to -Inf.  If same:
87 	 *	+0 + +0 = +0; -0 + -0 = -0.
88 	 *  - x is 0.  Implied: y != 0.
89 	 *	Result is y.
90 	 *  - other.  Implied: both x and y are numbers.
91 	 *	Do addition a la Hennessey & Patterson.
92 	 */
93 	DPRINTF(FPE_REG, ("fpu_add:\n"));
94 	DUMPFPN(FPE_REG, x);
95 	DUMPFPN(FPE_REG, y);
96 	DPRINTF(FPE_REG, ("=>\n"));
97 	ORDER(x, y);
98 	if (ISNAN(y)) {
99 		fe->fe_cx |= FPSCR_VXSNAN;
100 		DUMPFPN(FPE_REG, y);
101 		return (y);
102 	}
103 	if (ISINF(y)) {
104 		if (ISINF(x) && x->fp_sign != y->fp_sign) {
105 			fe->fe_cx |= FPSCR_VXISI;
106 			return (fpu_newnan(fe));
107 		}
108 		DUMPFPN(FPE_REG, y);
109 		return (y);
110 	}
111 	rd = ((fe->fe_fpscr) & FPSCR_RN);
112 	if (ISZERO(y)) {
113 		if (rd != FSR_RD_RM)	/* only -0 + -0 gives -0 */
114 			y->fp_sign &= x->fp_sign;
115 		else			/* any -0 operand gives -0 */
116 			y->fp_sign |= x->fp_sign;
117 		DUMPFPN(FPE_REG, y);
118 		return (y);
119 	}
120 	if (ISZERO(x)) {
121 		DUMPFPN(FPE_REG, y);
122 		return (y);
123 	}
124 	/*
125 	 * We really have two numbers to add, although their signs may
126 	 * differ.  Make the exponents match, by shifting the smaller
127 	 * number right (e.g., 1.011 => 0.1011) and increasing its
128 	 * exponent (2^3 => 2^4).  Note that we do not alter the exponents
129 	 * of x and y here.
130 	 */
131 	r = &fe->fe_f3;
132 	r->fp_class = FPC_NUM;
133 	if (x->fp_exp == y->fp_exp) {
134 		r->fp_exp = x->fp_exp;
135 		r->fp_sticky = 0;
136 	} else {
137 		if (x->fp_exp < y->fp_exp) {
138 			/*
139 			 * Try to avoid subtract case iii (see below).
140 			 * This also guarantees that x->fp_sticky = 0.
141 			 */
142 			SWAP(x, y);
143 		}
144 		/* now x->fp_exp > y->fp_exp */
145 		r->fp_exp = x->fp_exp;
146 		r->fp_sticky = fpu_shr(y, x->fp_exp - y->fp_exp);
147 	}
148 	r->fp_sign = x->fp_sign;
149 	if (x->fp_sign == y->fp_sign) {
150 		FPU_DECL_CARRY
151 
152 		/*
153 		 * The signs match, so we simply add the numbers.  The result
154 		 * may be `supernormal' (as big as 1.111...1 + 1.111...1, or
155 		 * 11.111...0).  If so, a single bit shift-right will fix it
156 		 * (but remember to adjust the exponent).
157 		 */
158 		/* r->fp_mant = x->fp_mant + y->fp_mant */
159 		FPU_ADDS(r->fp_mant[3], x->fp_mant[3], y->fp_mant[3]);
160 		FPU_ADDCS(r->fp_mant[2], x->fp_mant[2], y->fp_mant[2]);
161 		FPU_ADDCS(r->fp_mant[1], x->fp_mant[1], y->fp_mant[1]);
162 		FPU_ADDC(r0, x->fp_mant[0], y->fp_mant[0]);
163 		if ((r->fp_mant[0] = r0) >= FP_2) {
164 			(void) fpu_shr(r, 1);
165 			r->fp_exp++;
166 		}
167 	} else {
168 		FPU_DECL_CARRY
169 
170 		/*
171 		 * The signs differ, so things are rather more difficult.
172 		 * H&P would have us negate the negative operand and add;
173 		 * this is the same as subtracting the negative operand.
174 		 * This is quite a headache.  Instead, we will subtract
175 		 * y from x, regardless of whether y itself is the negative
176 		 * operand.  When this is done one of three conditions will
177 		 * hold, depending on the magnitudes of x and y:
178 		 *   case i)   |x| > |y|.  The result is just x - y,
179 		 *	with x's sign, but it may need to be normalized.
180 		 *   case ii)  |x| = |y|.  The result is 0 (maybe -0)
181 		 *	so must be fixed up.
182 		 *   case iii) |x| < |y|.  We goofed; the result should
183 		 *	be (y - x), with the same sign as y.
184 		 * We could compare |x| and |y| here and avoid case iii,
185 		 * but that would take just as much work as the subtract.
186 		 * We can tell case iii has occurred by an overflow.
187 		 *
188 		 * N.B.: since x->fp_exp >= y->fp_exp, x->fp_sticky = 0.
189 		 */
190 		/* r->fp_mant = x->fp_mant - y->fp_mant */
191 		FPU_SET_CARRY(y->fp_sticky);
192 		FPU_SUBCS(r3, x->fp_mant[3], y->fp_mant[3]);
193 		FPU_SUBCS(r2, x->fp_mant[2], y->fp_mant[2]);
194 		FPU_SUBCS(r1, x->fp_mant[1], y->fp_mant[1]);
195 		FPU_SUBC(r0, x->fp_mant[0], y->fp_mant[0]);
196 		if (r0 < FP_2) {
197 			/* cases i and ii */
198 			if ((r0 | r1 | r2 | r3) == 0) {
199 				/* case ii */
200 				r->fp_class = FPC_ZERO;
201 				r->fp_sign = rd == FSR_RD_RM;
202 				return (r);
203 			}
204 		} else {
205 			/*
206 			 * Oops, case iii.  This can only occur when the
207 			 * exponents were equal, in which case neither
208 			 * x nor y have sticky bits set.  Flip the sign
209 			 * (to y's sign) and negate the result to get y - x.
210 			 */
211 #ifdef DIAGNOSTIC
212 			if (x->fp_exp != y->fp_exp || r->fp_sticky)
213 				panic("fpu_add");
214 #endif
215 			r->fp_sign = y->fp_sign;
216 			FPU_SUBS(r3, 0, r3);
217 			FPU_SUBCS(r2, 0, r2);
218 			FPU_SUBCS(r1, 0, r1);
219 			FPU_SUBC(r0, 0, r0);
220 		}
221 		r->fp_mant[3] = r3;
222 		r->fp_mant[2] = r2;
223 		r->fp_mant[1] = r1;
224 		r->fp_mant[0] = r0;
225 		if (r0 < FP_1)
226 			fpu_norm(r);
227 	}
228 	DUMPFPN(FPE_REG, r);
229 	return (r);
230 }
231