xref: /netbsd-src/sys/arch/powerpc/booke/spe.c (revision b7b7574d3bf8eeb51a1fa3977b59142ec6434a55)
1 /*	$NetBSD: spe.c,v 1.8 2014/05/16 00:48:41 rmind Exp $	*/
2 
3 /*-
4  * Copyright (c) 2011 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Matt Thomas of 3am Software Foundry.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: spe.c,v 1.8 2014/05/16 00:48:41 rmind Exp $");
34 
35 #include "opt_altivec.h"
36 
37 #ifdef PPC_HAVE_SPE
38 
39 #include <sys/param.h>
40 #include <sys/proc.h>
41 #include <sys/systm.h>
42 #include <sys/atomic.h>
43 #include <sys/siginfo.h>
44 #include <sys/pcu.h>
45 
46 #include <powerpc/altivec.h>
47 #include <powerpc/spr.h>
48 #include <powerpc/booke/spr.h>
49 #include <powerpc/psl.h>
50 #include <powerpc/pcb.h>
51 
52 static void vec_state_load(lwp_t *, u_int);
53 static void vec_state_save(lwp_t *);
54 static void vec_state_release(lwp_t *);
55 
56 const pcu_ops_t vec_ops = {
57 	.pcu_id = PCU_VEC,
58 	.pcu_state_load = vec_state_load,
59 	.pcu_state_save = vec_state_save,
60 	.pcu_state_release = vec_state_release,
61 };
62 
63 bool
64 vec_used_p(lwp_t *l)
65 {
66 	return pcu_valid_p(&vec_ops);
67 }
68 
69 void
70 vec_mark_used(lwp_t *l)
71 {
72 	pcu_discard(&vec_ops, true);
73 }
74 
75 void
76 vec_state_load(lwp_t *l, u_int flags)
77 {
78 	struct pcb * const pcb = lwp_getpcb(l);
79 
80 	if ((flags & PCU_VALID) == 0) {
81 		memset(&pcb->pcb_vr, 0, sizeof(pcb->pcb_vr));
82 		vec_mark_used(l);
83 	}
84 
85 	/*
86 	 * Enable SPE temporarily (and disable interrupts).
87 	 */
88 	const register_t msr = mfmsr();
89 	mtmsr((msr & ~PSL_EE) | PSL_SPV);
90 	__asm volatile ("isync");
91 
92 	/*
93 	 * Call an assembly routine to do load everything.
94 	 */
95 	vec_load_from_vreg(&pcb->pcb_vr);
96 	__asm volatile ("sync");
97 
98 
99 	/*
100 	 * Restore MSR (turn off SPE)
101 	 */
102 	mtmsr(msr);
103 	__asm volatile ("isync");
104 
105 	/*
106 	 * Set PSL_SPV so vectors will be enabled on return to user.
107 	 */
108 	l->l_md.md_utf->tf_srr1 |= PSL_SPV;
109 }
110 
111 void
112 vec_state_save(lwp_t *l)
113 {
114 	struct pcb * const pcb = lwp_getpcb(l);
115 
116 	/*
117 	 * Turn on SPE, turn off interrupts.
118 	 */
119 	const register_t msr = mfmsr();
120 	mtmsr((msr & ~PSL_EE) | PSL_SPV);
121 	__asm volatile ("isync");
122 
123 	/*
124 	 * Save the vector state which is best done in assembly.
125 	 */
126 	vec_unload_to_vreg(&pcb->pcb_vr);
127 	__asm volatile ("sync");
128 
129 	/*
130 	 * Restore MSR (turn off SPE)
131 	 */
132 	mtmsr(msr);
133 	__asm volatile ("isync");
134 }
135 
136 void
137 vec_state_release(lwp_t *l)
138 {
139 	/*
140 	 * Turn off SPV so the next SPE instruction will cause a
141 	 * SPE unavailable exception
142 	 */
143 	l->l_md.md_utf->tf_srr1 &= ~PSL_SPV;
144 }
145 
146 void
147 vec_restore_from_mcontext(lwp_t *l, const mcontext_t *mcp)
148 {
149 	struct pcb * const pcb = lwp_getpcb(l);
150 	const union __vr *vr = mcp->__vrf.__vrs;
151 
152 	KASSERT(l == curlwp);
153 
154 	vec_save();
155 
156 	/* grab the accumulator */
157 	pcb->pcb_vr.vreg[8][0] = vr->__vr32[2];
158 	pcb->pcb_vr.vreg[8][1] = vr->__vr32[3];
159 
160 	/*
161 	 * We store the high parts of each register in the first 8 vectors.
162 	 */
163 	for (u_int i = 0; i < 8; i++, vr += 4) {
164 		pcb->pcb_vr.vreg[i][0] = vr[0].__vr32[0];
165 		pcb->pcb_vr.vreg[i][1] = vr[1].__vr32[0];
166 		pcb->pcb_vr.vreg[i][2] = vr[2].__vr32[0];
167 		pcb->pcb_vr.vreg[i][3] = vr[3].__vr32[0];
168 	}
169 	l->l_md.md_utf->tf_spefscr = pcb->pcb_vr.vscr = mcp->__vrf.__vscr;
170 	pcb->pcb_vr.vrsave = mcp->__vrf.__vrsave;
171 }
172 
173 bool
174 vec_save_to_mcontext(lwp_t *l, mcontext_t *mcp, unsigned int *flagp)
175 {
176 	struct pcb * const pcb = lwp_getpcb(l);
177 
178 	KASSERT(l == curlwp);
179 
180 	if (!vec_used_p(l))
181 		return false;
182 
183 	vec_save();
184 
185 	mcp->__gregs[_REG_MSR] |= PSL_SPV;
186 
187 	union __vr *vr = mcp->__vrf.__vrs;
188 	const register_t *fixreg = l->l_md.md_utf->tf_fixreg;
189 	for (u_int i = 0; i < 32; i++, vr += 4, fixreg += 4) {
190 		vr[0].__vr32[0] = pcb->pcb_vr.vreg[i][0];
191 		vr[0].__vr32[1] = fixreg[0];
192 		vr[0].__vr32[2] = 0;
193 		vr[0].__vr32[3] = 0;
194 		vr[1].__vr32[0] = pcb->pcb_vr.vreg[i][1];
195 		vr[1].__vr32[1] = fixreg[1];
196 		vr[1].__vr32[2] = 0;
197 		vr[1].__vr32[3] = 0;
198 		vr[2].__vr32[0] = pcb->pcb_vr.vreg[i][2];
199 		vr[2].__vr32[1] = fixreg[2];
200 		vr[2].__vr32[2] = 0;
201 		vr[2].__vr32[3] = 0;
202 		vr[3].__vr32[0] = pcb->pcb_vr.vreg[i][3];
203 		vr[3].__vr32[1] = fixreg[3];
204 		vr[3].__vr32[2] = 0;
205 		vr[3].__vr32[3] = 0;
206 	}
207 
208 	mcp->__vrf.__vrs[0].__vr32[2] = pcb->pcb_vr.vreg[8][0];
209 	mcp->__vrf.__vrs[0].__vr32[3] = pcb->pcb_vr.vreg[8][1];
210 
211 	mcp->__vrf.__vrsave = pcb->pcb_vr.vrsave;
212 	mcp->__vrf.__vscr = l->l_md.md_utf->tf_spefscr;
213 
214 	*flagp |= _UC_POWERPC_SPE;
215 
216 	return true;
217 }
218 
219 static const struct {
220 	uint32_t mask;
221 	int code;
222 } spefscr_siginfo_map[] = {
223 	{ SPEFSCR_FINV|SPEFSCR_FINVH, FPE_FLTINV },
224 	{ SPEFSCR_FOVF|SPEFSCR_FOVFH, FPE_FLTOVF },
225 	{ SPEFSCR_FUNF|SPEFSCR_FUNFH, FPE_FLTUND },
226 	{ SPEFSCR_FX  |SPEFSCR_FXH,   FPE_FLTRES },
227 	{ SPEFSCR_FDBZ|SPEFSCR_FDBZH, FPE_FLTDIV },
228 	{ SPEFSCR_OV  |SPEFSCR_OVH,   FPE_INTOVF },
229 };
230 
231 int
232 vec_siginfo_code(const struct trapframe *tf)
233 {
234 	for (u_int i = 0; i < __arraycount(spefscr_siginfo_map); i++) {
235 		if (tf->tf_spefscr & spefscr_siginfo_map[i].mask)
236 			return spefscr_siginfo_map[i].code;
237 	}
238 	return 0;
239 }
240 
241 #endif /* PPC_HAVE_SPE */
242