1 /*- 2 * Copyright (c) 2011 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "opt_flash.h" 31 #define LBC_PRIVATE 32 33 #include <sys/cdefs.h> 34 35 __KERNEL_RCSID(0, "$NetBSD: pq3nandfcm.c,v 1.2 2011/07/17 23:08:56 dyoung Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/cpu.h> 41 42 #include <sys/bus.h> 43 44 #include <powerpc/booke/cpuvar.h> 45 #include <powerpc/booke/e500reg.h> 46 #include <powerpc/booke/obiovar.h> 47 48 #include <dev/nand/nand.h> 49 #include <dev/nand/onfi.h> 50 51 static int pq3nandfcm_match(device_t, cfdata_t, void *); 52 static void pq3nandfcm_attach(device_t, device_t, void *); 53 static int pq3nandfcm_detach(device_t, int); 54 55 static void pq3nandfcm_select(device_t, bool); 56 static void pq3nandfcm_command(device_t, uint8_t); 57 static void pq3nandfcm_address(device_t, uint8_t); 58 static void pq3nandfcm_busy(device_t); 59 static void pq3nandfcm_read_byte(device_t, uint8_t *); 60 static void pq3nandfcm_write_byte(device_t, uint8_t); 61 static void pq3nandfcm_read_buf(device_t, void *, size_t); 62 static void pq3nandfcm_write_buf(device_t, const void *, size_t); 63 64 struct pq3nandfcm_softc { 65 device_t sc_dev; 66 bus_space_tag_t sc_window_bst; 67 bus_space_handle_t sc_window_bsh; 68 bus_size_t sc_window_size; 69 70 struct nand_interface sc_nandif; 71 device_t sc_nanddev; 72 73 struct pq3obio_softc *sc_obio; 74 struct pq3lbc_softc *sc_lbc; 75 76 u_int sc_cs; 77 78 }; 79 80 CFATTACH_DECL_NEW(pq3nandfcm, sizeof(struct pq3nandfcm_softc), 81 pq3nandfcm_match, pq3nandfcm_attach, pq3nandfcm_detach, NULL); 82 83 int 84 pq3nandfcm_match(device_t parent, cfdata_t cf, void *aux) 85 { 86 struct generic_attach_args * const ga = aux; 87 struct pq3obio_softc * const psc = device_private(parent); 88 struct pq3lbc_softc * const lbc = &psc->sc_lbcs[ga->ga_cs]; 89 90 if ((lbc->lbc_br & BR_V) == 0) 91 return 0; 92 93 if (__SHIFTOUT(lbc->lbc_br,BR_MSEL) != BR_MSEL_FCM) 94 return 0; 95 96 return 1; 97 } 98 99 void 100 pq3nandfcm_attach(device_t parent, device_t self, void *aux) 101 { 102 struct generic_attach_args * const ga = aux; 103 struct pq3nandfcm_softc * const sc = device_private(self); 104 struct pq3obio_softc * const psc = device_private(parent); 105 struct pq3lbc_softc * const lbc = &psc->sc_lbcs[ga->ga_cs]; 106 107 sc->sc_dev = self; 108 sc->sc_obio = psc; 109 sc->sc_lbc = lbc; 110 } 111 112 int 113 pq3nandfcm_detach(device_t self, int flags) 114 { 115 struct pq3nandfcm_softc * const sc = device_private(self); 116 int rv = 0; 117 118 pmf_device_deregister(self); 119 120 if (sc->sc_nanddev != NULL) 121 rv = config_detach(sc->sc_nanddev, flags); 122 123 bus_space_unmap(sc->sc_window_bst, sc->sc_window_bsh, 124 sc->sc_window_size); 125 return rv; 126 } 127 void 128 pq3nandfcm_command(device_t self, uint8_t command) 129 { 130 struct pq3nandfcm_softc * const sc = device_private(self); 131 132 lbc_lock(sc->sc_obio); 133 lbc_write_4(sc->sc_obio, FCR, __SHIFTIN(command, FCR_CMD0)); 134 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_CM0, FIR_OP0)); 135 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs); 136 lbc_unlock(sc->sc_obio); 137 138 } 139 140 void 141 pq3nandfcm_address(device_t self, uint8_t address) 142 { 143 struct pq3nandfcm_softc * const sc = device_private(self); 144 145 lbc_lock(sc->sc_obio); 146 lbc_write_4(sc->sc_obio, MDR, __SHIFTIN(address, MDR_AS0)); 147 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_UA, FIR_OP0)); 148 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs); 149 lbc_unlock(sc->sc_obio); 150 } 151 152 void 153 pq3nandfcm_busy(device_t self) 154 { 155 struct pq3nandfcm_softc * const sc = device_private(self); 156 157 lbc_lock(sc->sc_obio); 158 for (;;) { 159 uint32_t v = lbc_read_4(sc->sc_obio, LTESR); 160 if ((v & LTESR_CC) == 0) { 161 /* 162 * The command is done but the device might not 163 * be ready since the CC doesn't check for that. 164 */ 165 break; 166 } 167 DELAY(1); 168 } 169 lbc_unlock(sc->sc_obio); 170 } 171 172 void 173 pq3nandfcm_read_byte(device_t self, uint8_t *valp) 174 { 175 struct pq3nandfcm_softc * const sc = device_private(self); 176 177 lbc_lock(sc->sc_obio); 178 /* 179 * Make sure the device is ready before reading the byte. 180 */ 181 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_RSW, FIR_OP0)); 182 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs); 183 uint32_t v = lbc_read_4(sc->sc_obio, MDR); 184 lbc_unlock(sc->sc_obio); 185 186 *valp = (uint8_t) v; 187 } 188 189 void 190 pq3nandfcm_write_byte(device_t self, uint8_t val) 191 { 192 struct pq3nandfcm_softc * const sc = device_private(self); 193 194 lbc_lock(sc->sc_obio); 195 lbc_write_4(sc->sc_obio, MDR, val); 196 /* 197 * Make sure the device is ready before writing the byte. 198 */ 199 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_WS, FIR_OP0)); 200 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs); 201 lbc_unlock(sc->sc_obio); 202 } 203 204 void 205 pq3nandfcm_read_buf(device_t self, void *buf, size_t len) 206 { 207 struct pq3nandfcm_softc * const sc = device_private(self); 208 bus_size_t offset = 0; 209 uint32_t *dp32 = buf; 210 211 KASSERT(len < 4096); 212 KASSERT((len & 3) == 0); 213 KASSERT(((uintptr_t)dp32 & 3) == 0); 214 215 lbc_lock(sc->sc_obio); 216 lbc_write_4(sc->sc_obio, FCR, len); 217 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_RBW, FIR_OP0)); 218 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs); 219 220 while (lbc_read_4(sc->sc_obio, LTESR) & LTESR_CC) { 221 DELAY(1); 222 } 223 for (offset = 0; len >= 4; offset += 4, len -= 4) { 224 *dp32++ = fcm_buf_read(sc, offset); 225 } 226 if (len) { 227 const uint32_t mask = ~0 >> (8 * len); 228 const uint32_t data = fcm_buf_read(sc, offset); 229 *dp32 = (data & ~mask) | (*dp32 & mask); 230 } 231 lbc_unlock(sc->sc_obio); 232 } 233 234 void 235 pq3nandfcm_write_buf(device_t self, const void *buf, size_t len) 236 { 237 struct pq3nandfcm_softc * const sc = device_private(self); 238 bus_size_t offset = 0; 239 const uint32_t *dp32 = buf; 240 241 KASSERT(len < 4096); 242 KASSERT((len & 3) == 0); 243 KASSERT(((uintptr_t)dp32 & 3) == 0); 244 245 lbc_lock(sc->sc_obio); 246 lbc_write_4(sc->sc_obio, FCR, len); 247 248 /* 249 * First we need to copy to the FCM buffer. There will be a few extra 250 * bytes at the end but we don't care. 251 */ 252 for (len = roundup2(len, 4); offset < len; offset += 4, dp32++) { 253 fcm_buf_write(sc, offset, *dp32); 254 } 255 256 /* 257 * W 258 */ 259 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_WB, FIR_OP0)); 260 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs); 261 while (lbc_read_4(sc->sc_obio, LTESR) & LTESR_CC) { 262 DELAY(1); 263 } 264 lbc_unlock(sc->sc_obio); 265 } 266