1 /* $NetBSD: pq3gpio.c,v 1.12 2020/07/06 09:34:16 rin Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #define GLOBAL_PRIVATE 38 #define GPIO_PRIVATE 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.12 2020/07/06 09:34:16 rin Exp $"); 42 43 #ifdef _KERNEL_OPT 44 #include "opt_mpc85xx.h" 45 #endif 46 47 #include <sys/param.h> 48 #include <sys/cpu.h> 49 #include <sys/device.h> 50 #include <sys/tty.h> 51 #include <sys/kmem.h> 52 #include <sys/gpio.h> 53 #include <sys/bitops.h> 54 55 #include "ioconf.h" 56 57 #include <sys/intr.h> 58 #include <sys/bus.h> 59 60 #include <dev/gpio/gpiovar.h> 61 62 #include <powerpc/booke/cpuvar.h> 63 #include <powerpc/booke/spr.h> 64 #include <powerpc/booke/e500var.h> 65 #include <powerpc/booke/e500reg.h> 66 67 struct pq3gpio_group { 68 struct gpio_chipset_tag gc_tag; 69 gpio_pin_t gc_pins[32]; 70 bus_space_tag_t gc_bst; 71 bus_space_handle_t gc_bsh; 72 bus_size_t gc_reg; 73 }; 74 75 struct pq3gpio_softc { 76 device_t sc_dev; 77 bus_space_tag_t sc_bst; 78 bus_space_handle_t sc_bsh; 79 SIMPLEQ_HEAD(,pq3gpio_group) sc_gpios; 80 }; 81 82 static int 83 pq3gpio_pin_read(void *v, int num) 84 { 85 struct pq3gpio_group * const gc = v; 86 87 uint32_t data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg); 88 89 return (data >> (gc->gc_pins[num].pin_num ^ 31)) & 1; 90 } 91 92 static void 93 pq3gpio_pin_write(void *v, int num, int val) 94 { 95 struct pq3gpio_group * const gc = v; 96 const u_int mask = 1 << (gc->gc_pins[num].pin_num ^ 31); 97 98 val = val ? mask : 0; 99 u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg); 100 if ((data & mask) != val) { 101 data = (data & ~mask) | val; 102 bus_space_write_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg, data); 103 } 104 } 105 106 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8544) 107 static void 108 pq3gpio_null_pin_ctl(void *v, int num, int ctl) 109 { 110 } 111 #endif 112 113 #if defined(P1025) 114 /* 115 * P1025 has controllable input/output pins 116 */ 117 static void 118 pq3gpio_pin_ctl(void *v, int num, int ctl) 119 { 120 struct pq3gpio_group * const gc = v; 121 const size_t shift = gc->gc_pins[num].pin_num ^ 31; 122 123 uint64_t old_dir = 124 ((uint64_t)bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR1) << 32) 125 | (bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR2) << 0); 126 127 uint32_t dir = 0; 128 switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 129 case GPIO_PIN_INPUT|GPIO_PIN_OUTPUT: dir = CPDIR_INOUT; break; 130 case GPIO_PIN_OUTPUT: dir = CPDIR_OUT; break; 131 case GPIO_PIN_INPUT: dir = CPDIR_INOUT; break; 132 case 0: dir = CPDIR_DIS; break; 133 } 134 135 uint64_t new_dir = (old_dir & (3ULL << (2 * shift))) 136 | ((uint64_t)dir << (2 * shift)); 137 138 if ((uint32_t)old_dir != (uint32_t)new_dir) 139 bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR2, 140 (uint32_t)new_dir); 141 new_dir >>= 32; 142 old_dir >>= 32; 143 if ((uint32_t)old_dir != (uint32_t)new_dir) 144 bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR1, 145 (uint32_t)new_dir); 146 147 /* 148 * Now handle opendrain 149 */ 150 uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPODR); 151 uint32_t new_odr = old_odr; 152 uint32_t odr_mask = 1UL << shift; 153 154 if (ctl & GPIO_PIN_OPENDRAIN) { 155 new_odr |= odr_mask; 156 } else { 157 new_odr &= ~odr_mask; 158 } 159 160 if (old_odr != new_odr) 161 bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPODR, new_odr); 162 } 163 #endif 164 165 #if defined(MPC8536) || defined(P2020) || defined(P1023) 166 /* 167 * MPC8536 / P20x0 / P1023 have controllable input/output pins 168 */ 169 static void 170 pq3gpio_pin_ctl(void *v, int num, int ctl) 171 { 172 struct pq3gpio_group * const gc = v; 173 const u_int mask = 1 << (gc->gc_pins[num].pin_num ^ 31); 174 175 uint32_t old_dir = bus_space_read_4(gc->gc_bst, gc->gc_bsh, GPDIR); 176 uint32_t new_dir = old_dir; 177 switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 178 case GPIO_PIN_OUTPUT: new_dir |= mask; break; 179 case GPIO_PIN_INPUT: new_dir &= ~mask; break; 180 default: return; 181 } 182 if (old_dir != new_dir) 183 bus_space_write_4(gc->gc_bst, gc->gc_bsh, GPDIR, new_dir); 184 185 /* 186 * Now handle opendrain 187 */ 188 uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, GPODR); 189 uint32_t new_odr = old_odr; 190 191 if (ctl & GPIO_PIN_OPENDRAIN) { 192 new_odr |= mask; 193 } else { 194 new_odr &= ~mask; 195 } 196 197 if (old_odr != new_odr) 198 bus_space_write_4(gc->gc_bst, gc->gc_bsh, GPODR, new_odr); 199 } 200 #endif 201 202 static void 203 pq3gpio_group_create(device_t self, bus_space_tag_t bst, bus_space_handle_t bsh, 204 bus_size_t reg, uint32_t pinmask, int pincaps, 205 void (*pin_ctl)(void *, int, int)) 206 { 207 struct pq3gpio_group * const gc = kmem_zalloc(sizeof(*gc), KM_SLEEP); 208 209 gc->gc_bst = bst; 210 gc->gc_bsh = bsh; 211 gc->gc_reg = reg; 212 gc->gc_tag.gp_cookie = gc; 213 #if 0 214 gc->gc_tag.gp_gc_open = pq3gpio_gc_open; 215 gc->gc_tag.gp_gc_close = pq3gpio_gc_close; 216 #endif 217 gc->gc_tag.gp_pin_read = pq3gpio_pin_read; 218 gc->gc_tag.gp_pin_write = pq3gpio_pin_write; 219 gc->gc_tag.gp_pin_ctl = pin_ctl; 220 221 u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, reg); 222 u_int mask = __BIT(31); 223 gpio_pin_t *pin = gc->gc_pins; 224 for (u_int i = 0; mask != 0; i++, mask >>= 1) { 225 if (mask & pinmask) { 226 pin->pin_num = i; 227 pin->pin_caps = pincaps; 228 pin->pin_flags = pincaps; 229 pin->pin_state = (data & mask) != 0; 230 pin++; 231 } 232 } 233 234 struct gpiobus_attach_args gba = { 235 .gba_gc = &gc->gc_tag, 236 .gba_pins = gc->gc_pins, 237 .gba_npins = pin - gc->gc_pins, 238 }; 239 240 config_found_ia(self, "gpiobus", &gba, gpiobus_print); 241 } 242 243 #ifdef MPC8536 244 static void 245 pq3gpio_mpc8536_attach(device_t self, bus_space_tag_t bst, 246 bus_space_handle_t bsh, u_int svr) 247 { 248 static const uint8_t gpio2pmuxcr_map[] = { 249 [0] = ilog2(PMUXCR_PCI_REQGNT3), 250 [1] = ilog2(PMUXCR_PCI_REQGNT4), 251 [2] = ilog2(PMUXCR_PCI_REQGNT3), 252 [3] = ilog2(PMUXCR_PCI_REQGNT4), 253 [4] = ilog2(PMUXCR_SDHC_CD), 254 [5] = ilog2(PMUXCR_SDHC_WP), 255 [6] = ilog2(PMUXCR_USB1), 256 [7] = ilog2(PMUXCR_USB1), 257 [8] = ilog2(PMUXCR_USB2), 258 [9] = ilog2(PMUXCR_USB2), 259 [10] = ilog2(PMUXCR_DMA0), 260 [11] = ilog2(PMUXCR_DMA1), 261 [12] = ilog2(PMUXCR_DMA0), 262 [13] = ilog2(PMUXCR_DMA1), 263 [14] = ilog2(PMUXCR_DMA0), 264 [15] = ilog2(PMUXCR_DMA1), 265 }; 266 267 uint32_t pinmask = 0xffff0000; /* assume all bits are valid */ 268 uint32_t gpiomask = __BIT(31); 269 size_t pincnt = 16; 270 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR); 271 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); 272 i++, gpiomask >>= 1) { 273 if (pmuxcr & __BIT(gpio2pmuxcr_map[i])) { 274 pinmask &= ~gpiomask; 275 pincnt--; 276 } 277 } 278 279 /* 280 * Create GPIO pin groups 281 */ 282 aprint_normal_dev(self, "%zu input/output/opendrain pins\n", 283 pincnt); 284 pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask, 285 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN, 286 pq3gpio_pin_ctl); 287 } 288 #endif /* MPC8536 */ 289 290 #ifdef MPC8544 291 static void 292 pq3gpio_mpc8544_attach(device_t self, bus_space_tag_t bst, 293 bus_space_handle_t bsh, u_int svr) 294 { 295 /* 296 * Enable GPOUT 297 */ 298 uint32_t gpiocr = bus_space_read_4(bst, bsh, GPIOCR); 299 gpiocr |= GPIOCR_GPOUT; 300 bus_space_write_4(bst, bsh, GPIOCR, gpiocr); 301 302 aprint_normal_dev(self, "8 input pins, 8 output pins\n"); 303 304 /* 305 * Create GPIO pin groups 306 */ 307 pq3gpio_group_create(self, bst, bsh, GPINDR, 0xff000000, 308 GPIO_PIN_INPUT, pq3gpio_null_pin_ctl); 309 pq3gpio_group_create(self, bst, bsh, GPOUTDR, 0xff000000, 310 GPIO_PIN_OUTPUT, pq3gpio_null_pin_ctl); 311 } 312 #endif /* MPC8544 */ 313 314 #if defined(MPC8548) || defined(MPC8555) 315 static void 316 pq3gpio_mpc8548_attach(device_t self, bus_space_tag_t bst, 317 bus_space_handle_t bsh, u_int svr) 318 { 319 const uint32_t pordevsr = bus_space_read_4(bst, bsh, PORDEVSR); 320 const uint32_t devdisr = bus_space_read_4(bst, bsh, DEVDISR); 321 uint32_t gpiocr = bus_space_read_4(bst, bsh, GPIOCR); 322 323 uint32_t inmask = 0; 324 uint32_t outmask = 0; 325 326 size_t ipins = 0; 327 size_t opins = 0; 328 329 aprint_normal_dev(self, "GPIOCR %#x, DEVDISR %#x, PORDEVSR %#x\n", 330 gpiocr, devdisr, pordevsr); 331 aprint_normal_dev(self, "GPINDR %#x, GPOUTDR %#x, GPPORCR %#x\n", 332 bus_space_read_4(bst, bsh, GPINDR), 333 bus_space_read_4(bst, bsh, GPOUTDR), 334 bus_space_read_4(bst, bsh, GPPORCR)); 335 336 /* 337 * Use PCI2 AD[15:0] as GPIO if PCI2 is disabled and 338 * PCI1 is either disabled or not 64bits wide. 339 */ 340 if ((devdisr & DEVDISR_PCI2) && 341 ((devdisr & DEVDISR_PCI1) || (pordevsr & PORDEVSR_PCI32))) { 342 gpiocr |= GPIOCR_PCIOUT; 343 gpiocr |= GPIOCR_PCIIN; 344 outmask |= 0x00ff0000; 345 inmask |= 0x00ff0000; 346 opins += 8; 347 ipins += 8; 348 } 349 if (devdisr & DEVDISR_TSEC2) { 350 gpiocr |= GPIOCR_TX2; 351 gpiocr |= GPIOCR_RX2; 352 outmask |= 0xff000000; 353 inmask |= 0xff000000; 354 opins += 8; 355 ipins += 8; 356 } 357 if (svr != (SVR_MPC8555v1 >> 16)) { 358 gpiocr |= GPIOCR_GPOUT; 359 outmask |= 0x000000ff; 360 opins += 8; 361 } 362 #if 1 363 aprint_normal_dev(self, "GPIOCR: %#x\n", gpiocr); 364 #else 365 bus_space_write_4(bst, bsh, GPIOCR, gpiocr); 366 #endif 367 368 /* 369 * Create GPIO pin groups 370 */ 371 aprint_normal_dev(self, "%zu input pins, %zu output pins\n", 372 ipins, opins); 373 374 if (inmask) 375 pq3gpio_group_create(self, bst, bsh, GPINDR, inmask, 376 GPIO_PIN_INPUT, pq3gpio_null_pin_ctl); 377 if (outmask) 378 pq3gpio_group_create(self, bst, bsh, GPOUTDR, outmask, 379 GPIO_PIN_OUTPUT, pq3gpio_null_pin_ctl); 380 } 381 #endif /* MPC8548 */ 382 383 #ifdef P1025 384 static void 385 pq3gpio_p1025_attach(device_t self, bus_space_tag_t bst, 386 bus_space_handle_t bsh, u_int svr) 387 { 388 static const uint32_t gpio2pmuxcr_map[][4] = { 389 { 0, __BIT(12), 0, PMUXCR_SDHC_WP }, 390 { __BIT(15), __BIT(8), 0, PMUXCR_USB1 }, 391 { __BITS(14,4)|__BIT(16)|__BITS(27,17)|__BIT(30), 392 __BIT(1)|__BITS(3,2), 0, PMUXCR_QE0 }, 393 { __BITS(3,1), 0, 0, PMUXCR_QE3 }, 394 { 0, __BITS(17,14), 0, PMUXCR_QE8 }, 395 { __BIT(29), __BITS(19,18), 0, PMUXCR_QE9 }, 396 { 0, __BITS(22,21), 0, PMUXCR_QE10 }, 397 { 0, __BITS(28,23), 0, PMUXCR_QE11 }, 398 { 0, __BIT(20), 0, PMUXCR_QE12 }, 399 }; 400 401 uint32_t pinmask[3] = { 402 0xffffffff, 0xffffffff, 0xffffffff 403 }; /* assume all bits are valid */ 404 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR); 405 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) { 406 if (pmuxcr & gpio2pmuxcr_map[i][3]) { 407 pinmask[0] &= ~gpio2pmuxcr_map[i][0]; 408 pinmask[1] &= ~gpio2pmuxcr_map[i][1]; 409 pinmask[2] &= ~gpio2pmuxcr_map[i][2]; 410 } 411 } 412 413 /* 414 * Create GPIO pin groups 415 */ 416 for (size_t i = 0; i < 3; i++) { 417 if (pinmask[i]) { 418 bus_space_handle_t bsh2; 419 aprint_normal_dev(self, 420 "gpio[%c]: %zu input/output/opendrain pins\n", 421 "abc"[i], popcount32(pinmask[i])); 422 bus_space_subregion(bst, bsh, CPBASE(i), 0x20, &bsh2); 423 pq3gpio_group_create(self, bst, bsh2, CPDAT, 424 pinmask[0], 425 GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN, 426 pq3gpio_pin_ctl); 427 } 428 } 429 } 430 #endif /* P1025 */ 431 432 #ifdef P2020 433 static void 434 pq3gpio_p20x0_attach(device_t self, bus_space_tag_t bst, 435 bus_space_handle_t bsh, u_int svr) 436 { 437 static const uint32_t gpio2pmuxcr_map[][2] = { 438 { __BIT(8), PMUXCR_SDHC_CD }, 439 { __BIT(9), PMUXCR_SDHC_WP }, 440 /* 441 * These are really two bits but the low bit MBZ so we ignore 442 * it. 443 */ 444 { __BIT(10), PMUXCR_TSEC3_TS }, 445 { __BIT(11), PMUXCR_TSEC3_TS }, 446 }; 447 448 uint32_t pinmask = 0xffff0000; /* assume all bits are valid */ 449 size_t pincnt = 16; 450 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR); 451 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) { 452 if (pmuxcr & gpio2pmuxcr_map[i][1]) { 453 pinmask &= ~gpio2pmuxcr_map[i][0]; 454 pincnt--; 455 } 456 } 457 458 /* 459 * Create GPIO pin groups 460 */ 461 aprint_normal_dev(self, "%zu input/output/opendrain pins\n", 462 pincnt); 463 pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask, 464 GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN, 465 pq3gpio_pin_ctl); 466 } 467 #endif /* P2020 */ 468 469 #ifdef P1023 470 static void 471 pq3gpio_p1023_attach(device_t self, bus_space_tag_t bst, 472 bus_space_handle_t bsh, u_int svr) 473 { 474 static const uint32_t gpio2pmuxcr2_map[][3] = { 475 { __PPCBITS( 0, 1), __PPCBITS( 0, 1), 0 }, /* GPIO_1 */ 476 { __PPCBIT(2), __PPCBITS( 2, 3), 0 }, /* GPUO_2 */ 477 { __PPCBITS( 4, 5), __PPCBITS( 4, 5), 0 }, /* GPUO_3 */ 478 { __PPCBITS( 6, 7), __PPCBITS( 6, 7), 0 }, /* GPUO_4 */ 479 { __PPCBITS( 8, 9), __PPCBITS( 8, 9), 0 }, /* GPUO_5 */ 480 { __PPCBITS(10,11), __PPCBITS(10,11), 0 }, /* GPUO_6 */ 481 { __PPCBITS(12,13), __PPCBITS(12,13), 0 }, /* GPUO_7 */ 482 { __PPCBITS(14,15), __PPCBITS(14,15), 0 }, /* GPUO_8 */ 483 { __PPCBIT(3), __PPCBITS(18,19), 0 }, /* GPUO_9 */ 484 }; 485 486 uint32_t pinmask = 0xffff0000; /* assume all bits are valid */ 487 size_t pincnt = 16; 488 const uint32_t pmuxcr2 = cpu_read_4(GLOBAL_BASE + PMUXCR2); 489 for (size_t i = 0; i < __arraycount(gpio2pmuxcr2_map); i++) { 490 const uint32_t *map = gpio2pmuxcr2_map[i]; 491 if ((pmuxcr2 & map[1]) != map[2]) { 492 pinmask &= ~map[0]; 493 pincnt--; 494 } 495 } 496 497 /* 498 * Create GPIO pin groups 499 */ 500 aprint_normal_dev(self, "%zu input/output/opendrain pins\n", pincnt); 501 pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask, 502 GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN, pq3gpio_pin_ctl); 503 } 504 #endif /* P1023 */ 505 506 static const struct pq3gpio_svr_info { 507 uint16_t si_svr; 508 void (*si_attach)(device_t, bus_space_tag_t, bus_space_handle_t, u_int); 509 bus_addr_t si_base; 510 bus_size_t si_size; 511 } pq3gpio_svrs[] = { 512 #ifdef MPC8548 513 { SVR_MPC8548v2 >> 16, pq3gpio_mpc8548_attach, 514 GLOBAL_BASE, GLOBAL_SIZE }, 515 #endif 516 #ifdef MPC8555 517 { SVR_MPC8555v1 >> 16, pq3gpio_mpc8548_attach, 518 GLOBAL_BASE, GLOBAL_SIZE }, 519 #endif 520 #ifdef MPC8544 521 { SVR_MPC8544v1 >> 16, pq3gpio_mpc8544_attach, 522 GLOBAL_BASE, GLOBAL_SIZE }, 523 #endif 524 #ifdef MPC8536 525 { SVR_MPC8536v1 >> 16, pq3gpio_mpc8536_attach, 526 GPIO_BASE, GPIO_SIZE }, 527 #endif 528 #ifdef P1025 529 { SVR_P1025v1 >> 16, pq3gpio_p1025_attach, 530 GLOBAL_BASE, GLOBAL_SIZE }, 531 #endif 532 #ifdef P2020 533 { SVR_P2020v2 >> 16, pq3gpio_p20x0_attach, 534 GPIO_BASE, GPIO_SIZE }, 535 #endif 536 #ifdef P1023 537 { SVR_P1023v1 >> 16, pq3gpio_p1023_attach, 538 GPIO_BASE, GPIO_SIZE }, 539 #endif 540 }; 541 542 void 543 pq3gpio_attach(device_t parent, device_t self, void *aux) 544 { 545 struct mainbus_attach_args * const ma = aux; 546 bus_space_tag_t bst = ma->ma_memt; 547 bus_space_handle_t bsh; 548 549 const uint16_t svr = e500_get_svr(); 550 for (u_int i = 0; i < __arraycount(pq3gpio_svrs); i++) { 551 const struct pq3gpio_svr_info * const si = &pq3gpio_svrs[i]; 552 if (si->si_svr == svr) { 553 int error = bus_space_map(bst, si->si_base, 554 si->si_size, 0, &bsh); 555 if (error) { 556 aprint_error_dev(self, 557 "can't map global registers for gpio: %d\n", 558 error); 559 return; 560 } 561 (*si->si_attach)(self, bst, bsh, svr); 562 return; 563 } 564 } 565 aprint_normal_dev(self, 566 "0 input groups, 0 output groups (unknown svr %#x)\n", 567 svr); 568 } 569