1 /* $NetBSD: asc_ioasic.c,v 1.6 2000/03/06 03:09:43 mhitch Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 40 __KERNEL_RCSID(0, "$NetBSD: asc_ioasic.c,v 1.6 2000/03/06 03:09:43 mhitch Exp $"); 41 42 #include <sys/types.h> 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 55 #include <dev/ic/ncr53c9xreg.h> 56 #include <dev/ic/ncr53c9xvar.h> 57 58 #include <dev/tc/tcvar.h> 59 #include <dev/tc/ioasicvar.h> 60 #include <dev/tc/ioasicreg.h> 61 62 struct asc_softc { 63 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 64 bus_space_tag_t sc_bst; 65 bus_space_handle_t sc_bsh; 66 bus_space_handle_t sc_scsi_bsh; 67 bus_dma_tag_t sc_dmat; 68 bus_dmamap_t sc_dmamap; 69 caddr_t *sc_dmaaddr; 70 size_t *sc_dmalen; 71 size_t sc_dmasize; 72 int sc_active; /* DMA active ? */ 73 int sc_ispullup; /* DMA into main memory? */ 74 }; 75 76 static int asc_ioasic_match __P((struct device *, struct cfdata *, void *)); 77 static void asc_ioasic_attach __P((struct device *, struct device *, void *)); 78 79 struct cfattach xasc_ioasic_ca = { 80 sizeof(struct asc_softc), asc_ioasic_match, asc_ioasic_attach 81 }; 82 83 static struct scsipi_device asc_ioasic_dev = { 84 NULL, /* Use default error handler */ 85 NULL, /* have a queue, served by this */ 86 NULL, /* have no async handler */ 87 NULL, /* Use default 'done' routine */ 88 }; 89 90 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 91 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 92 static int asc_dma_isintr __P((struct ncr53c9x_softc *sc)); 93 static void asc_ioasic_reset __P((struct ncr53c9x_softc *)); 94 static int asc_ioasic_intr __P((struct ncr53c9x_softc *)); 95 static int asc_ioasic_setup __P((struct ncr53c9x_softc *, 96 caddr_t *, size_t *, int, size_t *)); 97 static void asc_ioasic_go __P((struct ncr53c9x_softc *)); 98 static void asc_ioasic_stop __P((struct ncr53c9x_softc *)); 99 static int asc_dma_isactive __P((struct ncr53c9x_softc *)); 100 static void asc_clear_latched_intr __P((struct ncr53c9x_softc *)); 101 102 static struct ncr53c9x_glue asc_ioasic_glue = { 103 asc_read_reg, 104 asc_write_reg, 105 asc_dma_isintr, 106 asc_ioasic_reset, 107 asc_ioasic_intr, 108 asc_ioasic_setup, 109 asc_ioasic_go, 110 asc_ioasic_stop, 111 asc_dma_isactive, 112 asc_clear_latched_intr, 113 }; 114 115 static int 116 asc_ioasic_match(parent, cfdata, aux) 117 struct device *parent; 118 struct cfdata *cfdata; 119 void *aux; 120 { 121 struct ioasicdev_attach_args *d = aux; 122 123 if (strncmp("asc", d->iada_modname, TC_ROM_LLEN)) 124 return 0; 125 126 return 1; 127 } 128 129 static void 130 asc_ioasic_attach(parent, self, aux) 131 struct device *parent, *self; 132 void *aux; 133 { 134 struct ioasicdev_attach_args *d = aux; 135 struct asc_softc *asc = (struct asc_softc *)self; 136 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 137 138 /* 139 * Set up glue for MI code early; we use some of it here. 140 */ 141 sc->sc_glue = &asc_ioasic_glue; 142 asc->sc_bst = ((struct ioasic_softc *)parent)->sc_bst; 143 asc->sc_bsh = ((struct ioasic_softc *)parent)->sc_bsh; 144 asc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat; 145 if (bus_space_subregion(asc->sc_bst, 146 asc->sc_bsh, 147 IOASIC_SLOT_12_START, 0x100, &asc->sc_scsi_bsh)) { 148 printf("%s: unable to map device\n", sc->sc_dev.dv_xname); 149 return; 150 } 151 152 sc->sc_id = 7; 153 sc->sc_freq = 25000000; 154 155 /* gimme Mhz */ 156 sc->sc_freq /= 1000000; 157 158 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_BIO, 159 (int (*)(void *))ncr53c9x_intr, sc); 160 161 /* 162 * XXX More of this should be in ncr53c9x_attach(), but 163 * XXX should we really poke around the chip that much in 164 * XXX the MI code? Think about this more... 165 */ 166 167 /* 168 * Set up static configuration info. 169 */ 170 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 171 sc->sc_cfg2 = NCRCFG2_SCSI2; 172 sc->sc_cfg3 = 0; 173 sc->sc_rev = NCR_VARIANT_NCR53C94; 174 175 /* 176 * XXX minsync and maxxfer _should_ be set up in MI code, 177 * XXX but it appears to have some dependency on what sort 178 * XXX of DMA we're hooked up to, etc. 179 */ 180 181 /* 182 * This is the value used to start sync negotiations 183 * Note that the NCR register "SYNCTP" is programmed 184 * in "clocks per byte", and has a minimum value of 4. 185 * The SCSI period used in negotiation is one-fourth 186 * of the time (in nanoseconds) needed to transfer one byte. 187 * Since the chip's clock is given in MHz, we have the following 188 * formula: 4 * period = (1000 / freq) * 4 189 */ 190 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4 ; 191 sc->sc_maxxfer = 64 * 1024; 192 193 /* Do the common parts of attachment. */ 194 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 195 sc->sc_adapter.scsipi_minphys = minphys; 196 ncr53c9x_attach(sc, &asc_ioasic_dev); 197 } 198 199 void 200 asc_ioasic_reset(sc) 201 struct ncr53c9x_softc *sc; 202 { 203 struct asc_softc *asc = (struct asc_softc *)sc; 204 u_int32_t ssr; 205 206 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 207 ssr &= ~IOASIC_CSR_DMAEN_SCSI; 208 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 209 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, 0); 210 asc->sc_active = 0; 211 } 212 213 #define SCRDEBUG(x) 214 215 static int 216 asc_ioasic_intr(sc) 217 struct ncr53c9x_softc *sc; 218 { 219 struct asc_softc *asc = (struct asc_softc *)sc; 220 int trans, resid; 221 u_int tcl, tcm, ssr, scr, intr; 222 223 if (asc->sc_active == 0) 224 panic("dmaintr: DMA wasn't active"); 225 226 #define IOASIC_ASC_ERRORS \ 227 (IOASIC_INTR_SCSI_PTR_LOAD|IOASIC_INTR_SCSI_OVRUN|IOASIC_INTR_SCSI_READ_E) 228 /* 229 * When doing polled I/O, the SCSI bits in the interrupt register won't 230 * get cleared by the interrupt processing. This will cause the DMA 231 * address registers to not load on the next DMA transfer. 232 * Check for these bits here, and clear them if needed. 233 */ 234 intr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR); 235 if ((intr & IOASIC_ASC_ERRORS) != 0) 236 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR, 237 intr & ~IOASIC_ASC_ERRORS); 238 239 /* DMA has stopped */ 240 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 241 ssr &= ~IOASIC_CSR_DMAEN_SCSI; 242 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 243 asc->sc_active = 0; 244 245 if (asc->sc_dmasize == 0) { 246 /* A "Transfer Pad" operation completed */ 247 tcl = NCR_READ_REG(sc, NCR_TCL); 248 tcm = NCR_READ_REG(sc, NCR_TCM); 249 NCR_DMA(("ioasic_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 250 tcl | (tcm << 8), tcl, tcm)); 251 return 0; 252 } 253 254 resid = 0; 255 if (!asc->sc_ispullup && 256 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 257 NCR_DMA(("ioasic_intr: empty FIFO of %d ", resid)); 258 DELAY(1); 259 } 260 261 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 262 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 263 264 trans = asc->sc_dmasize - resid; 265 if (trans < 0) { /* transferred < 0 ? */ 266 printf("ioasic_intr: xfer (%d) > req (%d)\n", 267 trans, asc->sc_dmasize); 268 trans = asc->sc_dmasize; 269 } 270 NCR_DMA(("ioasic_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 271 tcl, tcm, trans, resid)); 272 273 scr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR); 274 if (asc->sc_ispullup && scr != 0) { 275 u_int32_t ptr; 276 u_int16_t *p; 277 union { 278 u_int32_t sdr[2]; 279 u_int16_t half[4]; 280 } scratch; 281 scratch.sdr[0] = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 282 IOASIC_SCSI_SDR0); 283 scratch.sdr[1] = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 284 IOASIC_SCSI_SDR1); 285 ptr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 286 IOASIC_SCSI_DMAPTR); 287 ptr = (ptr >> 3) & 0x1ffffffc; 288 SCRDEBUG(("SCSI_SCR -> %x, DMAPTR: %p\n", scr, (void *)ptr)); 289 p = (u_int16_t *)MIPS_PHYS_TO_KSEG0(ptr); 290 /* 291 * scr 292 * 1 -> half[0] 293 * 2 -> half[0] + half[1] 294 * 3 -> half[0] + half[1] + half[2] 295 */ 296 scr &= IOASIC_SCR_WORD; 297 p[0] = scratch.half[0]; 298 if (scr > 1) 299 p[1] = scratch.half[1]; 300 if (scr > 2) 301 p[2] = scratch.half[2]; 302 } 303 304 *asc->sc_dmalen -= trans; 305 *asc->sc_dmaaddr += trans; 306 307 return 0; 308 } 309 310 #define TWOPAGE(a) (NBPG*2 - ((a) & (NBPG-1))) 311 312 int 313 asc_ioasic_setup(sc, addr, len, datain, dmasize) 314 struct ncr53c9x_softc *sc; 315 caddr_t *addr; 316 size_t *len; 317 int datain; 318 size_t *dmasize; 319 { 320 struct asc_softc *asc = (struct asc_softc *)sc; 321 u_int32_t ssr, scr; 322 size_t size; 323 vaddr_t cp; 324 paddr_t ptr0, ptr1; 325 extern paddr_t kvtophys __P((vaddr_t)); 326 327 asc->sc_dmaaddr = addr; 328 asc->sc_dmalen = len; 329 asc->sc_ispullup = datain; 330 331 NCR_DMA(("ioasic_setup: start %d@%p %s\n", 332 *asc->sc_dmalen, *asc->sc_dmaaddr, datain ? "IN" : "OUT")); 333 334 /* upto two 4KB pages */ 335 size = min(*dmasize, TWOPAGE((size_t)*addr)); 336 *dmasize = asc->sc_dmasize = size; 337 338 NCR_DMA(("ioasic_setup: dmasize = %d\n", asc->sc_dmasize)); 339 340 /* stop DMA engine first */ 341 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 342 ssr &= ~IOASIC_CSR_DMAEN_SCSI; 343 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 344 345 /* If R4K, writeback and invalidate the buffer */ 346 if (CPUISMIPS3) 347 mips3_HitFlushDCache((vaddr_t)*addr, size); 348 349 cp = (vaddr_t)*addr; 350 if ((cp & 7) == 0) 351 scr = 0; 352 else { 353 u_int32_t *p; 354 355 p = (u_int32_t *)(cp & ~7); 356 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 357 IOASIC_SCSI_SDR0, p[0]); 358 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 359 IOASIC_SCSI_SDR1, p[1]); 360 361 scr = (cp >> 1) & 3; 362 cp &= ~7; 363 if (asc->sc_ispullup == 0) { 364 scr |= 4; 365 cp += 8; 366 } 367 SCRDEBUG(("SCSI_SCR <- %x, DMAPTR: %p\n", scr, (void *)kvtophys(cp))); 368 } 369 ptr0 = kvtophys(cp); 370 cp = mips_trunc_page(cp + NBPG); 371 ptr1 = ((vaddr_t)*addr + size > cp) ? kvtophys(cp) : ~0; 372 373 /* If not R4K, need to invalidate cache lines for physical segments */ 374 if (!CPUISMIPS3 && datain) { 375 if (ptr1 == ~0) 376 MachFlushDCache(MIPS_PHYS_TO_KSEG0(ptr0), size); 377 else { 378 int size0 = NBPG - (ptr0 & (NBPG - 1)); 379 int size1 = size - size0; 380 MachFlushDCache(MIPS_PHYS_TO_KSEG0(ptr0), size0); 381 MachFlushDCache(MIPS_PHYS_TO_KSEG0(ptr1), size1); 382 } 383 } 384 385 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, scr); 386 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 387 IOASIC_SCSI_DMAPTR, IOASIC_DMA_ADDR(ptr0)); 388 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 389 IOASIC_SCSI_NEXTPTR, IOASIC_DMA_ADDR(ptr1)); 390 return 0; 391 } 392 393 void 394 asc_ioasic_go(sc) 395 struct ncr53c9x_softc *sc; 396 { 397 struct asc_softc *asc = (struct asc_softc *)sc; 398 u_int32_t ssr; 399 400 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 401 if (asc->sc_ispullup) 402 ssr |= IOASIC_CSR_SCSI_DIR; 403 else { 404 /* ULTRIX does in this way */ 405 ssr &= ~IOASIC_CSR_SCSI_DIR; 406 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 407 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 408 } 409 ssr |= IOASIC_CSR_DMAEN_SCSI; 410 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 411 asc->sc_active = 1; 412 } 413 414 /* NEVER CALLED BY MI 53C9x ENGINE INDEED */ 415 void 416 asc_ioasic_stop(sc) 417 struct ncr53c9x_softc *sc; 418 { 419 } 420 421 static u_char 422 asc_read_reg(sc, reg) 423 struct ncr53c9x_softc *sc; 424 int reg; 425 { 426 struct asc_softc *asc = (struct asc_softc *)sc; 427 u_int32_t v; 428 429 v = bus_space_read_4(asc->sc_bst, 430 asc->sc_scsi_bsh, reg * sizeof(u_int32_t)); 431 432 return v & 0xff; 433 } 434 435 static void 436 asc_write_reg(sc, reg, val) 437 struct ncr53c9x_softc *sc; 438 int reg; 439 u_char val; 440 { 441 struct asc_softc *asc = (struct asc_softc *)sc; 442 443 bus_space_write_4(asc->sc_bst, 444 asc->sc_scsi_bsh, reg * sizeof(u_int32_t), val); 445 } 446 447 static int 448 asc_dma_isintr(sc) 449 struct ncr53c9x_softc *sc; 450 { 451 return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT); 452 } 453 454 static int 455 asc_dma_isactive(sc) 456 struct ncr53c9x_softc *sc; 457 { 458 struct asc_softc *asc = (struct asc_softc *)sc; 459 460 return asc->sc_active; 461 } 462 463 static void 464 asc_clear_latched_intr(sc) 465 struct ncr53c9x_softc *sc; 466 { 467 } 468