1 /* $NetBSD: asc_ioasic.c,v 1.14 2002/10/02 04:15:10 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 40 __KERNEL_RCSID(0, "$NetBSD: asc_ioasic.c,v 1.14 2002/10/02 04:15:10 thorpej Exp $"); 41 42 #include <sys/types.h> 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 55 #include <dev/ic/ncr53c9xreg.h> 56 #include <dev/ic/ncr53c9xvar.h> 57 58 #include <dev/tc/tcvar.h> 59 #include <dev/tc/ioasicvar.h> 60 #include <dev/tc/ioasicreg.h> 61 62 struct asc_softc { 63 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 64 bus_space_tag_t sc_bst; /* bus space tag */ 65 bus_space_handle_t sc_bsh; /* bus space handle */ 66 bus_space_handle_t sc_scsi_bsh; /* ASC register handle */ 67 bus_dma_tag_t sc_dmat; /* bus dma tag */ 68 bus_dmamap_t sc_dmamap; /* bus dmamap */ 69 caddr_t *sc_dmaaddr; 70 size_t *sc_dmalen; 71 size_t sc_dmasize; 72 unsigned sc_flags; 73 #define ASC_ISPULLUP 0x0001 74 #define ASC_DMAACTIVE 0x0002 75 #define ASC_MAPLOADED 0x0004 76 }; 77 78 static int asc_ioasic_match __P((struct device *, struct cfdata *, void *)); 79 static void asc_ioasic_attach __P((struct device *, struct device *, void *)); 80 81 CFATTACH_DECL(asc_ioasic, sizeof(struct asc_softc), 82 asc_ioasic_match, asc_ioasic_attach, NULL, NULL); 83 84 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 85 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 86 static int asc_dma_isintr __P((struct ncr53c9x_softc *sc)); 87 static void asc_ioasic_reset __P((struct ncr53c9x_softc *)); 88 static int asc_ioasic_intr __P((struct ncr53c9x_softc *)); 89 static int asc_ioasic_setup __P((struct ncr53c9x_softc *, 90 caddr_t *, size_t *, int, size_t *)); 91 static void asc_ioasic_go __P((struct ncr53c9x_softc *)); 92 static void asc_ioasic_stop __P((struct ncr53c9x_softc *)); 93 static int asc_dma_isactive __P((struct ncr53c9x_softc *)); 94 static void asc_clear_latched_intr __P((struct ncr53c9x_softc *)); 95 96 static struct ncr53c9x_glue asc_ioasic_glue = { 97 asc_read_reg, 98 asc_write_reg, 99 asc_dma_isintr, 100 asc_ioasic_reset, 101 asc_ioasic_intr, 102 asc_ioasic_setup, 103 asc_ioasic_go, 104 asc_ioasic_stop, 105 asc_dma_isactive, 106 asc_clear_latched_intr, 107 }; 108 109 static int 110 asc_ioasic_match(parent, cfdata, aux) 111 struct device *parent; 112 struct cfdata *cfdata; 113 void *aux; 114 { 115 struct ioasicdev_attach_args *d = aux; 116 117 if (strncmp("asc", d->iada_modname, TC_ROM_LLEN)) 118 return 0; 119 120 return 1; 121 } 122 123 static void 124 asc_ioasic_attach(parent, self, aux) 125 struct device *parent, *self; 126 void *aux; 127 { 128 struct ioasicdev_attach_args *d = aux; 129 struct asc_softc *asc = (struct asc_softc *)self; 130 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 131 132 /* 133 * Set up glue for MI code early; we use some of it here. 134 */ 135 sc->sc_glue = &asc_ioasic_glue; 136 asc->sc_bst = ((struct ioasic_softc *)parent)->sc_bst; 137 asc->sc_bsh = ((struct ioasic_softc *)parent)->sc_bsh; 138 if (bus_space_subregion(asc->sc_bst, asc->sc_bsh, 139 IOASIC_SLOT_12_START, 0x100, &asc->sc_scsi_bsh)) { 140 printf(": failed to map device registers\n"); 141 return; 142 } 143 asc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat; 144 if (bus_dmamap_create(asc->sc_dmat, NBPG * 2, 145 2, NBPG, NBPG, BUS_DMA_NOWAIT, &asc->sc_dmamap)) { 146 printf(": failed to create DMA map\n"); 147 return; 148 } 149 150 sc->sc_id = 7; 151 sc->sc_freq = 25000000; 152 153 /* gimme Mhz */ 154 sc->sc_freq /= 1000000; 155 156 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_BIO, 157 ncr53c9x_intr, sc); 158 159 /* 160 * XXX More of this should be in ncr53c9x_attach(), but 161 * XXX should we really poke around the chip that much in 162 * XXX the MI code? Think about this more... 163 */ 164 165 /* 166 * Set up static configuration info. 167 */ 168 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 169 sc->sc_cfg2 = NCRCFG2_SCSI2; 170 sc->sc_cfg3 = 0; 171 sc->sc_rev = NCR_VARIANT_NCR53C94; 172 173 /* 174 * XXX minsync and maxxfer _should_ be set up in MI code, 175 * XXX but it appears to have some dependency on what sort 176 * XXX of DMA we're hooked up to, etc. 177 */ 178 179 /* 180 * This is the value used to start sync negotiations 181 * Note that the NCR register "SYNCTP" is programmed 182 * in "clocks per byte", and has a minimum value of 4. 183 * The SCSI period used in negotiation is one-fourth 184 * of the time (in nanoseconds) needed to transfer one byte. 185 * Since the chip's clock is given in MHz, we have the following 186 * formula: 4 * period = (1000 / freq) * 4 187 */ 188 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4 ; 189 sc->sc_maxxfer = 64 * 1024; 190 191 /* Do the common parts of attachment. */ 192 sc->sc_adapter.adapt_minphys = minphys; 193 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 194 ncr53c9x_attach(sc); 195 } 196 197 void 198 asc_ioasic_reset(sc) 199 struct ncr53c9x_softc *sc; 200 { 201 struct asc_softc *asc = (struct asc_softc *)sc; 202 u_int32_t ssr; 203 204 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 205 ssr &= ~IOASIC_CSR_DMAEN_SCSI; 206 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 207 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, 0); 208 209 if (asc->sc_flags & ASC_MAPLOADED) 210 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 211 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 212 } 213 214 #define TWOPAGE(a) (NBPG*2 - ((a) & (NBPG-1))) 215 216 int 217 asc_ioasic_setup(sc, addr, len, ispullup, dmasize) 218 struct ncr53c9x_softc *sc; 219 caddr_t *addr; 220 size_t *len; 221 int ispullup; 222 size_t *dmasize; 223 { 224 struct asc_softc *asc = (struct asc_softc *)sc; 225 u_int32_t ssr, scr, *p; 226 size_t size; 227 vaddr_t cp; 228 229 NCR_DMA(("%s: start %d@%p,%s\n", sc->sc_dev.dv_xname, 230 *asc->sc_dmalen, *asc->sc_dmaaddr, ispullup ? "IN" : "OUT")); 231 232 /* upto two 4KB pages */ 233 size = min(*dmasize, TWOPAGE((size_t)*addr)); 234 asc->sc_dmaaddr = addr; 235 asc->sc_dmalen = len; 236 asc->sc_dmasize = size; 237 asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 238 *dmasize = size; /* return trimmed transfer size */ 239 240 /* stop DMA engine first */ 241 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 242 ssr &= ~IOASIC_CSR_DMAEN_SCSI; 243 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 244 245 /* have dmamap for the transfering addresses */ 246 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, 247 *addr, size, 248 NULL /* kernel address */, BUS_DMA_NOWAIT)) 249 panic("%s: cannot allocate DMA address", sc->sc_dev.dv_xname); 250 251 /* take care of 8B constraint on starting address */ 252 cp = (vaddr_t)*addr; 253 if ((cp & 7) == 0) { 254 /* comfortably aligned to 8B boundary */ 255 scr = 0; 256 } 257 else { 258 /* truncate to the boundary */ 259 p = (u_int32_t *)(cp & ~7); 260 /* how many 16bit quantities in subject */ 261 scr = (cp & 7) >> 1; 262 /* trim down physical address too */ 263 asc->sc_dmamap->dm_segs[0].ds_addr &= ~7; 264 asc->sc_dmamap->dm_segs[0].ds_len += (cp & 6); 265 if ((asc->sc_flags & ASC_ISPULLUP) == 0) { 266 /* push down to SCSI device */ 267 scr |= 4; 268 /* round up physical address in this case */ 269 asc->sc_dmamap->dm_segs[0].ds_addr += 8; 270 /* don't care excess cache flush */ 271 } 272 /* pack fixup data in SDR0/SDR1 pair and instruct SCR */ 273 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 274 IOASIC_SCSI_SDR0, p[0]); 275 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 276 IOASIC_SCSI_SDR1, p[1]); 277 } 278 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 279 IOASIC_SCSI_DMAPTR, 280 IOASIC_DMA_ADDR(asc->sc_dmamap->dm_segs[0].ds_addr)); 281 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 282 IOASIC_SCSI_NEXTPTR, 283 (asc->sc_dmamap->dm_nsegs == 1) 284 ? ~0 : IOASIC_DMA_ADDR(asc->sc_dmamap->dm_segs[1].ds_addr)); 285 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, scr); 286 287 /* synchronize dmamap contents with memory image */ 288 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 289 0, size, 290 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 291 292 asc->sc_flags |= ASC_MAPLOADED; 293 return 0; 294 } 295 296 void 297 asc_ioasic_go(sc) 298 struct ncr53c9x_softc *sc; 299 { 300 struct asc_softc *asc = (struct asc_softc *)sc; 301 u_int32_t ssr; 302 303 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 304 if (asc->sc_flags & ASC_ISPULLUP) 305 ssr |= IOASIC_CSR_SCSI_DIR; 306 else { 307 /* ULTRIX does in this way */ 308 ssr &= ~IOASIC_CSR_SCSI_DIR; 309 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 310 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 311 } 312 ssr |= IOASIC_CSR_DMAEN_SCSI; 313 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 314 asc->sc_flags |= ASC_DMAACTIVE; 315 } 316 317 static int 318 asc_ioasic_intr(sc) 319 struct ncr53c9x_softc *sc; 320 { 321 struct asc_softc *asc = (struct asc_softc *)sc; 322 int trans, resid; 323 u_int tcl, tcm, ssr, scr, intr; 324 325 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 326 panic("ioasic_intr: DMA wasn't active"); 327 328 #define IOASIC_ASC_ERRORS \ 329 (IOASIC_INTR_SCSI_PTR_LOAD|IOASIC_INTR_SCSI_OVRUN|IOASIC_INTR_SCSI_READ_E) 330 /* 331 * When doing polled I/O, the SCSI bits in the interrupt register won't 332 * get cleared by the interrupt processing. This will cause the DMA 333 * address registers to not load on the next DMA transfer. 334 * Check for these bits here, and clear them if needed. 335 */ 336 intr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR); 337 if ((intr & IOASIC_ASC_ERRORS) != 0) { 338 intr &= ~IOASIC_ASC_ERRORS; 339 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR, intr); 340 } 341 342 /* DMA has stopped */ 343 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 344 ssr &= ~IOASIC_CSR_DMAEN_SCSI; 345 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 346 347 asc->sc_flags &= ~ASC_DMAACTIVE; 348 349 if (asc->sc_dmasize == 0) { 350 /* A "Transfer Pad" operation completed */ 351 tcl = NCR_READ_REG(sc, NCR_TCL); 352 tcm = NCR_READ_REG(sc, NCR_TCM); 353 NCR_DMA(("ioasic_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 354 tcl | (tcm << 8), tcl, tcm)); 355 return 0; 356 } 357 358 resid = 0; 359 if ((asc->sc_flags & ASC_ISPULLUP) == 0 && 360 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 361 NCR_DMA(("ioasic_intr: empty FIFO of %d ", resid)); 362 DELAY(1); 363 } 364 365 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 366 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 367 368 trans = asc->sc_dmasize - resid; 369 if (trans < 0) { /* transferred < 0 ? */ 370 printf("ioasic_intr: xfer (%d) > req (%d)\n", 371 trans, asc->sc_dmasize); 372 trans = asc->sc_dmasize; 373 } 374 NCR_DMA(("ioasic_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 375 tcl, tcm, trans, resid)); 376 377 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 378 0, asc->sc_dmasize, 379 (asc->sc_flags & ASC_ISPULLUP) 380 ? BUS_DMASYNC_POSTREAD 381 : BUS_DMASYNC_POSTWRITE); 382 383 scr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR); 384 if ((asc->sc_flags & ASC_ISPULLUP) && scr != 0) { 385 u_int32_t sdr[2], ptr; 386 387 sdr[0] = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 388 IOASIC_SCSI_SDR0); 389 sdr[1] = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 390 IOASIC_SCSI_SDR1); 391 ptr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 392 IOASIC_SCSI_DMAPTR); 393 ptr = (ptr >> 3) & 0x1ffffffc; 394 /* 395 * scr: 1 -> short[0] 396 * 2 -> short[0] + short[1] 397 * 3 -> short[0] + short[1] + short[2] 398 */ 399 scr &= IOASIC_SCR_WORD; 400 memcpy((void *)MIPS_PHYS_TO_KSEG0(ptr), sdr, scr << 1); 401 } 402 403 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 404 asc->sc_flags &= ~ASC_MAPLOADED; 405 406 *asc->sc_dmalen -= trans; 407 *asc->sc_dmaaddr += trans; 408 409 return 0; 410 } 411 412 413 void 414 asc_ioasic_stop(sc) 415 struct ncr53c9x_softc *sc; 416 { 417 struct asc_softc *asc = (struct asc_softc *)sc; 418 419 if (asc->sc_flags & ASC_MAPLOADED) { 420 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 421 0, asc->sc_dmasize, 422 (asc->sc_flags & ASC_ISPULLUP) 423 ? BUS_DMASYNC_POSTREAD 424 : BUS_DMASYNC_POSTWRITE); 425 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 426 } 427 428 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 429 } 430 431 static u_char 432 asc_read_reg(sc, reg) 433 struct ncr53c9x_softc *sc; 434 int reg; 435 { 436 struct asc_softc *asc = (struct asc_softc *)sc; 437 u_int32_t v; 438 439 v = bus_space_read_4(asc->sc_bst, 440 asc->sc_scsi_bsh, reg * sizeof(u_int32_t)); 441 442 return v & 0xff; 443 } 444 445 static void 446 asc_write_reg(sc, reg, val) 447 struct ncr53c9x_softc *sc; 448 int reg; 449 u_char val; 450 { 451 struct asc_softc *asc = (struct asc_softc *)sc; 452 453 bus_space_write_4(asc->sc_bst, 454 asc->sc_scsi_bsh, reg * sizeof(u_int32_t), val); 455 } 456 457 static int 458 asc_dma_isintr(sc) 459 struct ncr53c9x_softc *sc; 460 { 461 return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT); 462 } 463 464 static int 465 asc_dma_isactive(sc) 466 struct ncr53c9x_softc *sc; 467 { 468 struct asc_softc *asc = (struct asc_softc *)sc; 469 470 return !!(asc->sc_flags & ASC_DMAACTIVE); 471 } 472 473 static void 474 asc_clear_latched_intr(sc) 475 struct ncr53c9x_softc *sc; 476 { 477 } 478