1 /* $NetBSD: asc_ioasic.c,v 1.15 2003/04/02 04:20:32 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 40 __KERNEL_RCSID(0, "$NetBSD: asc_ioasic.c,v 1.15 2003/04/02 04:20:32 thorpej Exp $"); 41 42 #include <sys/types.h> 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <dev/scsipi/scsi_all.h> 51 #include <dev/scsipi/scsipi_all.h> 52 #include <dev/scsipi/scsiconf.h> 53 #include <dev/scsipi/scsi_message.h> 54 55 #include <machine/bus.h> 56 57 #include <dev/ic/ncr53c9xreg.h> 58 #include <dev/ic/ncr53c9xvar.h> 59 60 #include <dev/tc/tcvar.h> 61 #include <dev/tc/ioasicvar.h> 62 #include <dev/tc/ioasicreg.h> 63 64 struct asc_softc { 65 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 66 bus_space_tag_t sc_bst; /* bus space tag */ 67 bus_space_handle_t sc_bsh; /* bus space handle */ 68 bus_space_handle_t sc_scsi_bsh; /* ASC register handle */ 69 bus_dma_tag_t sc_dmat; /* bus dma tag */ 70 bus_dmamap_t sc_dmamap; /* bus dmamap */ 71 caddr_t *sc_dmaaddr; 72 size_t *sc_dmalen; 73 size_t sc_dmasize; 74 unsigned sc_flags; 75 #define ASC_ISPULLUP 0x0001 76 #define ASC_DMAACTIVE 0x0002 77 #define ASC_MAPLOADED 0x0004 78 }; 79 80 static int asc_ioasic_match __P((struct device *, struct cfdata *, void *)); 81 static void asc_ioasic_attach __P((struct device *, struct device *, void *)); 82 83 CFATTACH_DECL(asc_ioasic, sizeof(struct asc_softc), 84 asc_ioasic_match, asc_ioasic_attach, NULL, NULL); 85 86 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 87 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 88 static int asc_dma_isintr __P((struct ncr53c9x_softc *sc)); 89 static void asc_ioasic_reset __P((struct ncr53c9x_softc *)); 90 static int asc_ioasic_intr __P((struct ncr53c9x_softc *)); 91 static int asc_ioasic_setup __P((struct ncr53c9x_softc *, 92 caddr_t *, size_t *, int, size_t *)); 93 static void asc_ioasic_go __P((struct ncr53c9x_softc *)); 94 static void asc_ioasic_stop __P((struct ncr53c9x_softc *)); 95 static int asc_dma_isactive __P((struct ncr53c9x_softc *)); 96 static void asc_clear_latched_intr __P((struct ncr53c9x_softc *)); 97 98 static struct ncr53c9x_glue asc_ioasic_glue = { 99 asc_read_reg, 100 asc_write_reg, 101 asc_dma_isintr, 102 asc_ioasic_reset, 103 asc_ioasic_intr, 104 asc_ioasic_setup, 105 asc_ioasic_go, 106 asc_ioasic_stop, 107 asc_dma_isactive, 108 asc_clear_latched_intr, 109 }; 110 111 static int 112 asc_ioasic_match(parent, cfdata, aux) 113 struct device *parent; 114 struct cfdata *cfdata; 115 void *aux; 116 { 117 struct ioasicdev_attach_args *d = aux; 118 119 if (strncmp("asc", d->iada_modname, TC_ROM_LLEN)) 120 return 0; 121 122 return 1; 123 } 124 125 static void 126 asc_ioasic_attach(parent, self, aux) 127 struct device *parent, *self; 128 void *aux; 129 { 130 struct ioasicdev_attach_args *d = aux; 131 struct asc_softc *asc = (struct asc_softc *)self; 132 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 133 134 /* 135 * Set up glue for MI code early; we use some of it here. 136 */ 137 sc->sc_glue = &asc_ioasic_glue; 138 asc->sc_bst = ((struct ioasic_softc *)parent)->sc_bst; 139 asc->sc_bsh = ((struct ioasic_softc *)parent)->sc_bsh; 140 if (bus_space_subregion(asc->sc_bst, asc->sc_bsh, 141 IOASIC_SLOT_12_START, 0x100, &asc->sc_scsi_bsh)) { 142 printf(": failed to map device registers\n"); 143 return; 144 } 145 asc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat; 146 if (bus_dmamap_create(asc->sc_dmat, PAGE_SIZE * 2, 147 2, PAGE_SIZE, PAGE_SIZE, BUS_DMA_NOWAIT, 148 &asc->sc_dmamap)) { 149 printf(": failed to create DMA map\n"); 150 return; 151 } 152 153 sc->sc_id = 7; 154 sc->sc_freq = 25000000; 155 156 /* gimme Mhz */ 157 sc->sc_freq /= 1000000; 158 159 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_BIO, 160 ncr53c9x_intr, sc); 161 162 /* 163 * XXX More of this should be in ncr53c9x_attach(), but 164 * XXX should we really poke around the chip that much in 165 * XXX the MI code? Think about this more... 166 */ 167 168 /* 169 * Set up static configuration info. 170 */ 171 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 172 sc->sc_cfg2 = NCRCFG2_SCSI2; 173 sc->sc_cfg3 = 0; 174 sc->sc_rev = NCR_VARIANT_NCR53C94; 175 176 /* 177 * XXX minsync and maxxfer _should_ be set up in MI code, 178 * XXX but it appears to have some dependency on what sort 179 * XXX of DMA we're hooked up to, etc. 180 */ 181 182 /* 183 * This is the value used to start sync negotiations 184 * Note that the NCR register "SYNCTP" is programmed 185 * in "clocks per byte", and has a minimum value of 4. 186 * The SCSI period used in negotiation is one-fourth 187 * of the time (in nanoseconds) needed to transfer one byte. 188 * Since the chip's clock is given in MHz, we have the following 189 * formula: 4 * period = (1000 / freq) * 4 190 */ 191 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4 ; 192 sc->sc_maxxfer = 64 * 1024; 193 194 /* Do the common parts of attachment. */ 195 sc->sc_adapter.adapt_minphys = minphys; 196 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 197 ncr53c9x_attach(sc); 198 } 199 200 void 201 asc_ioasic_reset(sc) 202 struct ncr53c9x_softc *sc; 203 { 204 struct asc_softc *asc = (struct asc_softc *)sc; 205 u_int32_t ssr; 206 207 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 208 ssr &= ~IOASIC_CSR_DMAEN_SCSI; 209 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 210 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, 0); 211 212 if (asc->sc_flags & ASC_MAPLOADED) 213 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 214 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 215 } 216 217 #define TWOPAGE(a) (PAGE_SIZE*2 - ((a) & (PAGE_SIZE-1))) 218 219 int 220 asc_ioasic_setup(sc, addr, len, ispullup, dmasize) 221 struct ncr53c9x_softc *sc; 222 caddr_t *addr; 223 size_t *len; 224 int ispullup; 225 size_t *dmasize; 226 { 227 struct asc_softc *asc = (struct asc_softc *)sc; 228 u_int32_t ssr, scr, *p; 229 size_t size; 230 vaddr_t cp; 231 232 NCR_DMA(("%s: start %d@%p,%s\n", sc->sc_dev.dv_xname, 233 *asc->sc_dmalen, *asc->sc_dmaaddr, ispullup ? "IN" : "OUT")); 234 235 /* upto two 4KB pages */ 236 size = min(*dmasize, TWOPAGE((size_t)*addr)); 237 asc->sc_dmaaddr = addr; 238 asc->sc_dmalen = len; 239 asc->sc_dmasize = size; 240 asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 241 *dmasize = size; /* return trimmed transfer size */ 242 243 /* stop DMA engine first */ 244 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 245 ssr &= ~IOASIC_CSR_DMAEN_SCSI; 246 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 247 248 /* have dmamap for the transfering addresses */ 249 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, 250 *addr, size, 251 NULL /* kernel address */, BUS_DMA_NOWAIT)) 252 panic("%s: cannot allocate DMA address", sc->sc_dev.dv_xname); 253 254 /* take care of 8B constraint on starting address */ 255 cp = (vaddr_t)*addr; 256 if ((cp & 7) == 0) { 257 /* comfortably aligned to 8B boundary */ 258 scr = 0; 259 } 260 else { 261 /* truncate to the boundary */ 262 p = (u_int32_t *)(cp & ~7); 263 /* how many 16bit quantities in subject */ 264 scr = (cp & 7) >> 1; 265 /* trim down physical address too */ 266 asc->sc_dmamap->dm_segs[0].ds_addr &= ~7; 267 asc->sc_dmamap->dm_segs[0].ds_len += (cp & 6); 268 if ((asc->sc_flags & ASC_ISPULLUP) == 0) { 269 /* push down to SCSI device */ 270 scr |= 4; 271 /* round up physical address in this case */ 272 asc->sc_dmamap->dm_segs[0].ds_addr += 8; 273 /* don't care excess cache flush */ 274 } 275 /* pack fixup data in SDR0/SDR1 pair and instruct SCR */ 276 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 277 IOASIC_SCSI_SDR0, p[0]); 278 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 279 IOASIC_SCSI_SDR1, p[1]); 280 } 281 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 282 IOASIC_SCSI_DMAPTR, 283 IOASIC_DMA_ADDR(asc->sc_dmamap->dm_segs[0].ds_addr)); 284 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 285 IOASIC_SCSI_NEXTPTR, 286 (asc->sc_dmamap->dm_nsegs == 1) 287 ? ~0 : IOASIC_DMA_ADDR(asc->sc_dmamap->dm_segs[1].ds_addr)); 288 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, scr); 289 290 /* synchronize dmamap contents with memory image */ 291 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 292 0, size, 293 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 294 295 asc->sc_flags |= ASC_MAPLOADED; 296 return 0; 297 } 298 299 void 300 asc_ioasic_go(sc) 301 struct ncr53c9x_softc *sc; 302 { 303 struct asc_softc *asc = (struct asc_softc *)sc; 304 u_int32_t ssr; 305 306 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 307 if (asc->sc_flags & ASC_ISPULLUP) 308 ssr |= IOASIC_CSR_SCSI_DIR; 309 else { 310 /* ULTRIX does in this way */ 311 ssr &= ~IOASIC_CSR_SCSI_DIR; 312 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 313 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 314 } 315 ssr |= IOASIC_CSR_DMAEN_SCSI; 316 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 317 asc->sc_flags |= ASC_DMAACTIVE; 318 } 319 320 static int 321 asc_ioasic_intr(sc) 322 struct ncr53c9x_softc *sc; 323 { 324 struct asc_softc *asc = (struct asc_softc *)sc; 325 int trans, resid; 326 u_int tcl, tcm, ssr, scr, intr; 327 328 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 329 panic("ioasic_intr: DMA wasn't active"); 330 331 #define IOASIC_ASC_ERRORS \ 332 (IOASIC_INTR_SCSI_PTR_LOAD|IOASIC_INTR_SCSI_OVRUN|IOASIC_INTR_SCSI_READ_E) 333 /* 334 * When doing polled I/O, the SCSI bits in the interrupt register won't 335 * get cleared by the interrupt processing. This will cause the DMA 336 * address registers to not load on the next DMA transfer. 337 * Check for these bits here, and clear them if needed. 338 */ 339 intr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR); 340 if ((intr & IOASIC_ASC_ERRORS) != 0) { 341 intr &= ~IOASIC_ASC_ERRORS; 342 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR, intr); 343 } 344 345 /* DMA has stopped */ 346 ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR); 347 ssr &= ~IOASIC_CSR_DMAEN_SCSI; 348 bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr); 349 350 asc->sc_flags &= ~ASC_DMAACTIVE; 351 352 if (asc->sc_dmasize == 0) { 353 /* A "Transfer Pad" operation completed */ 354 tcl = NCR_READ_REG(sc, NCR_TCL); 355 tcm = NCR_READ_REG(sc, NCR_TCM); 356 NCR_DMA(("ioasic_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 357 tcl | (tcm << 8), tcl, tcm)); 358 return 0; 359 } 360 361 resid = 0; 362 if ((asc->sc_flags & ASC_ISPULLUP) == 0 && 363 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 364 NCR_DMA(("ioasic_intr: empty FIFO of %d ", resid)); 365 DELAY(1); 366 } 367 368 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 369 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 370 371 trans = asc->sc_dmasize - resid; 372 if (trans < 0) { /* transferred < 0 ? */ 373 printf("ioasic_intr: xfer (%d) > req (%d)\n", 374 trans, asc->sc_dmasize); 375 trans = asc->sc_dmasize; 376 } 377 NCR_DMA(("ioasic_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 378 tcl, tcm, trans, resid)); 379 380 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 381 0, asc->sc_dmasize, 382 (asc->sc_flags & ASC_ISPULLUP) 383 ? BUS_DMASYNC_POSTREAD 384 : BUS_DMASYNC_POSTWRITE); 385 386 scr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR); 387 if ((asc->sc_flags & ASC_ISPULLUP) && scr != 0) { 388 u_int32_t sdr[2], ptr; 389 390 sdr[0] = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 391 IOASIC_SCSI_SDR0); 392 sdr[1] = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 393 IOASIC_SCSI_SDR1); 394 ptr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 395 IOASIC_SCSI_DMAPTR); 396 ptr = (ptr >> 3) & 0x1ffffffc; 397 /* 398 * scr: 1 -> short[0] 399 * 2 -> short[0] + short[1] 400 * 3 -> short[0] + short[1] + short[2] 401 */ 402 scr &= IOASIC_SCR_WORD; 403 memcpy((void *)MIPS_PHYS_TO_KSEG0(ptr), sdr, scr << 1); 404 } 405 406 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 407 asc->sc_flags &= ~ASC_MAPLOADED; 408 409 *asc->sc_dmalen -= trans; 410 *asc->sc_dmaaddr += trans; 411 412 return 0; 413 } 414 415 416 void 417 asc_ioasic_stop(sc) 418 struct ncr53c9x_softc *sc; 419 { 420 struct asc_softc *asc = (struct asc_softc *)sc; 421 422 if (asc->sc_flags & ASC_MAPLOADED) { 423 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 424 0, asc->sc_dmasize, 425 (asc->sc_flags & ASC_ISPULLUP) 426 ? BUS_DMASYNC_POSTREAD 427 : BUS_DMASYNC_POSTWRITE); 428 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 429 } 430 431 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 432 } 433 434 static u_char 435 asc_read_reg(sc, reg) 436 struct ncr53c9x_softc *sc; 437 int reg; 438 { 439 struct asc_softc *asc = (struct asc_softc *)sc; 440 u_int32_t v; 441 442 v = bus_space_read_4(asc->sc_bst, 443 asc->sc_scsi_bsh, reg * sizeof(u_int32_t)); 444 445 return v & 0xff; 446 } 447 448 static void 449 asc_write_reg(sc, reg, val) 450 struct ncr53c9x_softc *sc; 451 int reg; 452 u_char val; 453 { 454 struct asc_softc *asc = (struct asc_softc *)sc; 455 456 bus_space_write_4(asc->sc_bst, 457 asc->sc_scsi_bsh, reg * sizeof(u_int32_t), val); 458 } 459 460 static int 461 asc_dma_isintr(sc) 462 struct ncr53c9x_softc *sc; 463 { 464 return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT); 465 } 466 467 static int 468 asc_dma_isactive(sc) 469 struct ncr53c9x_softc *sc; 470 { 471 struct asc_softc *asc = (struct asc_softc *)sc; 472 473 return !!(asc->sc_flags & ASC_DMAACTIVE); 474 } 475 476 static void 477 asc_clear_latched_intr(sc) 478 struct ncr53c9x_softc *sc; 479 { 480 } 481