1 /* $NetBSD: dmacreg.h,v 1.2 2008/04/28 20:23:31 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 typedef u_int64_t dmatag_t; 33 34 #define DMAC_BLOCK_SIZE 16 35 #define DMAC_SLICE_SIZE 128 36 #define DMAC_TRANSFER_QWCMAX 0xffff 37 38 /* all register length are 32bit */ 39 #define DMAC_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000) 40 #define DMAC_REGSIZE 0x00010000 41 42 /* 43 * DMAC common registers. 44 */ 45 #define D_CTRL_REG MIPS_PHYS_TO_KSEG1(0x1000e000) /* DMA control */ 46 #define D_STAT_REG MIPS_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */ 47 #define D_PCR_REG MIPS_PHYS_TO_KSEG1(0x1000e020) /* priority control */ 48 #define D_SQWC_REG MIPS_PHYS_TO_KSEG1(0x1000e030) /* interleave size */ 49 #define D_RBOR_REG MIPS_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */ 50 #define D_RBSR_REG MIPS_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */ 51 #define D_STADR_REG MIPS_PHYS_TO_KSEG1(0x1000e060) /* stall address */ 52 #define D_ENABLER_REG MIPS_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */ 53 #define D_ENABLEW_REG MIPS_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) */ 54 55 /* 56 * Channel registers. (10ch) 57 */ 58 #define DMA_CH_VIF0 0 /* to (priority 0) */ 59 #define DMA_CH_VIF1 1 /* both */ 60 #define DMA_CH_GIF 2 /* to */ 61 #define DMA_CH_FROMIPU 3 62 #define DMA_CH_TOIPU 4 63 #define DMA_CH_SIF0 5 /* from */ 64 #define DMA_CH_SIF1 6 /* to */ 65 #define DMA_CH_SIF2 7 /* both (priority 1) */ 66 #define DMA_CH_FROMSPR 8 /* burst channel */ 67 #define DMA_CH_TOSPR 9 /* burst channel */ 68 #define DMA_CH_VALID(x) (((x) >= 0) && ((x) <= 9)) 69 70 #define D_CHCR_OFS 0x00 71 #define D_MADR_OFS 0x10 72 #define D_QWC_OFS 0x20 73 #define D_TADR_OFS 0x30 74 #define D_ASR0_OFS 0x40 75 #define D_ASR1_OFS 0x50 76 #define D_SADR_OFS 0x80 77 78 #define D0_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000) 79 #define D1_REGBASE MIPS_PHYS_TO_KSEG1(0x10009000) 80 #define D2_REGBASE MIPS_PHYS_TO_KSEG1(0x1000a000) 81 #define D3_REGBASE MIPS_PHYS_TO_KSEG1(0x1000b000) 82 #define D4_REGBASE MIPS_PHYS_TO_KSEG1(0x1000b400) 83 #define D5_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c000) 84 #define D6_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c400) 85 #define D7_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c800) 86 #define D8_REGBASE MIPS_PHYS_TO_KSEG1(0x1000d000) 87 #define D9_REGBASE MIPS_PHYS_TO_KSEG1(0x1000d400) 88 89 #define D_CHCR_REG(base) (base) 90 #define D_MADR_REG(base) (base + D_MADR_OFS) 91 #define D_QWC_REG(base) (base + D_QWC_OFS) 92 #define D_TADR_REG(base) (base + D_TADR_OFS) 93 #define D_ASR0_REG(base) (base + D_ASR0_OFS) 94 #define D_ASR1_REG(base) (base + D_ASR1_OFS) 95 #define D_SADR_REG(base) (base + D_SADR_OFS) 96 97 #define D0_CHCR_REG MIPS_PHYS_TO_KSEG1(0x10008000) 98 #define D0_MADR_REG MIPS_PHYS_TO_KSEG1(0x10008010) 99 #define D0_QWC_REG MIPS_PHYS_TO_KSEG1(0x10008020) 100 #define D0_TADR_REG MIPS_PHYS_TO_KSEG1(0x10008030) 101 #define D0_ASR0_REG MIPS_PHYS_TO_KSEG1(0x10008040) 102 #define D0_ASR1_REG MIPS_PHYS_TO_KSEG1(0x10008050) 103 104 #define D1_CHCR_REG MIPS_PHYS_TO_KSEG1(0x10009000) 105 #define D1_MADR_REG MIPS_PHYS_TO_KSEG1(0x10009010) 106 #define D1_QWC_REG MIPS_PHYS_TO_KSEG1(0x10009020) 107 #define D1_TADR_REG MIPS_PHYS_TO_KSEG1(0x10009030) 108 #define D1_ASR0_REG MIPS_PHYS_TO_KSEG1(0x10009040) 109 #define D1_ASR1_REG MIPS_PHYS_TO_KSEG1(0x10009050) 110 111 #define D2_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000a000) 112 #define D2_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000a010) 113 #define D2_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000a020) 114 #define D2_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000a030) 115 #define D2_ASR0_REG MIPS_PHYS_TO_KSEG1(0x1000a040) 116 #define D2_ASR1_REG MIPS_PHYS_TO_KSEG1(0x1000a050) 117 118 #define D3_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000b000) 119 #define D3_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000b010) 120 #define D3_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000b020) 121 122 #define D4_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000b400) 123 #define D4_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000b410) 124 #define D4_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000b420) 125 #define D4_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000b430) 126 127 #define D5_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c000) 128 #define D5_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c010) 129 #define D5_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c020) 130 131 #define D6_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c400) 132 #define D6_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c410) 133 #define D6_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c420) 134 #define D6_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000c430) 135 136 #define D7_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c800) 137 #define D7_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c810) 138 #define D7_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c820) 139 140 #define D8_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000d000) 141 #define D8_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000d010) 142 #define D8_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000d020) 143 #define D8_SADR_REG MIPS_PHYS_TO_KSEG1(0x1000d080) 144 145 #define D9_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000d400) 146 #define D9_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000d410) 147 #define D9_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000d420) 148 #define D9_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000d430) 149 #define D9_SADR_REG MIPS_PHYS_TO_KSEG1(0x1000d480) 150 151 /* 152 * DMA control 153 */ 154 #define D_CTRL_DMAE 0x00000001 /* all DMA enable/disable */ 155 #define D_CTRL_RELE 0x00000002 /* Cycle stealing on/off */ 156 /* Memory FIFO drain control */ 157 #define D_CTRL_MFD_MASK 0x3 158 #define D_CTRL_MFD_SHIFT 2 159 #define D_CTRL_MFD(x) \ 160 (((x) >> D_CTRL_MFD_SHIFT) & D_CTRL_MFD_MASK) 161 #define D_CTRL_MFD_CLR(x) \ 162 ((x) & ~(D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT)) 163 #define D_CTRL_MFD_SET(x, val) \ 164 ((x) | (((val) << D_CTRL_MFD_SHIFT) & \ 165 (D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT))) 166 #define D_CTRL_MFD_DISABLE 0 167 #define D_CTRL_MFD_VIF1 2 168 #define D_CTRL_MFD_GIF 3 169 170 /* Stall control source channel */ 171 #define D_CTRL_STS_MASK 0x3 172 #define D_CTRL_STS_SHIFT 4 173 #define D_CTRL_STS(x) \ 174 (((x) >> D_CTRL_STS_SHIFT) & D_CTRL_STS_MASK) 175 #define D_CTRL_STS_CLR(x) \ 176 ((x) & ~(D_CTRL_STS_MASK << D_CTRL_STS_SHIFT)) 177 #define D_CTRL_STS_SET(x, val) \ 178 ((x) | (((val) << D_CTRL_STS_SHIFT) & \ 179 (D_CTRL_STS_MASK << D_CTRL_STS_SHIFT))) 180 #define D_CTRL_STS_NONE 0 181 #define D_CTRL_STS_SIF0 1 182 #define D_CTRL_STS_FROMSPR 2 183 #define D_CTRL_STS_FROMIPU 3 184 185 /* Stall control drain channel */ 186 #define D_CTRL_STD_MASK 0x3 187 #define D_CTRL_STD_SHIFT 6 188 #define D_CTRL_STD(x) \ 189 (((x) >> D_CTRL_STD_SHIFT) & D_CTRL_STD_MASK) 190 #define D_CTRL_STD_CLR(x) \ 191 ((x) & ~(D_CTRL_STD_MASK << D_CTRL_STD_SHIFT)) 192 #define D_CTRL_STD_SET(x, val) \ 193 ((x) | (((val) << D_CTRL_STD_SHIFT) & \ 194 (D_CTRL_STD_MASK << D_CTRL_STD_SHIFT))) 195 #define D_CTRL_STD_NONE 0 196 #define D_CTRL_STD_VIF1 1 197 #define D_CTRL_STD_GIF 2 198 #define D_CTRL_STD_SIF1 3 199 200 /* 201 * Release cycle 202 * for burst channel Cycle steanling on mode only. 203 */ 204 #define D_CTRL_RCYC_MASK 0x7 205 #define D_CTRL_RCYC_SHIFT 8 206 #define D_CTRL_RCYC(x) \ 207 (((x) >> D_CTRL_RCYC_SHIFT) & D_CTRL_RCYC_MASK) 208 #define D_CTRL_RCYC_CLR(x) \ 209 ((x) & ~(D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT)) 210 #define D_CTRL_RCYC_SET(x, val) \ 211 ((x) | (((val) << D_CTRL_RCYC_SHIFT) & \ 212 (D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT))) 213 #define D_CTRL_RCYC_CYCLE(x) (8 << (x)) 214 215 /* 216 * Interrupt status register (write clear/invert) 217 * DMAC interrupt line connected to MIPS HwINT1 218 */ 219 /* MFIFO empty interrupt enable */ 220 #define D_STAT_MEIM 0x40000000 221 /* DMA stall interrupt enable */ 222 #define D_STAT_SIM 0x20000000 223 /* Channel interrupt enable */ 224 #define D_STAT_CIM_MASK 0x3ff 225 #define D_STAT_CIM_SHIFT 16 226 #define D_STAT_CIM(x) (((x) >> D_STAT_CIM_SHIFT) & D_STAT_CIM_MASK) 227 #define D_STAT_CIM_BIT(x) ((1 << (x)) << D_STAT_CIM_SHIFT) 228 #define D_STAT_CIM9 0x02000000 229 #define D_STAT_CIM8 0x01000000 230 #define D_STAT_CIM7 0x00800000 231 #define D_STAT_CIM6 0x00400000 232 #define D_STAT_CIM5 0x00200000 233 #define D_STAT_CIM4 0x00100000 234 #define D_STAT_CIM3 0x00080000 235 #define D_STAT_CIM2 0x00040000 236 #define D_STAT_CIM1 0x00020000 237 #define D_STAT_CIM0 0x00010000 238 /* BUSERR interrupt status */ 239 #define D_STAT_BEIS 0x00008000 240 /* MFIFO empty interrupt status */ 241 #define D_STAT_MEIS 0x00004000 242 /* DMA stall interrupt status */ 243 #define D_STAT_SIS 0x00002000 244 /* Channel interrupt status */ 245 #define D_STAT_CIS_MASK 0x3ff 246 #define D_STAT_CIS_SHIFT 0 247 #define D_STAT_CIS_BIT(x) (1 << (x)) 248 #define D_STAT_CIS9 0x00000200 249 #define D_STAT_CIS8 0x00000100 250 #define D_STAT_CIS7 0x00000080 251 #define D_STAT_CIS6 0x00000040 252 #define D_STAT_CIS5 0x00000020 253 #define D_STAT_CIS4 0x00000010 254 #define D_STAT_CIS3 0x00000008 255 #define D_STAT_CIS2 0x00000004 256 #define D_STAT_CIS1 0x00000002 257 #define D_STAT_CIS0 0x00000001 258 259 /* 260 * Priority control register. 261 */ 262 /* Priority control enable */ 263 #define D_PCR_PCE 0x80000000 264 /* Channel DMA enable (packet priority control enable) */ 265 #define D_PCR_CDE_MASK 0x3ff 266 #define D_PCR_CDE_SHIFT 16 267 #define D_PCR_CDE(x) \ 268 (((x) >> D_PCR_CDE_SHIFT) & D_PCR_CDE_MASK) 269 #define D_PCR_CDE_CLR(x) \ 270 ((x) & ~(D_PCR_CDE_MASK << D_PCR_CDE_SHIFT)) 271 #define D_PCR_CDE_SET(x, val) \ 272 ((x) | (((val) << D_PCR_CDE_SHIFT) & \ 273 (D_PCR_CDE_MASK << D_PCR_CDE_SHIFT))) 274 #define D_PCR_CDE9 0x02000000 275 #define D_PCR_CDE8 0x01000000 276 #define D_PCR_CDE7 0x00800000 277 #define D_PCR_CDE6 0x00400000 278 #define D_PCR_CDE5 0x00200000 279 #define D_PCR_CDE4 0x00100000 280 #define D_PCR_CDE3 0x00080000 281 #define D_PCR_CDE2 0x00040000 282 #define D_PCR_CDE1 0x00020000 283 #define D_PCR_CDE0 0x00010000 284 /* COP control (interrupt status connect to CPCOND[0] or not) */ 285 #define D_PCR_CPC_MASK 0x3ff 286 #define D_PCR_CPC_SHIFT 0 287 #define D_PCR_CPC(x) ((x) & D_PCR_CPC_MASK) 288 #define D_PCR_CPC_CLR(x) ((x) & ~D_PCR_CPC_MASK) 289 #define D_PCR_CPC_SET(x, val) ((x) | ((val) & D_PCR_CPC_MASK)) 290 #define D_PCR_CPC_BIT(x) (1 << (x)) 291 #define D_PCR_CPC9 0x00000200 292 #define D_PCR_CPC8 0x00000100 293 #define D_PCR_CPC7 0x00000080 294 #define D_PCR_CPC6 0x00000040 295 #define D_PCR_CPC5 0x00000020 296 #define D_PCR_CPC4 0x00000010 297 #define D_PCR_CPC3 0x00000008 298 #define D_PCR_CPC2 0x00000004 299 #define D_PCR_CPC1 0x00000002 300 #define D_PCR_CPC0 0x00000001 301 302 /* 303 * Interleave size register 304 */ 305 /* Transfer quadword counter */ 306 #define D_SQWC_TQWC_MASK 0xff 307 #define D_SQWC_TQWC_SHIFT 16 308 #define D_SQWC_TQWC(x) \ 309 (((x) >> D_SQWC_TQWC_SHIFT) & D_SQWC_TQWC_MASK) 310 #define D_SQWC_TQWC_CLR(x) \ 311 ((x) & ~(D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT)) 312 #define D_SQWC_TQWC_SET(x, val) \ 313 ((x) | (((val) << D_SQWC_TQWC_SHIFT) & \ 314 (D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT))) 315 /* Skip quadword counter */ 316 #define D_SQWC_SQWC_MASK 0xff 317 #define D_SQWC_SQWC_SHIFT 0 318 #define D_SQWC_SQWC(x) \ 319 (((x) >> D_SQWC_SQWC_SHIFT) & D_SQWC_SQWC_MASK) 320 #define D_SQWC_SQWC_CLR(x) \ 321 ((x) & ~(D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT)) 322 #define D_SQWC_SQWC_SET(x, val) \ 323 ((x) | (((val) << D_SQWC_SQWC_SHIFT) & \ 324 (D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT))) 325 326 /* 327 * Ring buffer address register 328 * 16byte alignment address [30:4] 329 */ 330 331 /* 332 * Ring buffer size register 333 * must be 2 ** n qword. [30:4] 334 */ 335 336 /* 337 * Stall address register 338 * [30:0] (qword alignment) 339 */ 340 341 /* 342 * DMA suspend register 343 */ 344 #define D_ENABLE_SUSPEND 0x00010000 345 346 347 /* 348 * Channel specific register. 349 */ 350 351 /* CHANNEL CONTROL REGISTER */ 352 /* upper 16bit of DMA tag last read. */ 353 #define D_CHCR_TAG_MASK 0xff 354 #define D_CHCR_TAG_SHIFT 16 355 #define D_CHCR_TAG(x) \ 356 (((x) >> D_CHCR_TAG_SHIFT) & D_CHCR_TAG_MASK) 357 #define D_CHCR_TAG_CLR(x) \ 358 ((x) & ~(D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT)) 359 #define D_CHCR_TAG_SET(x, val) \ 360 ((x) | (((val) << D_CHCR_TAG_SHIFT) & \ 361 (D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT))) 362 /* DMA start */ 363 #define D_CHCR_STR 0x00000100 364 /* Tag interrupt enable (IRQ bit of DMAtag) */ 365 #define D_CHCR_TIE 0x00000080 366 /* Tag transfer enable (Source chain mode only) */ 367 #define D_CHCR_TTE 0x00000040 368 /* Address stack pointer */ 369 #define D_CHCR_ASP_MASK 0x3 370 #define D_CHCR_ASP_SHIFT 4 371 #define D_CHCR_ASP(x) \ 372 (((x) >> D_CHCR_ASP_SHIFT) & D_CHCR_ASP_MASK) 373 #define D_CHCR_ASP_CLR(x) \ 374 ((x) & ~(D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT)) 375 #define D_CHCR_ASP_SET(x, val) \ 376 ((x) | (((val) << D_CHCR_ASP_SHIFT) & \ 377 (D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT))) 378 #define D_CHCR_ASP_PUSHED_NONE 0 379 #define D_CHCR_ASP_PUSHED_1 1 380 #define D_CHCR_ASP_PUSHED_2 2 381 /* Logical transfer mode */ 382 #define D_CHCR_MOD_MASK 0x3 383 #define D_CHCR_MOD_SHIFT 2 384 #define D_CHCR_MOD(x) \ 385 (((x) >> D_CHCR_MOD_SHIFT) & D_CHCR_MOD_MASK) 386 #define D_CHCR_MOD_CLR(x) \ 387 ((x) & ~(D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT)) 388 #define D_CHCR_MOD_SET(x, val) \ 389 ((x) | (((val) << D_CHCR_MOD_SHIFT) & \ 390 (D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT))) 391 #define D_CHCR_MOD_NORMAL 0 392 #define D_CHCR_MOD_CHAIN 1 393 #define D_CHCR_MOD_INTERLEAVE 2 394 /* 395 * DMA transfer direction (1 ... from Memory, 0 ... to Memory) 396 * (VIF1, SIF2 only. i.e. `both'-direction channel requires this) 397 */ 398 #define D_CHCR_DIR 0x00000001 399 400 /* 401 * TRANSFER ADDRESS REGISTER (D-RAM address) 402 * 16 byte alignment. In FROMSPR, TOSPR channel, D_MADR_SPR always 0 403 */ 404 #define D_MADR_SPR 0x80000000 405 406 /* 407 * TAG ADDRESS REGISTER (next tag address) 408 * 16 byte alignment. 409 */ 410 #define D_TADR_SPR 0x80000000 411 412 /* 413 * TAG ADDRESS STACK REGISTER (2 stage) 414 * 16 byte alignment. 415 */ 416 #define D_ASR_SPR 0x80000000 417 418 /* 419 * SPR TRANSFER ADDRESS REGISTER (SPR address) 420 * 16 byte alignment. FROMSPR, TOSPR only. 421 */ 422 #define D_SADR_MASK 0x3fff 423 #define D_SADR_SHIFT 0 424 #define D_SADR(x) \ 425 ((u_int32_t)(x) & D_SADR_MASK) 426 /* 427 * TRANSFER SIZE REGISTER 428 * min 16 byte to max 1 Mbyte. 429 */ 430 #define D_QWC_MASK 0xffff 431 #define D_QWC_SHIFT 0 432 #define D_QWC(x) (((x) >> D_QWC_SHIFT) & D_QWC_MASK) 433 #define D_QWC_CLR(x) ((x) & ~(D_QWC_MASK << D_QWC_SHIFT)) 434 #define D_QWC_SET(x, val) \ 435 ((x) | (((val) << D_QWC_SHIFT) & D_QWC_MASK << D_QWC_SHIFT)) 436 437 /* 438 * Source/Destination Chain Tag definition. 439 * SC ... VIF0, VIF1, GIF, toIPU, SIF1, toSPR 440 * DC ... SIF0, fromSPR 441 */ 442 /* 443 * DMA address 444 * At least, 16byte align. 445 * but 64byte align is recommended. because EE D-cash line size is 64byte. 446 * To gain maximum DMA speed, use 128 byte align. 447 */ 448 #define DMATAG_ADDR_MASK 0xffffffff 449 #define DMATAG_ADDR_SHIFT 32 450 #define DMATAG_ADDR(x) \ 451 ((u_int32_t)(((x) >> DMATAG_ADDR_SHIFT) & DMATAG_ADDR_MASK)) 452 #define DMATAG_ADDR_SET(x, val) \ 453 ((dmatag_t)(x) | (((dmatag_t)(val)) << DMATAG_ADDR_SHIFT)) 454 455 #define DMATAG_ADDR32_INVALID(x) ((x) & 0xf) /* 16byte alignment */ 456 457 /* 458 * DMA controller command 459 */ 460 #define DMATAG_CMD_MASK 0xffffffff 461 #define DMATAG_CMD_SHIFT 0 462 #define DMATAG_CMD(x) \ 463 ((u_int32_t)((x) & DMATAG_CMD_MASK)) 464 465 #define DMATAG_CMD_IRQ 0x80000000 466 467 #define DMATAG_CMD_ID_MASK 0x7 468 #define DMATAG_CMD_ID_SHIFT 28 469 #define DMATAG_CMD_ID(x) \ 470 (((x) >> DMATAG_CMD_ID_SHIFT) & DMATAG_CMD_ID_MASK) 471 #define DMATAG_CMD_ID_CLR(x) \ 472 ((x) & ~(DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT)) 473 #define DMATAG_CMD_ID_SET(x, val) \ 474 ((x) | (((val) << DMATAG_CMD_ID_SHIFT) & \ 475 (DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT))) 476 #define DMATAG_CMD_SCID_REFE 0 477 #define DMATAG_CMD_SCID_CNT 1 478 #define DMATAG_CMD_SCID_NEXT 2 479 #define DMATAG_CMD_SCID_REF 3 480 #define DMATAG_CMD_SCID_REFS 4 /* VIF1, GIF, SIF1 only */ 481 #define DMATAG_CMD_SCID_CALL 5 /* VIF0, VIF1, GIF only */ 482 #define DMATAG_CMD_SCID_RET 6 /* VIF0, VIF1, GIF only */ 483 #define DMATAG_CMD_SCID_END 7 484 485 #define DMATAG_CMD_DCID_CNTS 0 /* SIF0, fromSPR only */ 486 #define DMATAG_CMD_DCID_CNT 1 487 #define DMATAG_CMD_DCID_END 7 488 489 #define DMATAG_CMD_PCE_MASK 0x3 490 #define DMATAG_CMD_PCE_SHIFT 26 491 #define DMATAG_CMD_PCE(x) \ 492 (((x) >> DMATAG_CMD_PCE_SHIFT) & DMATAG_CMD_PCE_MASK) 493 #define DMATAG_CMD_PCE_CLR(x) \ 494 ((x) & ~(DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT)) 495 #define DMATAG_CMD_PCE_SET(x, val) \ 496 ((x) | (((val) << DMATAG_CMD_PCE_SHIFT) & \ 497 (DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT))) 498 #define DMATAG_CMD_PCE_NONE 0 499 #define DMATAG_CMD_PCE_DISABLE 2 500 #define DMATAG_CMD_PCE_ENABLE 3 501 502 #define DMATAG_CMD_QWC_MASK 0xffff 503 #define DMATAG_CMD_QWC_SHIFT 0 504 #define DMATAG_CMD_QWC(x) \ 505 (((x) >> DMATAG_CMD_QWC_SHIFT) & DMATAG_CMD_QWC_MASK) 506 #define DMATAG_CMD_QWC_CLR(x) \ 507 ((x) & ~(DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT)) 508 #define DMATAG_CMD_QWC_SET(x, val) \ 509 ((x) | (((val) << DMATAG_CMD_QWC_SHIFT) & \ 510 (DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT))) 511