xref: /netbsd-src/sys/arch/next68k/dev/zs.c (revision 8ac07aec990b9d2e483062509d0a9fa5b4f57cf2) 
1 /*	$NetBSD: zs.c,v 1.31 2008/03/29 19:15:35 tsutsui Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Gordon W. Ross.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * Zilog Z8530 Dual UART driver (machine-dependent part)
41  *
42  * Runs two serial lines per chip using slave drivers.
43  * Plain tty/async lines use the zs_async slave.
44  * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
45  */
46 
47 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56
48  * and then updated to reflect changes in 1.59
49  * by Darrin B Jewell <jewell@mit.edu>  Mon Mar 30 20:24:46 1998
50  */
51 
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.31 2008/03/29 19:15:35 tsutsui Exp $");
54 
55 #include "opt_ddb.h"
56 #include "opt_kgdb.h"
57 #include "opt_serial.h"
58 
59 #include <sys/param.h>
60 #include <sys/systm.h>
61 #include <sys/conf.h>
62 #include <sys/device.h>
63 #include <sys/file.h>
64 #include <sys/ioctl.h>
65 #include <sys/kernel.h>
66 #include <sys/proc.h>
67 #include <sys/tty.h>
68 #include <sys/time.h>
69 #include <sys/syslog.h>
70 #include <sys/intr.h>
71 #include <sys/cpu.h>
72 
73 #include <machine/autoconf.h>
74 #include <machine/psl.h>
75 
76 #include <dev/cons.h>
77 
78 #include <dev/ic/z8530reg.h>
79 #include <machine/z8530var.h>
80 
81 #include <next68k/next68k/isr.h>
82 
83 #include <next68k/dev/intiovar.h>
84 #include <next68k/dev/zs_cons.h>
85 
86 #include "ioconf.h"
87 #include "zsc.h" 	/* NZSC */
88 
89 #if (NZSC < 0)
90 #error "No serial controllers?"
91 #endif
92 
93 /*
94  * Some warts needed by z8530tty.c -
95  * The default parity REALLY needs to be the same as the PROM uses,
96  * or you can not see messages done with printf during boot-up...
97  */
98 int zs_def_cflag = (CREAD | CS8 | HUPCL);
99 
100 /*
101  * The NeXT provides a 3.686400 MHz clock to the ZS chips.
102  */
103 #define PCLK	(9600 * 384)		/* PCLK pin input clock rate */
104 
105 #define	ZS_DELAY()		delay(2)
106 
107 /* The layout of this is hardware-dependent (padding, order). */
108 struct zschan {
109 	volatile uint8_t zc_csr;	/* ctrl,status, and indirect access */
110 	uint8_t		zc_xxx0;
111 	volatile uint8_t zc_data;	/* data */
112 	uint8_t		zc_xxx1;
113 };
114 
115 /* Flags from cninit() */
116 static int zs_hwflags[2];
117 
118 /* Default speed for each channel */
119 static int zs_defspeed[2] = {
120 	9600,	 	/* ttya */
121 	9600,		/* ttyb */
122 };
123 
124 static uint8_t zs_init_reg[16] = {
125 	0,	/* 0: CMD (reset, etc.) */
126 	0,	/* 1: No interrupts yet. */
127 	0x18 + NEXT_I_IPL(NEXT_I_SCC),	/* 2: IVECT */
128 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
129 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
130 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
131 	0,	/* 6: TXSYNC/SYNCLO */
132 	0,	/* 7: RXSYNC/SYNCHI */
133 	0,	/* 8: alias for data port */
134 	ZSWR9_MASTER_IE,
135 	0,	/*10: Misc. TX/RX control bits */
136 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
137 	((PCLK/32)/9600)-2,	/*12: BAUDLO (default=9600) */
138 	0,			/*13: BAUDHI (default=9600) */
139 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
140 	ZSWR15_BREAK_IE,
141 };
142 
143 struct zschan *
144 zs_get_chan_addr(int channel)
145 {
146 	char *addr;
147 	struct zschan *zc;
148 
149 	addr = (void *)IIOV(NEXT_P_SCC);
150 	if (channel == 0) {
151 		/* handle the fact the ports are intertwined. */
152 		zc = (struct zschan *)(addr + 1);
153 	} else {
154 		zc = (struct zschan *)(addr);
155 	}
156 	return (zc);
157 }
158 
159 
160 /****************************************************************
161  * Autoconfig
162  ****************************************************************/
163 
164 /* Definition of the driver for autoconfig. */
165 static int	zs_match(device_t, cfdata_t, void *);
166 static void	zs_attach(device_t, device_t, void *);
167 static int	zs_print(void *, const char *);
168 
169 extern int  zs_getc(void *);
170 extern void zs_putc(void *, int);
171 
172 CFATTACH_DECL_NEW(zsc, sizeof(struct zsc_softc),
173     zs_match, zs_attach, NULL, NULL);
174 
175 static int zs_attached;
176 
177 /* Interrupt handlers. */
178 static int zshard(void *);
179 
180 static int zs_get_speed(struct zs_chanstate *);
181 
182 /*
183  * Is the zs chip present?
184  */
185 static int
186 zs_match(device_t parent, cfdata_t cf, void *aux)
187 {
188 	struct intio_attach_args *ia = aux;
189 
190 	if (zs_attached)
191 		return 0;
192 
193 	ia->ia_addr = (void *)IIOV(NEXT_P_SCC);
194 
195 	return 1;
196 }
197 
198 /*
199  * Attach a found zs.
200  *
201  * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR
202  * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE?
203  */
204 static void
205 zs_attach(device_t parent, device_t self, void *aux)
206 {
207 	struct zsc_softc *zsc = device_private(self);
208 	struct zsc_attach_args zsc_args;
209 	volatile struct zschan *zc;
210 	struct zs_chanstate *cs;
211 	int s, channel;
212 
213 	zs_attached = 1;
214 
215 	zsc->zsc_dev = self;
216 	aprint_normal("\n");
217 
218 	/*
219 	 * Initialize software state for each channel.
220 	 */
221 	for (channel = 0; channel < 2; channel++) {
222 		zsc_args.channel = channel;
223 		zsc_args.hwflags = zs_hwflags[channel];
224 		cs = &zsc->zsc_cs_store[channel];
225 		zsc->zsc_cs[channel] = cs;
226 
227 		zs_lock_init(cs);
228 		cs->cs_channel = channel;
229 		cs->cs_private = NULL;
230 		cs->cs_ops = &zsops_null;
231 		cs->cs_brg_clk = PCLK / 16;
232 
233 		zc = zs_get_chan_addr(channel);
234 		cs->cs_reg_csr  = &zc->zc_csr;
235 		cs->cs_reg_data = &zc->zc_data;
236 
237 		memcpy(cs->cs_creg, zs_init_reg, 16);
238 		memcpy(cs->cs_preg, zs_init_reg, 16);
239 
240 		/* XXX: Get these from the PROM properties! */
241 		/* XXX: See the mvme167 code.  Better. */
242 		if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
243 			cs->cs_defspeed = zs_get_speed(cs);
244 		else
245 			cs->cs_defspeed = zs_defspeed[channel];
246 		cs->cs_defcflag = zs_def_cflag;
247 
248 		/* Make these correspond to cs_defcflag (-crtscts) */
249 		cs->cs_rr0_dcd = ZSRR0_DCD;
250 		cs->cs_rr0_cts = 0;
251 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
252 		cs->cs_wr5_rts = 0;
253 
254 		/*
255 		 * Clear the master interrupt enable.
256 		 * The INTENA is common to both channels,
257 		 * so just do it on the A channel.
258 		 */
259 		if (channel == 0) {
260 			zs_write_reg(cs, 9, 0);
261 		}
262 
263 		/*
264 		 * Look for a child driver for this channel.
265 		 * The child attach will setup the hardware.
266 		 */
267 		if (!config_found(self, (void *)&zsc_args, zs_print)) {
268 			/* No sub-driver.  Just reset it. */
269 			uint8_t reset = (channel == 0) ?
270 				ZSWR9_A_RESET : ZSWR9_B_RESET;
271 			s = splzs();
272 			zs_write_reg(cs,  9, reset);
273 			splx(s);
274 		}
275 	}
276 
277 	isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0, NULL);
278 	zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
279 	    (void (*)(void *))zsc_intr_soft, zsc);
280 	INTR_ENABLE(NEXT_I_SCC);
281 
282 	/*
283 	 * Set the master interrupt enable and interrupt vector.
284 	 * (common to both channels, do it on A)
285 	 */
286 	cs = zsc->zsc_cs[0];
287 	s = splhigh();
288 	/* interrupt vector */
289 	zs_write_reg(cs, 2, zs_init_reg[2]);
290 	/* master interrupt control (enable) */
291 	zs_write_reg(cs, 9, zs_init_reg[9]);
292 	splx(s);
293 }
294 
295 static int
296 zs_print(void *aux, const char *name)
297 {
298 	struct zsc_attach_args *args = aux;
299 
300 	if (name != NULL)
301 		aprint_normal("%s: ", name);
302 
303 	if (args->channel != -1)
304 		aprint_normal(" channel %d", args->channel);
305 
306 	return (UNCONF);
307 }
308 
309 static volatile int zssoftpending;
310 
311 /*
312  * Our ZS chips all share a common, autovectored interrupt,
313  * so we have to look at all of them on each interrupt.
314  */
315 static int
316 zshard(void *arg)
317 {
318 	struct zsc_softc *zsc;
319 	int unit, rr3, rval;
320 
321 	if (!INTR_OCCURRED(NEXT_I_SCC))
322 		return 0;
323 
324 	rval = 0;
325 	for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
326 		zsc = device_private(zsc_cd.cd_devs[unit]);
327 		if (zsc == NULL)
328 			continue;
329 		rr3 = zsc_intr_hard(zsc);
330 		/* Count up the interrupts. */
331 		if (rr3) {
332 			rval |= rr3;
333 			zsc->zsc_intrcnt.ev_count++;
334 		}
335 		/* We are at splzs here, so no need to lock. */
336 		if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
337 			softint_schedule(zsc->zsc_softintr_cookie);
338 	}
339 
340 	return(1);
341 }
342 
343 /*
344  * Compute the current baud rate given a ZS channel.
345  */
346 static int
347 zs_get_speed(struct zs_chanstate *cs)
348 {
349 	int tconst;
350 
351 	tconst = zs_read_reg(cs, 12);
352 	tconst |= zs_read_reg(cs, 13) << 8;
353 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
354 }
355 
356 /*
357  * MD functions for setting the baud rate and control modes.
358  */
359 int
360 zs_set_speed(struct zs_chanstate *cs, int bps)
361 {
362 	int tconst, real_bps;
363 
364 	if (bps == 0)
365 		return (0);
366 
367 #ifdef	DIAGNOSTIC
368 	if (cs->cs_brg_clk == 0)
369 		panic("zs_set_speed");
370 #endif
371 
372 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
373 	if (tconst < 0)
374 		return (EINVAL);
375 
376 	/* Convert back to make sure we can do it. */
377 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
378 
379 	/* XXX - Allow some tolerance here? */
380 	if (real_bps != bps)
381 		return (EINVAL);
382 
383 	cs->cs_preg[12] = tconst;
384 	cs->cs_preg[13] = tconst >> 8;
385 
386 	/* Caller will stuff the pending registers. */
387 	return (0);
388 }
389 
390 int
391 zs_set_modes(struct zs_chanstate *cs, int cflag)
392 {
393 	int s;
394 
395 	/*
396 	 * Output hardware flow control on the chip is horrendous:
397 	 * if carrier detect drops, the receiver is disabled, and if
398 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
399 	 * Therefore, NEVER set the HFC bit, and instead use the
400 	 * status interrupt to detect CTS changes.
401 	 */
402 	s = splzs();
403 	cs->cs_rr0_pps = 0;
404 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
405 		cs->cs_rr0_dcd = 0;
406 		if ((cflag & MDMBUF) == 0)
407 			cs->cs_rr0_pps = ZSRR0_DCD;
408 	} else
409 		cs->cs_rr0_dcd = ZSRR0_DCD;
410 	if ((cflag & CRTSCTS) != 0) {
411 		cs->cs_wr5_dtr = ZSWR5_DTR;
412 		cs->cs_wr5_rts = ZSWR5_RTS;
413 		cs->cs_rr0_cts = ZSRR0_CTS;
414 	} else if ((cflag & CDTRCTS) != 0) {
415 		cs->cs_wr5_dtr = 0;
416 		cs->cs_wr5_rts = ZSWR5_DTR;
417 		cs->cs_rr0_cts = ZSRR0_CTS;
418 	} else if ((cflag & MDMBUF) != 0) {
419 		cs->cs_wr5_dtr = 0;
420 		cs->cs_wr5_rts = ZSWR5_DTR;
421 		cs->cs_rr0_cts = ZSRR0_DCD;
422 	} else {
423 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
424 		cs->cs_wr5_rts = 0;
425 		cs->cs_rr0_cts = 0;
426 	}
427 	splx(s);
428 
429 	/* Caller will stuff the pending registers. */
430 	return (0);
431 }
432 
433 /*
434  * Read or write the chip with suitable delays.
435  */
436 
437 uint8_t
438 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
439 {
440 	uint8_t val;
441 
442 	*cs->cs_reg_csr = reg;
443 	ZS_DELAY();
444 	val = *cs->cs_reg_csr;
445 	ZS_DELAY();
446 	return (val);
447 }
448 
449 void
450 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
451 {
452 	*cs->cs_reg_csr = reg;
453 	ZS_DELAY();
454 	*cs->cs_reg_csr = val;
455 	ZS_DELAY();
456 }
457 
458 uint8_t
459 zs_read_csr(struct zs_chanstate *cs)
460 {
461 	uint8_t val;
462 
463 	val = *cs->cs_reg_csr;
464 	ZS_DELAY();
465 	return (val);
466 }
467 
468 void
469 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
470 {
471 	*cs->cs_reg_csr = val;
472 	ZS_DELAY();
473 }
474 
475 uint8_t
476 zs_read_data(struct zs_chanstate *cs)
477 {
478 	uint8_t val;
479 
480 	val = *cs->cs_reg_data;
481 	ZS_DELAY();
482 	return (val);
483 }
484 
485 void
486 zs_write_data(struct zs_chanstate *cs, uint8_t val)
487 {
488 	*cs->cs_reg_data = val;
489 	ZS_DELAY();
490 }
491 
492 /****************************************************************
493  * Console support functions (Sun specific!)
494  * Note: this code is allowed to know about the layout of
495  * the chip registers, and uses that to keep things simple.
496  * XXX - I think I like the mvme167 code better. -gwr
497  ****************************************************************/
498 
499 extern void Debugger(void);
500 void *zs_conschan;
501 int	zs_consunit = 0;
502 
503 /*
504  * Handle user request to enter kernel debugger.
505  */
506 void
507 zs_abort(struct zs_chanstate *cs)
508 {
509 #if defined(ZS_CONSOLE_ABORT)
510 	volatile struct zschan *zc = zs_conschan;
511 	int rr0;
512 
513 	/* Wait for end of break to avoid PROM abort. */
514 	/* XXX - Limit the wait? */
515 	do {
516 		rr0 = zc->zc_csr;
517 		ZS_DELAY();
518 	} while (rr0 & ZSRR0_BREAK);
519 
520 #if defined(KGDB)
521 	zskgdb(cs);
522 #elif defined(DDB)
523 	Debugger();
524 #else
525 	/* XXX eventually, drop into next rom monitor here */
526 	printf("stopping on keyboard abort not supported without DDB or KGDB\n");
527 #endif
528 #else /* !ZS_CONSOLE_ABORT */
529 	return;
530 #endif
531 }
532 
533 /*
534  * Polled input char.
535  */
536 int
537 zs_getc(void *arg)
538 {
539 	volatile struct zschan *zc = arg;
540 	int s, c, rr0;
541 
542 	s = splhigh();
543 	/* Wait for a character to arrive. */
544 	do {
545 		rr0 = zc->zc_csr;
546 		ZS_DELAY();
547 	} while ((rr0 & ZSRR0_RX_READY) == 0);
548 
549 	c = zc->zc_data;
550 	ZS_DELAY();
551 	splx(s);
552 
553 	/*
554 	 * This is used by the kd driver to read scan codes,
555 	 * so don't translate '\r' ==> '\n' here...
556 	 */
557 	return (c);
558 }
559 
560 /*
561  * Polled output char.
562  */
563 void
564 zs_putc(void *arg, int c)
565 {
566 	volatile struct zschan *zc = arg;
567 	int s, rr0;
568 
569 	s = splhigh();
570 	/* Wait for transmitter to become ready. */
571 	do {
572 		rr0 = zc->zc_csr;
573 		ZS_DELAY();
574 	} while ((rr0 & ZSRR0_TX_READY) == 0);
575 
576 
577 	zc->zc_data = c;
578 	ZS_DELAY();
579 
580 	splx(s);
581 }
582 
583 /*****************************************************************/
584 
585 void zscninit(struct consdev *);
586 int  zscngetc(dev_t);
587 void zscnputc(dev_t, int);
588 void zscnprobe(struct consdev *);
589 
590 void
591 zscnprobe(struct consdev *cp)
592 {
593 	extern const struct cdevsw zstty_cdevsw;
594 	int     maj;
595 
596 	maj = cdevsw_lookup_major(&zstty_cdevsw);
597 	if (maj != -1) {
598 #ifdef SERCONSOLE
599 		cp->cn_pri = CN_REMOTE;
600 #else
601 		cp->cn_pri = CN_NORMAL;		 /* Lower than CN_INTERNAL */
602 #endif
603 		zs_consunit = 0;
604 		cp->cn_dev = makedev(maj, zs_consunit);
605 		zs_conschan = zs_get_chan_addr(zs_consunit);
606 	} else {
607 		cp->cn_pri = CN_DEAD;
608 	}
609 }
610 
611 void
612 zscninit(struct consdev *cn)
613 {
614 	struct zs_chanstate xcs;
615 	struct zs_chanstate *cs;
616 	volatile struct zschan *zc;
617 	int tconst, s;
618 
619 	zs_hwflags[zs_consunit] = ZS_HWFLAG_CONSOLE;
620 
621 	/* Setup temporary chanstate. */
622 	memset(&xcs, 0, sizeof(xcs));
623 	cs = &xcs;
624 	zc = zs_conschan;
625 	cs->cs_reg_csr  = &zc->zc_csr;
626 	cs->cs_reg_data = &zc->zc_data;
627 	cs->cs_channel = zs_consunit;
628 	cs->cs_brg_clk = PCLK / 16;
629 
630 	memcpy(cs->cs_preg, zs_init_reg, 16);
631 	cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
632 	cs->cs_preg[15] = ZSWR15_BREAK_IE;
633 
634 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, zs_defspeed[zs_consunit]);
635 	cs->cs_preg[12] = tconst;
636 	cs->cs_preg[13] = tconst >> 8;
637 
638 	/*
639 	 * can't use zs_set_speed as we haven't set up the
640 	 * signal sources, and it's not worth it for now
641 	 */
642 
643 	cs->cs_preg[9] &= ~ZSWR9_MASTER_IE;
644 	/* no interrupts until later, after attach. */
645 
646 	s = splhigh();
647 	zs_loadchannelregs(cs);
648 	splx(s);
649 
650 	printf("\nNetBSD/next68k console\n");
651 }
652 
653 /*
654  * Polled console input putchar.
655  */
656 int
657 zscngetc(dev_t dev)
658 {
659 	return (zs_getc(zs_conschan));
660 }
661 
662 /*
663  * Polled console output putchar.
664  */
665 void
666 zscnputc(dev_t dev, int c)
667 {
668 	zs_putc(zs_conschan, c);
669 }
670 
671 /*****************************************************************/
672