xref: /netbsd-src/sys/arch/next68k/dev/zs.c (revision 7fa608457b817eca6e0977b37f758ae064f3c99c) 
1 /*	$NetBSD: zs.c,v 1.29 2007/11/09 00:05:06 ad Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Gordon W. Ross.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * Zilog Z8530 Dual UART driver (machine-dependent part)
41  *
42  * Runs two serial lines per chip using slave drivers.
43  * Plain tty/async lines use the zs_async slave.
44  * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
45  */
46 
47 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56
48  * and then updated to reflect changes in 1.59
49  * by Darrin B Jewell <jewell@mit.edu>  Mon Mar 30 20:24:46 1998
50  */
51 
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.29 2007/11/09 00:05:06 ad Exp $");
54 
55 #include "opt_ddb.h"
56 #include "opt_kgdb.h"
57 #include "opt_serial.h"
58 
59 #include <sys/param.h>
60 #include <sys/systm.h>
61 #include <sys/conf.h>
62 #include <sys/device.h>
63 #include <sys/file.h>
64 #include <sys/ioctl.h>
65 #include <sys/kernel.h>
66 #include <sys/proc.h>
67 #include <sys/tty.h>
68 #include <sys/time.h>
69 #include <sys/syslog.h>
70 
71 #include <machine/autoconf.h>
72 #include <machine/cpu.h>
73 #include <machine/psl.h>
74 
75 #include <dev/cons.h>
76 
77 #include <dev/ic/z8530reg.h>
78 #include <machine/z8530var.h>
79 
80 #include <next68k/next68k/isr.h>
81 
82 #include <next68k/dev/intiovar.h>
83 #include <next68k/dev/zs_cons.h>
84 
85 #include "zsc.h" 	/* NZSC */
86 
87 #if (NZSC < 0)
88 #error "No serial controllers?"
89 #endif
90 
91 /*
92  * Some warts needed by z8530tty.c -
93  * The default parity REALLY needs to be the same as the PROM uses,
94  * or you can not see messages done with printf during boot-up...
95  */
96 int zs_def_cflag = (CREAD | CS8 | HUPCL);
97 
98 /*
99  * The NeXT provides a 3.686400 MHz clock to the ZS chips.
100  */
101 #define PCLK	(9600 * 384)		/* PCLK pin input clock rate */
102 
103 #define	ZS_DELAY()		delay(2)
104 
105 /* The layout of this is hardware-dependent (padding, order). */
106 struct zschan {
107 	volatile u_char	zc_csr;		/* ctrl,status, and indirect access */
108 	u_char		zc_xxx0;
109 	volatile u_char	zc_data;	/* data */
110 	u_char		zc_xxx1;
111 };
112 
113 /* Flags from cninit() */
114 static int zs_hwflags[2];
115 
116 /* Default speed for each channel */
117 static int zs_defspeed[2] = {
118 	9600,	 	/* ttya */
119 	9600,		/* ttyb */
120 };
121 
122 static u_char zs_init_reg[16] = {
123 	0,	/* 0: CMD (reset, etc.) */
124 	0,	/* 1: No interrupts yet. */
125 	0x18 + NEXT_I_IPL(NEXT_I_SCC),	/* 2: IVECT */
126 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
127 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
128 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
129 	0,	/* 6: TXSYNC/SYNCLO */
130 	0,	/* 7: RXSYNC/SYNCHI */
131 	0,	/* 8: alias for data port */
132 	ZSWR9_MASTER_IE,
133 	0,	/*10: Misc. TX/RX control bits */
134 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
135 	((PCLK/32)/9600)-2,	/*12: BAUDLO (default=9600) */
136 	0,			/*13: BAUDHI (default=9600) */
137 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
138 	ZSWR15_BREAK_IE,
139 };
140 
141 struct zschan *
142 zs_get_chan_addr(int channel)
143 {
144 	char *addr;
145 	struct zschan *zc;
146 
147 	addr = (void *)IIOV(NEXT_P_SCC);
148 	if (channel == 0) {
149 		/* handle the fact the ports are intertwined. */
150 		zc = (struct zschan *)(addr + 1);
151 	} else {
152 		zc = (struct zschan *)(addr);
153 	}
154 	return (zc);
155 }
156 
157 
158 /****************************************************************
159  * Autoconfig
160  ****************************************************************/
161 
162 /* Definition of the driver for autoconfig. */
163 static int	zs_match(struct device *, struct cfdata *, void *);
164 static void	zs_attach(struct device *, struct device *, void *);
165 static int	zs_print(void *, const char *);
166 
167 extern int  zs_getc(void *);
168 extern void zs_putc(void *, int);
169 
170 CFATTACH_DECL(zsc, sizeof(struct zsc_softc),
171     zs_match, zs_attach, NULL, NULL);
172 
173 extern struct cfdriver zsc_cd;
174 
175 static int zs_attached;
176 
177 /* Interrupt handlers. */
178 static int zshard(void *);
179 
180 static int zs_get_speed(struct zs_chanstate *);
181 
182 /*
183  * Is the zs chip present?
184  */
185 static int
186 zs_match(struct device *parent, struct cfdata *cf, void *aux)
187 {
188 	struct intio_attach_args *ia = (struct intio_attach_args *)aux;
189 
190 	if (zs_attached)
191 		return 0;
192 
193 	ia->ia_addr = (void *)IIOV(NEXT_P_SCC);
194 
195 	return 1;
196 }
197 
198 /*
199  * Attach a found zs.
200  *
201  * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR
202  * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE?
203  */
204 static void
205 zs_attach(struct device *parent, struct device *self, void *aux)
206 {
207 	struct zsc_softc *zsc = (void *) self;
208 	struct zsc_attach_args zsc_args;
209 	volatile struct zschan *zc;
210 	struct zs_chanstate *cs;
211 	int s, channel;
212 
213 	zs_attached = 1;
214 
215 	printf("\n");
216 
217 	/*
218 	 * Initialize software state for each channel.
219 	 */
220 	for (channel = 0; channel < 2; channel++) {
221 		zsc_args.channel = channel;
222 		zsc_args.hwflags = zs_hwflags[channel];
223 		cs = &zsc->zsc_cs_store[channel];
224 		zsc->zsc_cs[channel] = cs;
225 
226 		zs_lock_init(cs);
227 		cs->cs_channel = channel;
228 		cs->cs_private = NULL;
229 		cs->cs_ops = &zsops_null;
230 		cs->cs_brg_clk = PCLK / 16;
231 
232 		zc = zs_get_chan_addr(channel);
233 		cs->cs_reg_csr  = &zc->zc_csr;
234 		cs->cs_reg_data = &zc->zc_data;
235 
236 		memcpy(cs->cs_creg, zs_init_reg, 16);
237 		memcpy(cs->cs_preg, zs_init_reg, 16);
238 
239 		/* XXX: Get these from the PROM properties! */
240 		/* XXX: See the mvme167 code.  Better. */
241 		if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
242 			cs->cs_defspeed = zs_get_speed(cs);
243 		else
244 			cs->cs_defspeed = zs_defspeed[channel];
245 		cs->cs_defcflag = zs_def_cflag;
246 
247 		/* Make these correspond to cs_defcflag (-crtscts) */
248 		cs->cs_rr0_dcd = ZSRR0_DCD;
249 		cs->cs_rr0_cts = 0;
250 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
251 		cs->cs_wr5_rts = 0;
252 
253 		/*
254 		 * Clear the master interrupt enable.
255 		 * The INTENA is common to both channels,
256 		 * so just do it on the A channel.
257 		 */
258 		if (channel == 0) {
259 			zs_write_reg(cs, 9, 0);
260 		}
261 
262 		/*
263 		 * Look for a child driver for this channel.
264 		 * The child attach will setup the hardware.
265 		 */
266 		if (!config_found(self, (void *)&zsc_args, zs_print)) {
267 			/* No sub-driver.  Just reset it. */
268 			u_char reset = (channel == 0) ?
269 				ZSWR9_A_RESET : ZSWR9_B_RESET;
270 			s = splzs();
271 			zs_write_reg(cs,  9, reset);
272 			splx(s);
273 		}
274 	}
275 
276 	isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0, NULL);
277 	zsc->zsc_softintr_cookie = softintr_establish(IPL_SOFTSERIAL,
278 	    (void (*)(void *))zsc_intr_soft, zsc);
279 	INTR_ENABLE(NEXT_I_SCC);
280 
281 	/*
282 	 * Set the master interrupt enable and interrupt vector.
283 	 * (common to both channels, do it on A)
284 	 */
285 	cs = zsc->zsc_cs[0];
286 	s = splhigh();
287 	/* interrupt vector */
288 	zs_write_reg(cs, 2, zs_init_reg[2]);
289 	/* master interrupt control (enable) */
290 	zs_write_reg(cs, 9, zs_init_reg[9]);
291 	splx(s);
292 }
293 
294 static int
295 zs_print(void *aux, const char *name)
296 {
297 	struct zsc_attach_args *args = aux;
298 
299 	if (name != NULL)
300 		aprint_normal("%s: ", name);
301 
302 	if (args->channel != -1)
303 		aprint_normal(" channel %d", args->channel);
304 
305 	return (UNCONF);
306 }
307 
308 static volatile int zssoftpending;
309 
310 /*
311  * Our ZS chips all share a common, autovectored interrupt,
312  * so we have to look at all of them on each interrupt.
313  */
314 static int
315 zshard(void *arg)
316 {
317 	struct zsc_softc *zsc;
318 	int unit, rr3, rval;
319 
320 	if (!INTR_OCCURRED(NEXT_I_SCC))
321 		return 0;
322 
323 	rval = 0;
324 	for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
325 		zsc = zsc_cd.cd_devs[unit];
326 		if (zsc == NULL)
327 			continue;
328 		rr3 = zsc_intr_hard(zsc);
329 		/* Count up the interrupts. */
330 		if (rr3) {
331 			rval |= rr3;
332 			zsc->zsc_intrcnt.ev_count++;
333 		}
334 		/* We are at splzs here, so no need to lock. */
335 		if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
336 			softintr_schedule(zsc->zsc_softintr_cookie);
337 	}
338 
339 	return(1);
340 }
341 
342 /*
343  * Compute the current baud rate given a ZS channel.
344  */
345 static int
346 zs_get_speed(struct zs_chanstate *cs)
347 {
348 	int tconst;
349 
350 	tconst = zs_read_reg(cs, 12);
351 	tconst |= zs_read_reg(cs, 13) << 8;
352 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
353 }
354 
355 /*
356  * MD functions for setting the baud rate and control modes.
357  */
358 int
359 zs_set_speed(struct zs_chanstate *cs, int bps)
360 {
361 	int tconst, real_bps;
362 
363 	if (bps == 0)
364 		return (0);
365 
366 #ifdef	DIAGNOSTIC
367 	if (cs->cs_brg_clk == 0)
368 		panic("zs_set_speed");
369 #endif
370 
371 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
372 	if (tconst < 0)
373 		return (EINVAL);
374 
375 	/* Convert back to make sure we can do it. */
376 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
377 
378 	/* XXX - Allow some tolerance here? */
379 	if (real_bps != bps)
380 		return (EINVAL);
381 
382 	cs->cs_preg[12] = tconst;
383 	cs->cs_preg[13] = tconst >> 8;
384 
385 	/* Caller will stuff the pending registers. */
386 	return (0);
387 }
388 
389 int
390 zs_set_modes(struct zs_chanstate *cs, int cflag)
391 {
392 	int s;
393 
394 	/*
395 	 * Output hardware flow control on the chip is horrendous:
396 	 * if carrier detect drops, the receiver is disabled, and if
397 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
398 	 * Therefore, NEVER set the HFC bit, and instead use the
399 	 * status interrupt to detect CTS changes.
400 	 */
401 	s = splzs();
402 	cs->cs_rr0_pps = 0;
403 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
404 		cs->cs_rr0_dcd = 0;
405 		if ((cflag & MDMBUF) == 0)
406 			cs->cs_rr0_pps = ZSRR0_DCD;
407 	} else
408 		cs->cs_rr0_dcd = ZSRR0_DCD;
409 	if ((cflag & CRTSCTS) != 0) {
410 		cs->cs_wr5_dtr = ZSWR5_DTR;
411 		cs->cs_wr5_rts = ZSWR5_RTS;
412 		cs->cs_rr0_cts = ZSRR0_CTS;
413 	} else if ((cflag & CDTRCTS) != 0) {
414 		cs->cs_wr5_dtr = 0;
415 		cs->cs_wr5_rts = ZSWR5_DTR;
416 		cs->cs_rr0_cts = ZSRR0_CTS;
417 	} else if ((cflag & MDMBUF) != 0) {
418 		cs->cs_wr5_dtr = 0;
419 		cs->cs_wr5_rts = ZSWR5_DTR;
420 		cs->cs_rr0_cts = ZSRR0_DCD;
421 	} else {
422 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
423 		cs->cs_wr5_rts = 0;
424 		cs->cs_rr0_cts = 0;
425 	}
426 	splx(s);
427 
428 	/* Caller will stuff the pending registers. */
429 	return (0);
430 }
431 
432 /*
433  * Read or write the chip with suitable delays.
434  */
435 
436 u_char
437 zs_read_reg(struct zs_chanstate *cs, u_char reg)
438 {
439 	u_char val;
440 
441 	*cs->cs_reg_csr = reg;
442 	ZS_DELAY();
443 	val = *cs->cs_reg_csr;
444 	ZS_DELAY();
445 	return (val);
446 }
447 
448 void
449 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)
450 {
451 	*cs->cs_reg_csr = reg;
452 	ZS_DELAY();
453 	*cs->cs_reg_csr = val;
454 	ZS_DELAY();
455 }
456 
457 u_char
458 zs_read_csr(struct zs_chanstate *cs)
459 {
460 	u_char val;
461 
462 	val = *cs->cs_reg_csr;
463 	ZS_DELAY();
464 	return (val);
465 }
466 
467 void
468 zs_write_csr(struct zs_chanstate *cs, u_char val)
469 {
470 	*cs->cs_reg_csr = val;
471 	ZS_DELAY();
472 }
473 
474 u_char
475 zs_read_data(struct zs_chanstate *cs)
476 {
477 	u_char val;
478 
479 	val = *cs->cs_reg_data;
480 	ZS_DELAY();
481 	return (val);
482 }
483 
484 void
485 zs_write_data(struct zs_chanstate *cs, u_char val)
486 {
487 	*cs->cs_reg_data = val;
488 	ZS_DELAY();
489 }
490 
491 /****************************************************************
492  * Console support functions (Sun specific!)
493  * Note: this code is allowed to know about the layout of
494  * the chip registers, and uses that to keep things simple.
495  * XXX - I think I like the mvme167 code better. -gwr
496  ****************************************************************/
497 
498 extern void Debugger(void);
499 void *zs_conschan;
500 int	zs_consunit = 0;
501 
502 /*
503  * Handle user request to enter kernel debugger.
504  */
505 void
506 zs_abort(struct zs_chanstate *cs)
507 {
508 #if defined(ZS_CONSOLE_ABORT)
509 	volatile struct zschan *zc = zs_conschan;
510 	int rr0;
511 
512 	/* Wait for end of break to avoid PROM abort. */
513 	/* XXX - Limit the wait? */
514 	do {
515 		rr0 = zc->zc_csr;
516 		ZS_DELAY();
517 	} while (rr0 & ZSRR0_BREAK);
518 
519 #if defined(KGDB)
520 	zskgdb(cs);
521 #elif defined(DDB)
522 	Debugger();
523 #else
524 	/* XXX eventually, drop into next rom monitor here */
525 	printf("stopping on keyboard abort not supported without DDB or KGDB\n");
526 #endif
527 #else /* !ZS_CONSOLE_ABORT */
528 	return;
529 #endif
530 }
531 
532 /*
533  * Polled input char.
534  */
535 int
536 zs_getc(void *arg)
537 {
538 	volatile struct zschan *zc = arg;
539 	int s, c, rr0;
540 
541 	s = splhigh();
542 	/* Wait for a character to arrive. */
543 	do {
544 		rr0 = zc->zc_csr;
545 		ZS_DELAY();
546 	} while ((rr0 & ZSRR0_RX_READY) == 0);
547 
548 	c = zc->zc_data;
549 	ZS_DELAY();
550 	splx(s);
551 
552 	/*
553 	 * This is used by the kd driver to read scan codes,
554 	 * so don't translate '\r' ==> '\n' here...
555 	 */
556 	return (c);
557 }
558 
559 /*
560  * Polled output char.
561  */
562 void
563 zs_putc(void *arg, int c)
564 {
565 	volatile struct zschan *zc = arg;
566 	int s, rr0;
567 
568 	s = splhigh();
569 	/* Wait for transmitter to become ready. */
570 	do {
571 		rr0 = zc->zc_csr;
572 		ZS_DELAY();
573 	} while ((rr0 & ZSRR0_TX_READY) == 0);
574 
575 
576 	zc->zc_data = c;
577 	ZS_DELAY();
578 
579 	splx(s);
580 }
581 
582 /*****************************************************************/
583 
584 void zscninit(struct consdev *);
585 int  zscngetc(dev_t);
586 void zscnputc(dev_t, int);
587 void zscnprobe(struct consdev *);
588 
589 void
590 zscnprobe(struct consdev *cp)
591 {
592 	extern const struct cdevsw zstty_cdevsw;
593 	int     maj;
594 
595 	maj = cdevsw_lookup_major(&zstty_cdevsw);
596 	if (maj != -1) {
597 #ifdef SERCONSOLE
598 		cp->cn_pri = CN_REMOTE;
599 #else
600 		cp->cn_pri = CN_NORMAL;		 /* Lower than CN_INTERNAL */
601 #endif
602 		zs_consunit = 0;
603 		cp->cn_dev = makedev(maj, zs_consunit);
604 		zs_conschan = zs_get_chan_addr(zs_consunit);
605 	} else {
606 		cp->cn_pri = CN_DEAD;
607 	}
608 }
609 
610 void
611 zscninit(struct consdev *cn)
612 {
613 	struct zs_chanstate xcs;
614 	struct zs_chanstate *cs;
615 	volatile struct zschan *zc;
616 	int tconst, s;
617 
618 	zs_hwflags[zs_consunit] = ZS_HWFLAG_CONSOLE;
619 
620 	/* Setup temporary chanstate. */
621 	memset(&xcs, 0, sizeof(xcs));
622 	cs = &xcs;
623 	zc = zs_conschan;
624 	cs->cs_reg_csr  = &zc->zc_csr;
625 	cs->cs_reg_data = &zc->zc_data;
626 	cs->cs_channel = zs_consunit;
627 	cs->cs_brg_clk = PCLK / 16;
628 
629 	memcpy(cs->cs_preg, zs_init_reg, 16);
630 	cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
631 	cs->cs_preg[15] = ZSWR15_BREAK_IE;
632 
633 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, zs_defspeed[zs_consunit]);
634 	cs->cs_preg[12] = tconst;
635 	cs->cs_preg[13] = tconst >> 8;
636 
637 	/*
638 	 * can't use zs_set_speed as we haven't set up the
639 	 * signal sources, and it's not worth it for now
640 	 */
641 
642 	cs->cs_preg[9] &= ~ZSWR9_MASTER_IE;
643 	/* no interrupts until later, after attach. */
644 
645 	s = splhigh();
646 	zs_loadchannelregs(cs);
647 	splx(s);
648 
649 	printf("\nNetBSD/next68k console\n");
650 }
651 
652 /*
653  * Polled console input putchar.
654  */
655 int
656 zscngetc(dev_t dev)
657 {
658 	return (zs_getc(zs_conschan));
659 }
660 
661 /*
662  * Polled console output putchar.
663  */
664 void
665 zscnputc(dev_t dev, int c)
666 {
667 	zs_putc(zs_conschan, c);
668 }
669 
670 /*****************************************************************/
671