xref: /netbsd-src/sys/arch/newsmips/include/intr.h (revision 8b0f9554ff8762542c4defc4f70e1eb76fb508fa)
1 /*	$NetBSD: intr.h,v 1.22 2007/12/03 15:34:04 ad Exp $	*/
2 
3 /*-
4  * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *	This product includes software developed by the NetBSD
21  *	Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 #ifndef _MACHINE_INTR_H_
40 #define _MACHINE_INTR_H_
41 
42 #define IPL_NONE	0	/* disable only this interrupt */
43 #define IPL_SOFTCLOCK	1	/* clock software interrupts (SI 0) */
44 #define IPL_SOFTBIO	1	/* bio software interrupts (SI 0) */
45 #define IPL_SOFTNET	2	/* network software interrupts (SI 1) */
46 #define IPL_SOFTSERIAL	2	/* serial software interrupts (SI 1) */
47 #define	IPL_VM		3
48 #define IPL_SCHED	4	/* disable clock interrupts */
49 #define IPL_HIGH	4	/* disable all interrupts */
50 
51 #define _IPL_N		5
52 
53 #define _IPL_SI0_FIRST	IPL_SOFTCLOCK
54 #define _IPL_SI0_LAST	IPL_SOFTBIO
55 
56 #define _IPL_SI1_FIRST	IPL_SOFTNET
57 #define _IPL_SI1_LAST	IPL_SOFTSERIAL
58 
59 #ifdef _KERNEL
60 #ifndef _LOCORE
61 
62 #include <sys/device.h>
63 #include <mips/locore.h>
64 
65 extern const uint32_t ipl_sr_bits[_IPL_N];
66 
67 #define spl0()		(void)_spllower(0)
68 #define splx(s)		(void)_splset(s)
69 
70 #define splsoft()	_splraise(ipl_sr_bits[IPL_SOFT])
71 
72 typedef int ipl_t;
73 typedef struct {
74 	ipl_t _sr;
75 } ipl_cookie_t;
76 
77 static inline ipl_cookie_t
78 makeiplcookie(ipl_t ipl)
79 {
80 
81 	return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
82 }
83 
84 static inline int
85 splraiseipl(ipl_cookie_t icookie)
86 {
87 
88 	return _splraise(icookie._sr);
89 }
90 
91 #include <sys/spl.h>
92 
93 struct newsmips_intrhand {
94 	LIST_ENTRY(newsmips_intrhand) ih_q;
95 	struct evcnt intr_count;
96 	int (*ih_func)(void *);
97 	void *ih_arg;
98 	u_int ih_level;
99 	u_int ih_mask;
100 	u_int ih_priority;
101 };
102 
103 struct newsmips_intr {
104 	LIST_HEAD(,newsmips_intrhand) intr_q;
105 };
106 
107 /*
108  * Index into intrcnt[], which is defined in locore
109  */
110 #define SERIAL0_INTR	0
111 #define SERIAL1_INTR	1
112 #define SERIAL2_INTR	2
113 #define LANCE_INTR	3
114 #define SCSI_INTR	4
115 #define ERROR_INTR	5
116 #define HARDCLOCK_INTR	6
117 #define FPU_INTR	7
118 #define SLOT1_INTR	8
119 #define SLOT2_INTR	9
120 #define SLOT3_INTR	10
121 #define FLOPPY_INTR	11
122 #define STRAY_INTR	12
123 
124 extern u_int intrcnt[];
125 
126 /* handle i/o device interrupts */
127 #ifdef news3400
128 void news3400_intr(uint32_t, uint32_t, uint32_t, uint32_t);
129 #endif
130 #ifdef news5000
131 void news5000_intr(uint32_t, uint32_t, uint32_t, uint32_t);
132 #endif
133 extern void (*hardware_intr)(uint32_t, uint32_t, uint32_t, uint32_t);
134 
135 extern void (*enable_intr)(void);
136 extern void (*disable_intr)(void);
137 extern void (*enable_timer)(void);
138 
139 #endif /* !_LOCORE */
140 #endif /* _KERNEL */
141 #endif /* _MACHINE_INTR_H_ */
142