1 /* $NetBSD: zs.c,v 1.21 2005/12/11 12:18:24 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.21 2005/12/11 12:18:24 christos Exp $"); 49 50 #include "opt_ddb.h" 51 52 #include <sys/param.h> 53 #include <sys/device.h> 54 #include <sys/tty.h> 55 #include <sys/systm.h> 56 57 #include <machine/adrsmap.h> 58 #include <machine/cpu.h> 59 #include <machine/z8530var.h> 60 61 #include <dev/ic/z8530reg.h> 62 63 #define ZS_DELAY() (*zs_delay)() 64 65 extern struct cfdriver zsc_cd; 66 67 /* 68 * Some warts needed by z8530tty.c - 69 * The default parity REALLY needs to be the same as the PROM uses, 70 * or you can not see messages done with printf during boot-up... 71 */ 72 int zs_def_cflag = (CREAD | CS8 | HUPCL); 73 74 int 75 zs_print(void *aux, const char *name) 76 { 77 struct zsc_attach_args *args = aux; 78 79 if (name != NULL) 80 aprint_normal("%s: ", name); 81 82 if (args->channel != -1) 83 aprint_normal(" channel %d", args->channel); 84 85 return UNCONF; 86 } 87 88 /* 89 * Our ZS chips all share a common, autovectored interrupt, 90 * so we have to look at all of them on each interrupt. 91 */ 92 int 93 zshard(void *arg) 94 { 95 struct zsc_softc *zsc; 96 int unit, rval, softreq; 97 98 rval = 0; 99 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 100 zsc = zsc_cd.cd_devs[unit]; 101 if (zsc == NULL) 102 continue; 103 rval |= zsc_intr_hard(zsc); 104 softreq = zsc->zsc_cs[0]->cs_softreq; 105 softreq |= zsc->zsc_cs[1]->cs_softreq; 106 if (softreq) 107 softintr_schedule(zsc->zsc_si); 108 } 109 110 return rval; 111 } 112 113 /* 114 * Similar scheme as for zshard (look at all of them) 115 */ 116 void 117 zssoft(void *arg) 118 { 119 struct zsc_softc *zsc; 120 int s, unit; 121 122 /* Make sure we call the tty layer at spltty. */ 123 s = spltty(); 124 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 125 zsc = zsc_cd.cd_devs[unit]; 126 if (zsc == NULL) 127 continue; 128 (void)zsc_intr_soft(zsc); 129 } 130 splx(s); 131 } 132 133 /* 134 * Compute the current baud rate given a ZS channel. 135 */ 136 int 137 zs_get_speed(struct zs_chanstate *cs) 138 { 139 int tconst; 140 141 tconst = zs_read_reg(cs, 12); 142 tconst |= zs_read_reg(cs, 13) << 8; 143 return TCONST_TO_BPS(cs->cs_brg_clk, tconst); 144 } 145 146 /* 147 * MD functions for setting the baud rate and control modes. 148 */ 149 int 150 zs_set_speed(struct zs_chanstate *cs, int bps) 151 { 152 int tconst, real_bps; 153 154 if (bps == 0) 155 return 0; 156 157 #ifdef DIAGNOSTIC 158 if (cs->cs_brg_clk == 0) 159 panic("zs_set_speed"); 160 #endif 161 162 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 163 if (tconst < 0) 164 return EINVAL; 165 166 /* Convert back to make sure we can do it. */ 167 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 168 169 /* XXX - Allow some tolerance here? */ 170 if (real_bps != bps) 171 return EINVAL; 172 173 cs->cs_preg[12] = tconst; 174 cs->cs_preg[13] = tconst >> 8; 175 176 /* Caller will stuff the pending registers. */ 177 return 0; 178 } 179 180 int 181 zs_set_modes(struct zs_chanstate *cs, int cflag) 182 { 183 int s; 184 185 /* 186 * Output hardware flow control on the chip is horrendous: 187 * if carrier detect drops, the receiver is disabled, and if 188 * CTS drops, the transmitter is stoped IN MID CHARACTER! 189 * Therefore, NEVER set the HFC bit, and instead use the 190 * status interrupt to detect CTS changes. 191 */ 192 s = splserial(); 193 cs->cs_rr0_pps = 0; 194 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 195 cs->cs_rr0_dcd = 0; 196 if ((cflag & MDMBUF) == 0) 197 cs->cs_rr0_pps = ZSRR0_DCD; 198 } else 199 cs->cs_rr0_dcd = ZSRR0_DCD; 200 if ((cflag & CRTSCTS) != 0) { 201 cs->cs_wr5_dtr = ZSWR5_DTR; 202 cs->cs_wr5_rts = ZSWR5_RTS; 203 cs->cs_rr0_cts = ZSRR0_CTS; 204 } else if ((cflag & MDMBUF) != 0) { 205 cs->cs_wr5_dtr = 0; 206 cs->cs_wr5_rts = ZSWR5_DTR; 207 cs->cs_rr0_cts = ZSRR0_DCD; 208 } else { 209 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 210 cs->cs_wr5_rts = 0; 211 cs->cs_rr0_cts = 0; 212 } 213 splx(s); 214 215 /* Caller will stuff the pending registers. */ 216 return 0; 217 } 218 219 /* 220 * Read or write the chip with suitable delays. 221 */ 222 223 u_char 224 zs_read_reg(struct zs_chanstate *cs, u_char reg) 225 { 226 u_char val; 227 228 *cs->cs_reg_csr = reg; 229 ZS_DELAY(); 230 val = *cs->cs_reg_csr; 231 ZS_DELAY(); 232 return val; 233 } 234 235 void 236 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val) 237 { 238 239 *cs->cs_reg_csr = reg; 240 ZS_DELAY(); 241 *cs->cs_reg_csr = val; 242 ZS_DELAY(); 243 } 244 245 u_char zs_read_csr(struct zs_chanstate *cs) 246 { 247 u_char val; 248 249 val = *cs->cs_reg_csr; 250 ZS_DELAY(); 251 return val; 252 } 253 254 void zs_write_csr(struct zs_chanstate *cs, u_char val) 255 { 256 257 *cs->cs_reg_csr = val; 258 ZS_DELAY(); 259 } 260 261 u_char zs_read_data(struct zs_chanstate *cs) 262 { 263 u_char val; 264 265 val = *cs->cs_reg_data; 266 ZS_DELAY(); 267 return val; 268 } 269 270 void zs_write_data(struct zs_chanstate *cs, u_char val) 271 { 272 273 *cs->cs_reg_data = val; 274 ZS_DELAY(); 275 } 276 277 void 278 zs_abort(struct zs_chanstate *cs) 279 { 280 281 #ifdef DDB 282 Debugger(); 283 #endif 284 } 285