1 /* $NetBSD: zs.c,v 1.26 2010/06/26 03:44:49 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Zilog Z8530 Dual UART driver (machine-dependent part) 34 * 35 * Runs two serial lines per chip using slave drivers. 36 * Plain tty/async lines use the zs_async slave. 37 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.26 2010/06/26 03:44:49 tsutsui Exp $"); 42 43 #include "opt_ddb.h" 44 45 #include <sys/param.h> 46 #include <sys/device.h> 47 #include <sys/tty.h> 48 #include <sys/systm.h> 49 #include <sys/cpu.h> 50 #include <sys/intr.h> 51 52 #include <machine/adrsmap.h> 53 #include <machine/z8530var.h> 54 55 #include <dev/ic/z8530reg.h> 56 57 #include "ioconf.h" 58 59 #define ZS_DELAY() (*zs_delay)() 60 61 /* 62 * Some warts needed by z8530tty.c - 63 * The default parity REALLY needs to be the same as the PROM uses, 64 * or you can not see messages done with printf during boot-up... 65 */ 66 int zs_def_cflag = (CREAD | CS8 | HUPCL); 67 68 int 69 zs_print(void *aux, const char *name) 70 { 71 struct zsc_attach_args *args = aux; 72 73 if (name != NULL) 74 aprint_normal("%s: ", name); 75 76 if (args->channel != -1) 77 aprint_normal(" channel %d", args->channel); 78 79 return UNCONF; 80 } 81 82 /* 83 * Our ZS chips all share a common interrupt level, 84 * but we establish zshard handler per each ZS chips 85 * to avoid holding unnecessary locks in interrupt context. 86 */ 87 int 88 zshard(void *arg) 89 { 90 struct zsc_softc *zsc = arg; 91 int rval; 92 93 rval = zsc_intr_hard(zsc); 94 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) 95 softint_schedule(zsc->zsc_si); 96 97 return rval; 98 } 99 100 /* 101 * Compute the current baud rate given a ZS channel. 102 */ 103 int 104 zs_get_speed(struct zs_chanstate *cs) 105 { 106 int tconst; 107 108 tconst = zs_read_reg(cs, 12); 109 tconst |= zs_read_reg(cs, 13) << 8; 110 return TCONST_TO_BPS(cs->cs_brg_clk, tconst); 111 } 112 113 /* 114 * MD functions for setting the baud rate and control modes. 115 */ 116 int 117 zs_set_speed(struct zs_chanstate *cs, int bps) 118 { 119 int tconst, real_bps; 120 121 if (bps == 0) 122 return 0; 123 124 #ifdef DIAGNOSTIC 125 if (cs->cs_brg_clk == 0) 126 panic("zs_set_speed"); 127 #endif 128 129 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 130 if (tconst < 0) 131 return EINVAL; 132 133 /* Convert back to make sure we can do it. */ 134 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 135 136 /* XXX - Allow some tolerance here? */ 137 if (real_bps != bps) 138 return EINVAL; 139 140 cs->cs_preg[12] = tconst; 141 cs->cs_preg[13] = tconst >> 8; 142 143 /* Caller will stuff the pending registers. */ 144 return 0; 145 } 146 147 int 148 zs_set_modes(struct zs_chanstate *cs, int cflag) 149 { 150 int s; 151 152 /* 153 * Output hardware flow control on the chip is horrendous: 154 * if carrier detect drops, the receiver is disabled, and if 155 * CTS drops, the transmitter is stoped IN MID CHARACTER! 156 * Therefore, NEVER set the HFC bit, and instead use the 157 * status interrupt to detect CTS changes. 158 */ 159 s = splserial(); 160 cs->cs_rr0_pps = 0; 161 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 162 cs->cs_rr0_dcd = 0; 163 if ((cflag & MDMBUF) == 0) 164 cs->cs_rr0_pps = ZSRR0_DCD; 165 } else 166 cs->cs_rr0_dcd = ZSRR0_DCD; 167 if ((cflag & CRTSCTS) != 0) { 168 cs->cs_wr5_dtr = ZSWR5_DTR; 169 cs->cs_wr5_rts = ZSWR5_RTS; 170 cs->cs_rr0_cts = ZSRR0_CTS; 171 } else if ((cflag & MDMBUF) != 0) { 172 cs->cs_wr5_dtr = 0; 173 cs->cs_wr5_rts = ZSWR5_DTR; 174 cs->cs_rr0_cts = ZSRR0_DCD; 175 } else { 176 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 177 cs->cs_wr5_rts = 0; 178 cs->cs_rr0_cts = 0; 179 } 180 splx(s); 181 182 /* Caller will stuff the pending registers. */ 183 return 0; 184 } 185 186 /* 187 * Read or write the chip with suitable delays. 188 */ 189 190 uint8_t 191 zs_read_reg(struct zs_chanstate *cs, uint8_t reg) 192 { 193 uint8_t val; 194 195 *cs->cs_reg_csr = reg; 196 ZS_DELAY(); 197 val = *cs->cs_reg_csr; 198 ZS_DELAY(); 199 return val; 200 } 201 202 void 203 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val) 204 { 205 206 *cs->cs_reg_csr = reg; 207 ZS_DELAY(); 208 *cs->cs_reg_csr = val; 209 ZS_DELAY(); 210 } 211 212 uint8_t 213 zs_read_csr(struct zs_chanstate *cs) 214 { 215 uint8_t val; 216 217 val = *cs->cs_reg_csr; 218 ZS_DELAY(); 219 return val; 220 } 221 222 void 223 zs_write_csr(struct zs_chanstate *cs, uint8_t val) 224 { 225 226 *cs->cs_reg_csr = val; 227 ZS_DELAY(); 228 } 229 230 uint8_t 231 zs_read_data(struct zs_chanstate *cs) 232 { 233 uint8_t val; 234 235 val = *cs->cs_reg_data; 236 ZS_DELAY(); 237 return val; 238 } 239 240 void 241 zs_write_data(struct zs_chanstate *cs, uint8_t val) 242 { 243 244 *cs->cs_reg_data = val; 245 ZS_DELAY(); 246 } 247 248 void 249 zs_abort(struct zs_chanstate *cs) 250 { 251 252 #ifdef DDB 253 Debugger(); 254 #endif 255 } 256