xref: /netbsd-src/sys/arch/news68k/dev/zs.c (revision aaf4ece63a859a04e37cf3a7229b5fab0157cc06) 
1 /*	$NetBSD: zs.c,v 1.22 2005/12/11 12:18:23 christos Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Gordon W. Ross.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * Zilog Z8530 Dual UART driver (machine-dependent part)
41  *
42  * Runs two serial lines per chip using slave drivers.
43  * Plain tty/async lines use the zs_async slave.
44  */
45 
46 /*
47  * news68k/dev/zs.c - based on {newsmips,x68k,mvme68k}/dev/zs.c
48  */
49 
50 #include <sys/cdefs.h>
51 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.22 2005/12/11 12:18:23 christos Exp $");
52 
53 #include "opt_ddb.h"
54 
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/conf.h>
58 #include <sys/device.h>
59 #include <sys/tty.h>
60 
61 #include <machine/cpu.h>
62 #include <machine/z8530var.h>
63 
64 #include <dev/cons.h>
65 #include <dev/ic/z8530reg.h>
66 
67 #include <news68k/dev/hbvar.h>
68 
69 #include "ioconf.h"
70 
71 int  zs_getc(void *);
72 void zs_putc(void *, int);
73 
74 /*
75  * Some warts needed by z8530tty.c -
76  * The default parity REALLY needs to be the same as the PROM uses,
77  * or you can not see messages done with printf during boot-up...
78  */
79 int zs_def_cflag = (CREAD | CS8 | HUPCL);
80 
81 /*
82  * The news68k machines use three different clocks for the ZS chips.
83  */
84 #define NPCLK	3
85 #define PCLK0	(9600 * 416)	/*  news1700: 3.9936MHz */
86 #define PCLK1	(9600 * 512)	/*  news1200: 4.9152MHz */
87 #define PCLK2	(9600 * 384)	/*  external: 3.6864MHz */
88 
89 static const u_int pclk[NPCLK] = {
90 	PCLK0,
91 	PCLK1,
92 	PCLK2,
93 };
94 
95 /*
96  * Define interrupt levels.
97  */
98 #define ZSHARD_PRI 5
99 #define ZS_IVECT 64
100 
101 #define ZS_DELAY() /* delay(2) */
102 
103 /* The layout of this is hardware-dependent (padding, order). */
104 struct zschan {
105 	volatile u_char	zc_csr;		/* ctrl,status, and indirect access */
106 	volatile u_char	zc_data;	/* data */
107 };
108 struct zsdevice {
109 	/* Yes, they are backwards. */
110 	struct	zschan zs_chan_b;
111 	struct	zschan zs_chan_a;
112 };
113 
114 static u_char zs_sir;
115 
116 /* Default speed for all channels */
117 static int zs_defspeed = 9600;
118 
119 /* console status from cninit */
120 static struct zs_chanstate zs_conschan_store;
121 static struct zs_chanstate *zs_conschan;
122 static struct zschan *zc_cons;
123 
124 static u_char zs_init_reg[16] = {
125 	0,	/* 0: CMD (reset, etc.) */
126 	0,	/* 1: No interrupts yet. */
127 	ZS_IVECT,	/* IVECT */
128 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
129 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
130 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
131 	0,	/* 6: TXSYNC/SYNCLO */
132 	0,	/* 7: RXSYNC/SYNCHI */
133 	0,	/* 8: alias for data port */
134 	ZSWR9_MASTER_IE,
135 	0,	/*10: Misc. TX/RX control bits */
136 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
137 	BPS_TO_TCONST((PCLK0/16), 9600), /*12: BAUDLO (default=9600) */
138 	0,			/*13: BAUDHI (default=9600) */
139 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
140 	ZSWR15_BREAK_IE,
141 };
142 
143 
144 /****************************************************************
145  * Autoconfig
146  ****************************************************************/
147 
148 /* Definition of the driver for autoconfig. */
149 static int  zs_match(struct device *, struct cfdata *, void *);
150 static void zs_attach(struct device *, struct device *, void *);
151 static int  zs_print(void *, const char *name);
152 
153 CFATTACH_DECL(zsc, sizeof(struct zsc_softc),
154     zs_match, zs_attach, NULL, NULL);
155 
156 static int zshard(void *);
157 void zssoft(void *);
158 #if 0
159 static int zs_get_speed(struct zs_chanstate *);
160 #endif
161 
162 /*
163  * Is the zs chip present?
164  */
165 static int
166 zs_match(struct device *parent, struct cfdata *cf, void *aux)
167 {
168 	struct hb_attach_args *ha = aux;
169 	u_int addr;
170 
171 	if (strcmp(ha->ha_name, "zsc"))
172 		return 0;
173 
174 	/* XXX no default address */
175 	if (ha->ha_address == (u_int)-1)
176 		return 0;
177 
178 	addr = IIOV(ha->ha_address);
179 	/* This returns -1 on a fault (bus error). */
180 	if (badaddr((void *)addr, 1))
181 		return 0;
182 
183 	return 1;
184 }
185 
186 /*
187  * Attach a found zs.
188  */
189 static void
190 zs_attach(struct device *parent, struct device *self, void *aux)
191 {
192 	struct zsc_softc *zsc = (void *) self;
193 	struct cfdata *cf = self->dv_cfdata;
194 	struct hb_attach_args *ha = aux;
195 	struct zsc_attach_args zsc_args;
196 	struct zsdevice *zs;
197 	struct zschan *zc;
198 	struct zs_chanstate *cs;
199 	int s, channel, clk;
200 
201 	zs = (void *)IIOV(ha->ha_address);
202 
203 	clk = cf->cf_flags;
204 	if (clk < 0 || clk >= NPCLK)
205 		clk = 0;
206 
207 	printf("\n");
208 
209 	/*
210 	 * Initialize software state for each channel.
211 	 */
212 	for (channel = 0; channel < 2; channel++) {
213 		zsc_args.channel = channel;
214 		cs = &zsc->zsc_cs_store[channel];
215 		simple_lock_init(&cs->cs_lock);
216 
217 		zsc->zsc_cs[channel] = cs;
218 		zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b;
219 
220 		if (ha->ha_vect != -1)
221 			zs_init_reg[2] = ha->ha_vect;
222 
223 		if (zc == zc_cons) {
224 			memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
225 			zs_conschan = cs;
226 			zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
227 		} else {
228 			cs->cs_reg_csr  = &zc->zc_csr;
229 			cs->cs_reg_data = &zc->zc_data;
230 			memcpy(cs->cs_creg, zs_init_reg, 16);
231 			memcpy(cs->cs_preg, zs_init_reg, 16);
232 			cs->cs_defspeed = zs_defspeed;
233 			zsc_args.hwflags = 0;
234 		}
235 
236 		cs->cs_defcflag = zs_def_cflag;
237 
238 		cs->cs_channel = channel;
239 		cs->cs_private = NULL;
240 		cs->cs_ops = &zsops_null;
241 		cs->cs_brg_clk = pclk[clk] / 16;
242 
243 		/* Make these correspond to cs_defcflag (-crtscts) */
244 		cs->cs_rr0_dcd = ZSRR0_DCD;
245 		cs->cs_rr0_cts = 0;
246 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
247 		cs->cs_wr5_rts = 0;
248 
249 		/*
250 		 * Clear the master interrupt enable.
251 		 * The INTENA is common to both channels,
252 		 * so just do it on the A channel.
253 		 */
254 		if (channel == 0) {
255 			s = splhigh();
256 			zs_write_reg(cs, 9, 0);
257 			splx(s);
258 		}
259 
260 		/*
261 		 * Look for a child driver for this channel.
262 		 * The child attach will setup the hardware.
263 		 */
264 		if (!config_found(self, (void *)&zsc_args, zs_print)) {
265 			/* No sub-driver.  Just reset it. */
266 			u_char reset = (channel == 0) ?
267 				ZSWR9_A_RESET : ZSWR9_B_RESET;
268 			s = splhigh();
269 			zs_write_reg(cs,  9, reset);
270 			splx(s);
271 		}
272 	}
273 
274 	/*
275 	 * Now safe to install interrupt handlers.
276 	 */
277 	hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc);
278 
279 	/*
280 	 * Set the master interrupt enable and interrupt vector.
281 	 * (common to both channels, do it on A)
282 	 */
283 	cs = zsc->zsc_cs[0];
284 	s = splhigh();
285 	/* interrupt vector */
286 	zs_write_reg(cs, 2, zs_init_reg[2]);
287 	/* master interrupt control (enable) */
288 	zs_write_reg(cs, 9, zs_init_reg[9]);
289 	splx(s);
290 
291 	if (zs_sir == 0)
292 		zs_sir = allocate_sir(zssoft, zsc);
293 }
294 
295 static int
296 zs_print(void *aux, const char *name)
297 {
298 	struct zsc_attach_args *args = aux;
299 
300 	if (name != NULL)
301 		aprint_normal("%s: ", name);
302 
303 	if (args->channel != -1)
304 		aprint_normal(" channel %d", args->channel);
305 
306 	return UNCONF;
307 }
308 
309 /*
310  * For news68k-port, we don't use autovectored interrupt.
311  * We do not need to look at all of the zs chips.
312  */
313 static int
314 zshard(void *arg)
315 {
316 	struct zsc_softc *zsc = arg;
317 	int rval;
318 
319 	rval = zsc_intr_hard(zsc);
320 
321 	/* We are at splzs here, so no need to lock. */
322 	if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) {
323 		setsoftint(zs_sir);
324 	}
325 
326 	return rval;
327 }
328 
329 /*
330  * Shared among the all chips. We have to look at all of them.
331  */
332 void
333 zssoft(void *arg)
334 {
335 	struct zsc_softc *zsc;
336 	int s, unit;
337 
338 	/* Make sure we call the tty layer at spltty. */
339 	s = spltty();
340 	for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
341 		zsc = zsc_cd.cd_devs[unit];
342 		if (zsc == NULL)
343 			continue;
344 		(void) zsc_intr_soft(zsc);
345 	}
346 	splx(s);
347 }
348 
349 /*
350  * Compute the current baud rate given a ZS channel.
351  */
352 #if 0
353 static int
354 zs_get_speed(struct zs_chanstate *cs)
355 {
356 	int tconst;
357 
358 	tconst = zs_read_reg(cs, 12);
359 	tconst |= zs_read_reg(cs, 13) << 8;
360 	return TCONST_TO_BPS(cs->cs_brg_clk, tconst);
361 }
362 #endif
363 
364 /*
365  * MD functions for setting the baud rate and control modes.
366  */
367 int
368 zs_set_speed(struct zs_chanstate *cs, int bps)
369 {
370 	int tconst, real_bps;
371 
372 	if (bps == 0)
373 		return 0;
374 
375 #ifdef	DIAGNOSTIC
376 	if (cs->cs_brg_clk == 0)
377 		panic("zs_set_speed");
378 #endif
379 
380 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
381 	if (tconst < 0)
382 		return EINVAL;
383 
384 	/* Convert back to make sure we can do it. */
385 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
386 
387 	/* XXX - Allow some tolerance here? */
388 	if (real_bps != bps)
389 		return EINVAL;
390 
391 	cs->cs_preg[12] = tconst;
392 	cs->cs_preg[13] = tconst >> 8;
393 
394 	/* Caller will stuff the pending registers. */
395 	return 0;
396 }
397 
398 int
399 zs_set_modes(struct zs_chanstate *cs, int cflag)
400 {
401 	int s;
402 
403 	/*
404 	 * Output hardware flow control on the chip is horrendous:
405 	 * if carrier detect drops, the receiver is disabled, and if
406 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
407 	 * Therefore, NEVER set the HFC bit, and instead use the
408 	 * status interrupt to detect CTS changes.
409 	 */
410 	s = splzs();
411 	cs->cs_rr0_pps = 0;
412 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
413 		cs->cs_rr0_dcd = 0;
414 		if ((cflag & MDMBUF) == 0)
415 			cs->cs_rr0_pps = ZSRR0_DCD;
416 	} else
417 		cs->cs_rr0_dcd = ZSRR0_DCD;
418 	if ((cflag & CRTSCTS) != 0) {
419 		cs->cs_wr5_dtr = ZSWR5_DTR;
420 		cs->cs_wr5_rts = ZSWR5_RTS;
421 		cs->cs_rr0_cts = ZSRR0_CTS;
422 	} else if ((cflag & MDMBUF) != 0) {
423 		cs->cs_wr5_dtr = 0;
424 		cs->cs_wr5_rts = ZSWR5_DTR;
425 		cs->cs_rr0_cts = ZSRR0_DCD;
426 	} else {
427 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
428 		cs->cs_wr5_rts = 0;
429 		cs->cs_rr0_cts = 0;
430 	}
431 	splx(s);
432 
433 	/* Caller will stuff the pending registers. */
434 	return 0;
435 }
436 
437 
438 /*
439  * Read or write the chip with suitable delays.
440  */
441 
442 u_char
443 zs_read_reg(struct zs_chanstate *cs, u_char reg)
444 {
445 	u_char val;
446 
447 	*cs->cs_reg_csr = reg;
448 	ZS_DELAY();
449 	val = *cs->cs_reg_csr;
450 	ZS_DELAY();
451 	return val;
452 }
453 
454 void
455 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)
456 {
457 
458 	*cs->cs_reg_csr = reg;
459 	ZS_DELAY();
460 	*cs->cs_reg_csr = val;
461 	ZS_DELAY();
462 }
463 
464 u_char
465 zs_read_csr(struct zs_chanstate *cs)
466 {
467 	u_char val;
468 
469 	val = *cs->cs_reg_csr;
470 	ZS_DELAY();
471 	return val;
472 }
473 
474 void
475 zs_write_csr(struct zs_chanstate *cs, u_char val)
476 {
477 
478 	*cs->cs_reg_csr = val;
479 	ZS_DELAY();
480 }
481 
482 u_char
483 zs_read_data(struct zs_chanstate *cs)
484 {
485 	u_char val;
486 
487 	val = *cs->cs_reg_data;
488 	ZS_DELAY();
489 	return val;
490 }
491 
492 void
493 zs_write_data(struct zs_chanstate *cs, u_char val)
494 {
495 
496 	*cs->cs_reg_data = val;
497 	ZS_DELAY();
498 }
499 
500 void
501 zs_abort(struct zs_chanstate *cs)
502 {
503 
504 #ifdef DDB
505 	Debugger();
506 #endif
507 }
508 
509 /*
510  * Polled input char.
511  */
512 int
513 zs_getc(void *arg)
514 {
515 	struct zs_chanstate *cs = arg;
516 	int s, c, rr0;
517 
518 	s = splhigh();
519 	/* Wait for a character to arrive. */
520 	do {
521 		rr0 = *cs->cs_reg_csr;
522 		ZS_DELAY();
523 	} while ((rr0 & ZSRR0_RX_READY) == 0);
524 
525 	c = *cs->cs_reg_data;
526 	ZS_DELAY();
527 	splx(s);
528 
529 	return c;
530 }
531 
532 /*
533  * Polled output char.
534  */
535 void
536 zs_putc(void *arg, int c)
537 {
538 	struct zs_chanstate *cs = arg;
539 	int s, rr0;
540 
541 	s = splhigh();
542 	/* Wait for transmitter to become ready. */
543 	do {
544 		rr0 = *cs->cs_reg_csr;
545 		ZS_DELAY();
546 	} while ((rr0 & ZSRR0_TX_READY) == 0);
547 
548 	*cs->cs_reg_data = c;
549 	ZS_DELAY();
550 	splx(s);
551 }
552 
553 /*****************************************************************/
554 
555 static void zscnprobe(struct consdev *);
556 static void zscninit(struct consdev *);
557 static int  zscngetc(dev_t);
558 static void zscnputc(dev_t, int);
559 
560 struct consdev consdev_zs = {
561 	zscnprobe,
562 	zscninit,
563 	zscngetc,
564 	zscnputc,
565 	nullcnpollc,
566 	NULL,
567 	NULL,
568 	NULL,
569 	NODEV,
570 	CN_DEAD
571 };
572 
573 static void
574 zscnprobe(struct consdev *cn)
575 {
576 }
577 
578 static void
579 zscninit(struct consdev *cn)
580 {
581 	struct zs_chanstate *cs;
582 
583 	extern const struct cdevsw zstty_cdevsw;
584 	extern int tty00_is_console;
585 	extern uint32_t sccport0a;
586 
587 	cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
588 	if (tty00_is_console)
589 		cn->cn_pri = CN_REMOTE;
590 	else
591 		cn->cn_pri = CN_NORMAL;
592 
593 	zc_cons = (struct zschan *)sccport0a; /* XXX */
594 
595 	zs_conschan = cs = &zs_conschan_store;
596 
597 	/* Setup temporary chanstate. */
598 	cs->cs_reg_csr  = &zc_cons->zc_csr;
599 	cs->cs_reg_data = &zc_cons->zc_data;
600 
601 	/* Initialize the pending registers. */
602 	memcpy(cs->cs_preg, zs_init_reg, 16);
603 	cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
604 
605 	cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */
606 	cs->cs_preg[13] = 0;
607 	cs->cs_defspeed = 9600;
608 
609 	/* Clear the master interrupt enable. */
610 	zs_write_reg(cs, 9, 0);
611 
612 	/* Reset the whole SCC chip. */
613 	zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
614 
615 	/* Copy "pending" to "current" and H/W */
616 	zs_loadchannelregs(cs);
617 }
618 
619 static int
620 zscngetc(dev_t dev)
621 {
622 
623 	return zs_getc((void *)zs_conschan);
624 }
625 
626 static void
627 zscnputc(dev_t dev, int c)
628 {
629 
630 	zs_putc((void *)zs_conschan, c);
631 }
632