xref: /netbsd-src/sys/arch/news68k/dev/zs.c (revision 8b0f9554ff8762542c4defc4f70e1eb76fb508fa) 
1 /*	$NetBSD: zs.c,v 1.28 2007/12/03 15:34:02 ad Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Gordon W. Ross.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * Zilog Z8530 Dual UART driver (machine-dependent part)
41  *
42  * Runs two serial lines per chip using slave drivers.
43  * Plain tty/async lines use the zs_async slave.
44  */
45 
46 /*
47  * news68k/dev/zs.c - based on {newsmips,x68k,mvme68k}/dev/zs.c
48  */
49 
50 #include <sys/cdefs.h>
51 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.28 2007/12/03 15:34:02 ad Exp $");
52 
53 #include "opt_ddb.h"
54 
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/conf.h>
58 #include <sys/device.h>
59 #include <sys/tty.h>
60 #include <sys/cpu.h>
61 #include <sys/intr.h>
62 
63 #include <machine/z8530var.h>
64 
65 #include <dev/cons.h>
66 #include <dev/ic/z8530reg.h>
67 
68 #include <news68k/dev/hbvar.h>
69 
70 #include "ioconf.h"
71 
72 int  zs_getc(void *);
73 void zs_putc(void *, int);
74 
75 /*
76  * Some warts needed by z8530tty.c -
77  * The default parity REALLY needs to be the same as the PROM uses,
78  * or you can not see messages done with printf during boot-up...
79  */
80 int zs_def_cflag = (CREAD | CS8 | HUPCL);
81 
82 /*
83  * The news68k machines use three different clocks for the ZS chips.
84  */
85 #define NPCLK	3
86 #define PCLK0	(9600 * 416)	/*  news1700: 3.9936MHz */
87 #define PCLK1	(9600 * 512)	/*  news1200: 4.9152MHz */
88 #define PCLK2	(9600 * 384)	/*  external: 3.6864MHz */
89 
90 static const u_int pclk[NPCLK] = {
91 	PCLK0,
92 	PCLK1,
93 	PCLK2,
94 };
95 
96 /*
97  * Define interrupt levels.
98  */
99 #define ZSHARD_PRI 5
100 #define ZS_IVECT 64
101 
102 #define ZS_DELAY() /* delay(2) */
103 
104 /* The layout of this is hardware-dependent (padding, order). */
105 struct zschan {
106 	volatile u_char	zc_csr;		/* ctrl,status, and indirect access */
107 	volatile u_char	zc_data;	/* data */
108 };
109 struct zsdevice {
110 	/* Yes, they are backwards. */
111 	struct	zschan zs_chan_b;
112 	struct	zschan zs_chan_a;
113 };
114 
115 /* Default speed for all channels */
116 static int zs_defspeed = 9600;
117 
118 /* console status from cninit */
119 static struct zs_chanstate zs_conschan_store;
120 static struct zs_chanstate *zs_conschan;
121 static struct zschan *zc_cons;
122 
123 static u_char zs_init_reg[16] = {
124 	0,	/* 0: CMD (reset, etc.) */
125 	0,	/* 1: No interrupts yet. */
126 	ZS_IVECT,	/* IVECT */
127 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
128 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
129 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
130 	0,	/* 6: TXSYNC/SYNCLO */
131 	0,	/* 7: RXSYNC/SYNCHI */
132 	0,	/* 8: alias for data port */
133 	ZSWR9_MASTER_IE,
134 	0,	/*10: Misc. TX/RX control bits */
135 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
136 	BPS_TO_TCONST((PCLK0/16), 9600), /*12: BAUDLO (default=9600) */
137 	0,			/*13: BAUDHI (default=9600) */
138 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
139 	ZSWR15_BREAK_IE,
140 };
141 
142 
143 /****************************************************************
144  * Autoconfig
145  ****************************************************************/
146 
147 /* Definition of the driver for autoconfig. */
148 static int  zs_match(struct device *, struct cfdata *, void *);
149 static void zs_attach(struct device *, struct device *, void *);
150 static int  zs_print(void *, const char *name);
151 
152 CFATTACH_DECL(zsc, sizeof(struct zsc_softc),
153     zs_match, zs_attach, NULL, NULL);
154 
155 static int zshard(void *);
156 #if 0
157 static int zs_get_speed(struct zs_chanstate *);
158 #endif
159 
160 /*
161  * Is the zs chip present?
162  */
163 static int
164 zs_match(struct device *parent, struct cfdata *cf, void *aux)
165 {
166 	struct hb_attach_args *ha = aux;
167 	u_int addr;
168 
169 	if (strcmp(ha->ha_name, "zsc"))
170 		return 0;
171 
172 	/* XXX no default address */
173 	if (ha->ha_address == (u_int)-1)
174 		return 0;
175 
176 	addr = IIOV(ha->ha_address);
177 	/* This returns -1 on a fault (bus error). */
178 	if (badaddr((void *)addr, 1))
179 		return 0;
180 
181 	return 1;
182 }
183 
184 /*
185  * Attach a found zs.
186  */
187 static void
188 zs_attach(struct device *parent, struct device *self, void *aux)
189 {
190 	struct zsc_softc *zsc = (void *) self;
191 	struct cfdata *cf = device_cfdata(self);
192 	struct hb_attach_args *ha = aux;
193 	struct zsc_attach_args zsc_args;
194 	struct zsdevice *zs;
195 	struct zschan *zc;
196 	struct zs_chanstate *cs;
197 	int s, channel, clk;
198 
199 	zs = (void *)IIOV(ha->ha_address);
200 
201 	clk = cf->cf_flags;
202 	if (clk < 0 || clk >= NPCLK)
203 		clk = 0;
204 
205 	printf("\n");
206 
207 	/*
208 	 * Initialize software state for each channel.
209 	 */
210 	for (channel = 0; channel < 2; channel++) {
211 		zsc_args.channel = channel;
212 		cs = &zsc->zsc_cs_store[channel];
213 
214 		zsc->zsc_cs[channel] = cs;
215 		zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b;
216 
217 		if (ha->ha_vect != -1)
218 			zs_init_reg[2] = ha->ha_vect;
219 
220 		if (zc == zc_cons) {
221 			memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
222 			zs_conschan = cs;
223 			zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
224 		} else {
225 			cs->cs_reg_csr  = &zc->zc_csr;
226 			cs->cs_reg_data = &zc->zc_data;
227 			memcpy(cs->cs_creg, zs_init_reg, 16);
228 			memcpy(cs->cs_preg, zs_init_reg, 16);
229 			cs->cs_defspeed = zs_defspeed;
230 			zsc_args.hwflags = 0;
231 		}
232 
233 		zs_lock_init(cs);
234 		cs->cs_defcflag = zs_def_cflag;
235 
236 		cs->cs_channel = channel;
237 		cs->cs_private = NULL;
238 		cs->cs_ops = &zsops_null;
239 		cs->cs_brg_clk = pclk[clk] / 16;
240 
241 		/* Make these correspond to cs_defcflag (-crtscts) */
242 		cs->cs_rr0_dcd = ZSRR0_DCD;
243 		cs->cs_rr0_cts = 0;
244 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
245 		cs->cs_wr5_rts = 0;
246 
247 		/*
248 		 * Clear the master interrupt enable.
249 		 * The INTENA is common to both channels,
250 		 * so just do it on the A channel.
251 		 */
252 		if (channel == 0) {
253 			s = splhigh();
254 			zs_write_reg(cs, 9, 0);
255 			splx(s);
256 		}
257 
258 		/*
259 		 * Look for a child driver for this channel.
260 		 * The child attach will setup the hardware.
261 		 */
262 		if (!config_found(self, (void *)&zsc_args, zs_print)) {
263 			/* No sub-driver.  Just reset it. */
264 			u_char reset = (channel == 0) ?
265 				ZSWR9_A_RESET : ZSWR9_B_RESET;
266 			s = splhigh();
267 			zs_write_reg(cs,  9, reset);
268 			splx(s);
269 		}
270 	}
271 
272 	/*
273 	 * Now safe to install interrupt handlers.
274 	 */
275 	hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc);
276 	zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
277 	    (void (*)(void *))zsc_intr_soft, zsc);
278 
279 	/*
280 	 * Set the master interrupt enable and interrupt vector.
281 	 * (common to both channels, do it on A)
282 	 */
283 	cs = zsc->zsc_cs[0];
284 	s = splhigh();
285 	/* interrupt vector */
286 	zs_write_reg(cs, 2, zs_init_reg[2]);
287 	/* master interrupt control (enable) */
288 	zs_write_reg(cs, 9, zs_init_reg[9]);
289 	splx(s);
290 
291 }
292 
293 static int
294 zs_print(void *aux, const char *name)
295 {
296 	struct zsc_attach_args *args = aux;
297 
298 	if (name != NULL)
299 		aprint_normal("%s: ", name);
300 
301 	if (args->channel != -1)
302 		aprint_normal(" channel %d", args->channel);
303 
304 	return UNCONF;
305 }
306 
307 /*
308  * For news68k-port, we don't use autovectored interrupt.
309  * We do not need to look at all of the zs chips.
310  */
311 static int
312 zshard(void *arg)
313 {
314 	struct zsc_softc *zsc = arg;
315 	int rval;
316 
317 	rval = zsc_intr_hard(zsc);
318 
319 	/* We are at splzs here, so no need to lock. */
320 	if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) {
321 		softint_schedule(zsc->zsc_softintr_cookie);
322 	}
323 
324 	return rval;
325 }
326 
327 /*
328  * Compute the current baud rate given a ZS channel.
329  */
330 #if 0
331 static int
332 zs_get_speed(struct zs_chanstate *cs)
333 {
334 	int tconst;
335 
336 	tconst = zs_read_reg(cs, 12);
337 	tconst |= zs_read_reg(cs, 13) << 8;
338 	return TCONST_TO_BPS(cs->cs_brg_clk, tconst);
339 }
340 #endif
341 
342 /*
343  * MD functions for setting the baud rate and control modes.
344  */
345 int
346 zs_set_speed(struct zs_chanstate *cs, int bps)
347 {
348 	int tconst, real_bps;
349 
350 	if (bps == 0)
351 		return 0;
352 
353 #ifdef	DIAGNOSTIC
354 	if (cs->cs_brg_clk == 0)
355 		panic("zs_set_speed");
356 #endif
357 
358 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
359 	if (tconst < 0)
360 		return EINVAL;
361 
362 	/* Convert back to make sure we can do it. */
363 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
364 
365 	/* XXX - Allow some tolerance here? */
366 	if (real_bps != bps)
367 		return EINVAL;
368 
369 	cs->cs_preg[12] = tconst;
370 	cs->cs_preg[13] = tconst >> 8;
371 
372 	/* Caller will stuff the pending registers. */
373 	return 0;
374 }
375 
376 int
377 zs_set_modes(struct zs_chanstate *cs, int cflag)
378 {
379 	int s;
380 
381 	/*
382 	 * Output hardware flow control on the chip is horrendous:
383 	 * if carrier detect drops, the receiver is disabled, and if
384 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
385 	 * Therefore, NEVER set the HFC bit, and instead use the
386 	 * status interrupt to detect CTS changes.
387 	 */
388 	s = splzs();
389 	cs->cs_rr0_pps = 0;
390 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
391 		cs->cs_rr0_dcd = 0;
392 		if ((cflag & MDMBUF) == 0)
393 			cs->cs_rr0_pps = ZSRR0_DCD;
394 	} else
395 		cs->cs_rr0_dcd = ZSRR0_DCD;
396 	if ((cflag & CRTSCTS) != 0) {
397 		cs->cs_wr5_dtr = ZSWR5_DTR;
398 		cs->cs_wr5_rts = ZSWR5_RTS;
399 		cs->cs_rr0_cts = ZSRR0_CTS;
400 	} else if ((cflag & MDMBUF) != 0) {
401 		cs->cs_wr5_dtr = 0;
402 		cs->cs_wr5_rts = ZSWR5_DTR;
403 		cs->cs_rr0_cts = ZSRR0_DCD;
404 	} else {
405 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
406 		cs->cs_wr5_rts = 0;
407 		cs->cs_rr0_cts = 0;
408 	}
409 	splx(s);
410 
411 	/* Caller will stuff the pending registers. */
412 	return 0;
413 }
414 
415 
416 /*
417  * Read or write the chip with suitable delays.
418  */
419 
420 u_char
421 zs_read_reg(struct zs_chanstate *cs, u_char reg)
422 {
423 	u_char val;
424 
425 	*cs->cs_reg_csr = reg;
426 	ZS_DELAY();
427 	val = *cs->cs_reg_csr;
428 	ZS_DELAY();
429 	return val;
430 }
431 
432 void
433 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)
434 {
435 
436 	*cs->cs_reg_csr = reg;
437 	ZS_DELAY();
438 	*cs->cs_reg_csr = val;
439 	ZS_DELAY();
440 }
441 
442 u_char
443 zs_read_csr(struct zs_chanstate *cs)
444 {
445 	u_char val;
446 
447 	val = *cs->cs_reg_csr;
448 	ZS_DELAY();
449 	return val;
450 }
451 
452 void
453 zs_write_csr(struct zs_chanstate *cs, u_char val)
454 {
455 
456 	*cs->cs_reg_csr = val;
457 	ZS_DELAY();
458 }
459 
460 u_char
461 zs_read_data(struct zs_chanstate *cs)
462 {
463 	u_char val;
464 
465 	val = *cs->cs_reg_data;
466 	ZS_DELAY();
467 	return val;
468 }
469 
470 void
471 zs_write_data(struct zs_chanstate *cs, u_char val)
472 {
473 
474 	*cs->cs_reg_data = val;
475 	ZS_DELAY();
476 }
477 
478 void
479 zs_abort(struct zs_chanstate *cs)
480 {
481 
482 #ifdef DDB
483 	Debugger();
484 #endif
485 }
486 
487 /*
488  * Polled input char.
489  */
490 int
491 zs_getc(void *arg)
492 {
493 	struct zs_chanstate *cs = arg;
494 	int s, c, rr0;
495 
496 	s = splhigh();
497 	/* Wait for a character to arrive. */
498 	do {
499 		rr0 = *cs->cs_reg_csr;
500 		ZS_DELAY();
501 	} while ((rr0 & ZSRR0_RX_READY) == 0);
502 
503 	c = *cs->cs_reg_data;
504 	ZS_DELAY();
505 	splx(s);
506 
507 	return c;
508 }
509 
510 /*
511  * Polled output char.
512  */
513 void
514 zs_putc(void *arg, int c)
515 {
516 	struct zs_chanstate *cs = arg;
517 	int s, rr0;
518 
519 	s = splhigh();
520 	/* Wait for transmitter to become ready. */
521 	do {
522 		rr0 = *cs->cs_reg_csr;
523 		ZS_DELAY();
524 	} while ((rr0 & ZSRR0_TX_READY) == 0);
525 
526 	*cs->cs_reg_data = c;
527 	ZS_DELAY();
528 	splx(s);
529 }
530 
531 /*****************************************************************/
532 
533 static void zscnprobe(struct consdev *);
534 static void zscninit(struct consdev *);
535 static int  zscngetc(dev_t);
536 static void zscnputc(dev_t, int);
537 
538 struct consdev consdev_zs = {
539 	zscnprobe,
540 	zscninit,
541 	zscngetc,
542 	zscnputc,
543 	nullcnpollc,
544 	NULL,
545 	NULL,
546 	NULL,
547 	NODEV,
548 	CN_DEAD
549 };
550 
551 static void
552 zscnprobe(struct consdev *cn)
553 {
554 }
555 
556 static void
557 zscninit(struct consdev *cn)
558 {
559 	struct zs_chanstate *cs;
560 
561 	extern const struct cdevsw zstty_cdevsw;
562 	extern int tty00_is_console;
563 	extern uint32_t sccport0a;
564 
565 	cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
566 	if (tty00_is_console)
567 		cn->cn_pri = CN_REMOTE;
568 	else
569 		cn->cn_pri = CN_NORMAL;
570 
571 	zc_cons = (struct zschan *)sccport0a; /* XXX */
572 
573 	zs_conschan = cs = &zs_conschan_store;
574 
575 	/* Setup temporary chanstate. */
576 	cs->cs_reg_csr  = &zc_cons->zc_csr;
577 	cs->cs_reg_data = &zc_cons->zc_data;
578 
579 	/* Initialize the pending registers. */
580 	memcpy(cs->cs_preg, zs_init_reg, 16);
581 	cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
582 
583 	cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */
584 	cs->cs_preg[13] = 0;
585 	cs->cs_defspeed = 9600;
586 
587 	/* Clear the master interrupt enable. */
588 	zs_write_reg(cs, 9, 0);
589 
590 	/* Reset the whole SCC chip. */
591 	zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
592 
593 	/* Copy "pending" to "current" and H/W */
594 	zs_loadchannelregs(cs);
595 }
596 
597 static int
598 zscngetc(dev_t dev)
599 {
600 
601 	return zs_getc((void *)zs_conschan);
602 }
603 
604 static void
605 zscnputc(dev_t dev, int c)
606 {
607 
608 	zs_putc((void *)zs_conschan, c);
609 }
610