xref: /netbsd-src/sys/arch/news68k/dev/zs.c (revision 7fa608457b817eca6e0977b37f758ae064f3c99c) 
1 /*	$NetBSD: zs.c,v 1.27 2007/11/09 00:05:05 ad Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Gordon W. Ross.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * Zilog Z8530 Dual UART driver (machine-dependent part)
41  *
42  * Runs two serial lines per chip using slave drivers.
43  * Plain tty/async lines use the zs_async slave.
44  */
45 
46 /*
47  * news68k/dev/zs.c - based on {newsmips,x68k,mvme68k}/dev/zs.c
48  */
49 
50 #include <sys/cdefs.h>
51 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.27 2007/11/09 00:05:05 ad Exp $");
52 
53 #include "opt_ddb.h"
54 
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/conf.h>
58 #include <sys/device.h>
59 #include <sys/tty.h>
60 
61 #include <machine/cpu.h>
62 #include <machine/z8530var.h>
63 
64 #include <dev/cons.h>
65 #include <dev/ic/z8530reg.h>
66 
67 #include <news68k/dev/hbvar.h>
68 
69 #include "ioconf.h"
70 
71 int  zs_getc(void *);
72 void zs_putc(void *, int);
73 
74 /*
75  * Some warts needed by z8530tty.c -
76  * The default parity REALLY needs to be the same as the PROM uses,
77  * or you can not see messages done with printf during boot-up...
78  */
79 int zs_def_cflag = (CREAD | CS8 | HUPCL);
80 
81 /*
82  * The news68k machines use three different clocks for the ZS chips.
83  */
84 #define NPCLK	3
85 #define PCLK0	(9600 * 416)	/*  news1700: 3.9936MHz */
86 #define PCLK1	(9600 * 512)	/*  news1200: 4.9152MHz */
87 #define PCLK2	(9600 * 384)	/*  external: 3.6864MHz */
88 
89 static const u_int pclk[NPCLK] = {
90 	PCLK0,
91 	PCLK1,
92 	PCLK2,
93 };
94 
95 /*
96  * Define interrupt levels.
97  */
98 #define ZSHARD_PRI 5
99 #define ZS_IVECT 64
100 
101 #define ZS_DELAY() /* delay(2) */
102 
103 /* The layout of this is hardware-dependent (padding, order). */
104 struct zschan {
105 	volatile u_char	zc_csr;		/* ctrl,status, and indirect access */
106 	volatile u_char	zc_data;	/* data */
107 };
108 struct zsdevice {
109 	/* Yes, they are backwards. */
110 	struct	zschan zs_chan_b;
111 	struct	zschan zs_chan_a;
112 };
113 
114 /* Default speed for all channels */
115 static int zs_defspeed = 9600;
116 
117 /* console status from cninit */
118 static struct zs_chanstate zs_conschan_store;
119 static struct zs_chanstate *zs_conschan;
120 static struct zschan *zc_cons;
121 
122 static u_char zs_init_reg[16] = {
123 	0,	/* 0: CMD (reset, etc.) */
124 	0,	/* 1: No interrupts yet. */
125 	ZS_IVECT,	/* IVECT */
126 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
127 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
128 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
129 	0,	/* 6: TXSYNC/SYNCLO */
130 	0,	/* 7: RXSYNC/SYNCHI */
131 	0,	/* 8: alias for data port */
132 	ZSWR9_MASTER_IE,
133 	0,	/*10: Misc. TX/RX control bits */
134 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
135 	BPS_TO_TCONST((PCLK0/16), 9600), /*12: BAUDLO (default=9600) */
136 	0,			/*13: BAUDHI (default=9600) */
137 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
138 	ZSWR15_BREAK_IE,
139 };
140 
141 
142 /****************************************************************
143  * Autoconfig
144  ****************************************************************/
145 
146 /* Definition of the driver for autoconfig. */
147 static int  zs_match(struct device *, struct cfdata *, void *);
148 static void zs_attach(struct device *, struct device *, void *);
149 static int  zs_print(void *, const char *name);
150 
151 CFATTACH_DECL(zsc, sizeof(struct zsc_softc),
152     zs_match, zs_attach, NULL, NULL);
153 
154 static int zshard(void *);
155 #if 0
156 static int zs_get_speed(struct zs_chanstate *);
157 #endif
158 
159 /*
160  * Is the zs chip present?
161  */
162 static int
163 zs_match(struct device *parent, struct cfdata *cf, void *aux)
164 {
165 	struct hb_attach_args *ha = aux;
166 	u_int addr;
167 
168 	if (strcmp(ha->ha_name, "zsc"))
169 		return 0;
170 
171 	/* XXX no default address */
172 	if (ha->ha_address == (u_int)-1)
173 		return 0;
174 
175 	addr = IIOV(ha->ha_address);
176 	/* This returns -1 on a fault (bus error). */
177 	if (badaddr((void *)addr, 1))
178 		return 0;
179 
180 	return 1;
181 }
182 
183 /*
184  * Attach a found zs.
185  */
186 static void
187 zs_attach(struct device *parent, struct device *self, void *aux)
188 {
189 	struct zsc_softc *zsc = (void *) self;
190 	struct cfdata *cf = device_cfdata(self);
191 	struct hb_attach_args *ha = aux;
192 	struct zsc_attach_args zsc_args;
193 	struct zsdevice *zs;
194 	struct zschan *zc;
195 	struct zs_chanstate *cs;
196 	int s, channel, clk;
197 
198 	zs = (void *)IIOV(ha->ha_address);
199 
200 	clk = cf->cf_flags;
201 	if (clk < 0 || clk >= NPCLK)
202 		clk = 0;
203 
204 	printf("\n");
205 
206 	/*
207 	 * Initialize software state for each channel.
208 	 */
209 	for (channel = 0; channel < 2; channel++) {
210 		zsc_args.channel = channel;
211 		cs = &zsc->zsc_cs_store[channel];
212 
213 		zsc->zsc_cs[channel] = cs;
214 		zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b;
215 
216 		if (ha->ha_vect != -1)
217 			zs_init_reg[2] = ha->ha_vect;
218 
219 		if (zc == zc_cons) {
220 			memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
221 			zs_conschan = cs;
222 			zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
223 		} else {
224 			cs->cs_reg_csr  = &zc->zc_csr;
225 			cs->cs_reg_data = &zc->zc_data;
226 			memcpy(cs->cs_creg, zs_init_reg, 16);
227 			memcpy(cs->cs_preg, zs_init_reg, 16);
228 			cs->cs_defspeed = zs_defspeed;
229 			zsc_args.hwflags = 0;
230 		}
231 
232 		zs_lock_init(cs);
233 		cs->cs_defcflag = zs_def_cflag;
234 
235 		cs->cs_channel = channel;
236 		cs->cs_private = NULL;
237 		cs->cs_ops = &zsops_null;
238 		cs->cs_brg_clk = pclk[clk] / 16;
239 
240 		/* Make these correspond to cs_defcflag (-crtscts) */
241 		cs->cs_rr0_dcd = ZSRR0_DCD;
242 		cs->cs_rr0_cts = 0;
243 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
244 		cs->cs_wr5_rts = 0;
245 
246 		/*
247 		 * Clear the master interrupt enable.
248 		 * The INTENA is common to both channels,
249 		 * so just do it on the A channel.
250 		 */
251 		if (channel == 0) {
252 			s = splhigh();
253 			zs_write_reg(cs, 9, 0);
254 			splx(s);
255 		}
256 
257 		/*
258 		 * Look for a child driver for this channel.
259 		 * The child attach will setup the hardware.
260 		 */
261 		if (!config_found(self, (void *)&zsc_args, zs_print)) {
262 			/* No sub-driver.  Just reset it. */
263 			u_char reset = (channel == 0) ?
264 				ZSWR9_A_RESET : ZSWR9_B_RESET;
265 			s = splhigh();
266 			zs_write_reg(cs,  9, reset);
267 			splx(s);
268 		}
269 	}
270 
271 	/*
272 	 * Now safe to install interrupt handlers.
273 	 */
274 	hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc);
275 	zsc->zsc_softintr_cookie = softintr_establish(IPL_SOFTSERIAL,
276 	    (void (*)(void *))zsc_intr_soft, zsc);
277 
278 	/*
279 	 * Set the master interrupt enable and interrupt vector.
280 	 * (common to both channels, do it on A)
281 	 */
282 	cs = zsc->zsc_cs[0];
283 	s = splhigh();
284 	/* interrupt vector */
285 	zs_write_reg(cs, 2, zs_init_reg[2]);
286 	/* master interrupt control (enable) */
287 	zs_write_reg(cs, 9, zs_init_reg[9]);
288 	splx(s);
289 
290 }
291 
292 static int
293 zs_print(void *aux, const char *name)
294 {
295 	struct zsc_attach_args *args = aux;
296 
297 	if (name != NULL)
298 		aprint_normal("%s: ", name);
299 
300 	if (args->channel != -1)
301 		aprint_normal(" channel %d", args->channel);
302 
303 	return UNCONF;
304 }
305 
306 /*
307  * For news68k-port, we don't use autovectored interrupt.
308  * We do not need to look at all of the zs chips.
309  */
310 static int
311 zshard(void *arg)
312 {
313 	struct zsc_softc *zsc = arg;
314 	int rval;
315 
316 	rval = zsc_intr_hard(zsc);
317 
318 	/* We are at splzs here, so no need to lock. */
319 	if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) {
320 		softintr_schedule(zsc->zsc_softintr_cookie);
321 	}
322 
323 	return rval;
324 }
325 
326 /*
327  * Compute the current baud rate given a ZS channel.
328  */
329 #if 0
330 static int
331 zs_get_speed(struct zs_chanstate *cs)
332 {
333 	int tconst;
334 
335 	tconst = zs_read_reg(cs, 12);
336 	tconst |= zs_read_reg(cs, 13) << 8;
337 	return TCONST_TO_BPS(cs->cs_brg_clk, tconst);
338 }
339 #endif
340 
341 /*
342  * MD functions for setting the baud rate and control modes.
343  */
344 int
345 zs_set_speed(struct zs_chanstate *cs, int bps)
346 {
347 	int tconst, real_bps;
348 
349 	if (bps == 0)
350 		return 0;
351 
352 #ifdef	DIAGNOSTIC
353 	if (cs->cs_brg_clk == 0)
354 		panic("zs_set_speed");
355 #endif
356 
357 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
358 	if (tconst < 0)
359 		return EINVAL;
360 
361 	/* Convert back to make sure we can do it. */
362 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
363 
364 	/* XXX - Allow some tolerance here? */
365 	if (real_bps != bps)
366 		return EINVAL;
367 
368 	cs->cs_preg[12] = tconst;
369 	cs->cs_preg[13] = tconst >> 8;
370 
371 	/* Caller will stuff the pending registers. */
372 	return 0;
373 }
374 
375 int
376 zs_set_modes(struct zs_chanstate *cs, int cflag)
377 {
378 	int s;
379 
380 	/*
381 	 * Output hardware flow control on the chip is horrendous:
382 	 * if carrier detect drops, the receiver is disabled, and if
383 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
384 	 * Therefore, NEVER set the HFC bit, and instead use the
385 	 * status interrupt to detect CTS changes.
386 	 */
387 	s = splzs();
388 	cs->cs_rr0_pps = 0;
389 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
390 		cs->cs_rr0_dcd = 0;
391 		if ((cflag & MDMBUF) == 0)
392 			cs->cs_rr0_pps = ZSRR0_DCD;
393 	} else
394 		cs->cs_rr0_dcd = ZSRR0_DCD;
395 	if ((cflag & CRTSCTS) != 0) {
396 		cs->cs_wr5_dtr = ZSWR5_DTR;
397 		cs->cs_wr5_rts = ZSWR5_RTS;
398 		cs->cs_rr0_cts = ZSRR0_CTS;
399 	} else if ((cflag & MDMBUF) != 0) {
400 		cs->cs_wr5_dtr = 0;
401 		cs->cs_wr5_rts = ZSWR5_DTR;
402 		cs->cs_rr0_cts = ZSRR0_DCD;
403 	} else {
404 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
405 		cs->cs_wr5_rts = 0;
406 		cs->cs_rr0_cts = 0;
407 	}
408 	splx(s);
409 
410 	/* Caller will stuff the pending registers. */
411 	return 0;
412 }
413 
414 
415 /*
416  * Read or write the chip with suitable delays.
417  */
418 
419 u_char
420 zs_read_reg(struct zs_chanstate *cs, u_char reg)
421 {
422 	u_char val;
423 
424 	*cs->cs_reg_csr = reg;
425 	ZS_DELAY();
426 	val = *cs->cs_reg_csr;
427 	ZS_DELAY();
428 	return val;
429 }
430 
431 void
432 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)
433 {
434 
435 	*cs->cs_reg_csr = reg;
436 	ZS_DELAY();
437 	*cs->cs_reg_csr = val;
438 	ZS_DELAY();
439 }
440 
441 u_char
442 zs_read_csr(struct zs_chanstate *cs)
443 {
444 	u_char val;
445 
446 	val = *cs->cs_reg_csr;
447 	ZS_DELAY();
448 	return val;
449 }
450 
451 void
452 zs_write_csr(struct zs_chanstate *cs, u_char val)
453 {
454 
455 	*cs->cs_reg_csr = val;
456 	ZS_DELAY();
457 }
458 
459 u_char
460 zs_read_data(struct zs_chanstate *cs)
461 {
462 	u_char val;
463 
464 	val = *cs->cs_reg_data;
465 	ZS_DELAY();
466 	return val;
467 }
468 
469 void
470 zs_write_data(struct zs_chanstate *cs, u_char val)
471 {
472 
473 	*cs->cs_reg_data = val;
474 	ZS_DELAY();
475 }
476 
477 void
478 zs_abort(struct zs_chanstate *cs)
479 {
480 
481 #ifdef DDB
482 	Debugger();
483 #endif
484 }
485 
486 /*
487  * Polled input char.
488  */
489 int
490 zs_getc(void *arg)
491 {
492 	struct zs_chanstate *cs = arg;
493 	int s, c, rr0;
494 
495 	s = splhigh();
496 	/* Wait for a character to arrive. */
497 	do {
498 		rr0 = *cs->cs_reg_csr;
499 		ZS_DELAY();
500 	} while ((rr0 & ZSRR0_RX_READY) == 0);
501 
502 	c = *cs->cs_reg_data;
503 	ZS_DELAY();
504 	splx(s);
505 
506 	return c;
507 }
508 
509 /*
510  * Polled output char.
511  */
512 void
513 zs_putc(void *arg, int c)
514 {
515 	struct zs_chanstate *cs = arg;
516 	int s, rr0;
517 
518 	s = splhigh();
519 	/* Wait for transmitter to become ready. */
520 	do {
521 		rr0 = *cs->cs_reg_csr;
522 		ZS_DELAY();
523 	} while ((rr0 & ZSRR0_TX_READY) == 0);
524 
525 	*cs->cs_reg_data = c;
526 	ZS_DELAY();
527 	splx(s);
528 }
529 
530 /*****************************************************************/
531 
532 static void zscnprobe(struct consdev *);
533 static void zscninit(struct consdev *);
534 static int  zscngetc(dev_t);
535 static void zscnputc(dev_t, int);
536 
537 struct consdev consdev_zs = {
538 	zscnprobe,
539 	zscninit,
540 	zscngetc,
541 	zscnputc,
542 	nullcnpollc,
543 	NULL,
544 	NULL,
545 	NULL,
546 	NODEV,
547 	CN_DEAD
548 };
549 
550 static void
551 zscnprobe(struct consdev *cn)
552 {
553 }
554 
555 static void
556 zscninit(struct consdev *cn)
557 {
558 	struct zs_chanstate *cs;
559 
560 	extern const struct cdevsw zstty_cdevsw;
561 	extern int tty00_is_console;
562 	extern uint32_t sccport0a;
563 
564 	cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
565 	if (tty00_is_console)
566 		cn->cn_pri = CN_REMOTE;
567 	else
568 		cn->cn_pri = CN_NORMAL;
569 
570 	zc_cons = (struct zschan *)sccport0a; /* XXX */
571 
572 	zs_conschan = cs = &zs_conschan_store;
573 
574 	/* Setup temporary chanstate. */
575 	cs->cs_reg_csr  = &zc_cons->zc_csr;
576 	cs->cs_reg_data = &zc_cons->zc_data;
577 
578 	/* Initialize the pending registers. */
579 	memcpy(cs->cs_preg, zs_init_reg, 16);
580 	cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
581 
582 	cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */
583 	cs->cs_preg[13] = 0;
584 	cs->cs_defspeed = 9600;
585 
586 	/* Clear the master interrupt enable. */
587 	zs_write_reg(cs, 9, 0);
588 
589 	/* Reset the whole SCC chip. */
590 	zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
591 
592 	/* Copy "pending" to "current" and H/W */
593 	zs_loadchannelregs(cs);
594 }
595 
596 static int
597 zscngetc(dev_t dev)
598 {
599 
600 	return zs_getc((void *)zs_conschan);
601 }
602 
603 static void
604 zscnputc(dev_t dev, int c)
605 {
606 
607 	zs_putc((void *)zs_conschan, c);
608 }
609