1 /* $NetBSD: zs.c,v 1.34 2005/12/11 12:18:17 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * 45 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej@NetBSD.org> 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.34 2005/12/11 12:18:17 christos Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/conf.h> 54 #include <sys/device.h> 55 #include <sys/file.h> 56 #include <sys/ioctl.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> 59 #include <sys/tty.h> 60 #include <sys/time.h> 61 #include <sys/syslog.h> 62 63 #include <dev/cons.h> 64 #include <dev/ic/z8530reg.h> 65 #include <machine/z8530var.h> 66 67 #include <machine/cpu.h> 68 #include <machine/bus.h> 69 #include <machine/intr.h> 70 71 #include <mvme68k/dev/zsvar.h> 72 73 /* 74 * Some warts needed by z8530tty.c - 75 * The default parity REALLY needs to be the same as the PROM uses, 76 * or you can not see messages done with printf during boot-up... 77 */ 78 int zs_def_cflag = (CREAD | CS8 | HUPCL); 79 80 /* Flags from zscnprobe() */ 81 static int zs_hwflags[NZSC][2]; 82 83 /* Default speed for each channel */ 84 static int zs_defspeed[NZSC][2] = { 85 { 9600, /* port 1 */ 86 9600 }, /* port 2 */ 87 { 9600, /* port 3 */ 88 9600 }, /* port 4 */ 89 }; 90 91 static struct zs_chanstate zs_conschan_store; 92 static struct zs_chanstate *zs_conschan; 93 94 u_char zs_init_reg[16] = { 95 0, /* 0: CMD (reset, etc.) */ 96 0, /* 1: No interrupts yet. */ 97 0x18 + ZSHARD_PRI, /* IVECT */ 98 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 99 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 100 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 101 0, /* 6: TXSYNC/SYNCLO */ 102 0, /* 7: RXSYNC/SYNCHI */ 103 0, /* 8: alias for data port */ 104 ZSWR9_MASTER_IE, 105 0, /*10: Misc. TX/RX control bits */ 106 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 107 0, /*12: BAUDLO (default=9600) */ 108 0, /*13: BAUDHI (default=9600) */ 109 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 110 ZSWR15_BREAK_IE, 111 }; 112 113 114 /**************************************************************** 115 * Autoconfig 116 ****************************************************************/ 117 118 /* Definition of the driver for autoconfig. */ 119 static int zsc_print __P((void *, const char *name)); 120 int zs_getc __P((void *)); 121 void zs_putc __P((void *, int)); 122 123 #if 0 124 static int zs_get_speed __P((struct zs_chanstate *)); 125 #endif 126 127 extern struct cfdriver zsc_cd; 128 129 cons_decl(zsc_pcc); 130 131 132 /* 133 * Configure children of an SCC. 134 */ 135 void 136 zs_config(zsc, zs, vector, pclk) 137 struct zsc_softc *zsc; 138 struct zsdevice *zs; 139 int vector, pclk; 140 { 141 struct zsc_attach_args zsc_args; 142 volatile struct zschan *zc; 143 struct zs_chanstate *cs; 144 int zsc_unit, channel, s; 145 146 zsc_unit = zsc->zsc_dev.dv_unit; 147 printf(": Zilog 8530 SCC at vector 0x%x\n", vector); 148 149 /* 150 * Initialize software state for each channel. 151 */ 152 for (channel = 0; channel < 2; channel++) { 153 zsc_args.channel = channel; 154 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 155 cs = &zsc->zsc_cs_store[channel]; 156 zsc->zsc_cs[channel] = cs; 157 simple_lock_init(&cs->cs_lock); 158 159 /* 160 * If we're the console, copy the channel state, and 161 * adjust the console channel pointer. 162 */ 163 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 164 memcpy(cs, zs_conschan, sizeof(struct zs_chanstate)); 165 zs_conschan = cs; 166 } else { 167 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 168 cs->cs_reg_csr = zc->zc_csr; 169 cs->cs_reg_data = zc->zc_data; 170 memcpy(cs->cs_creg, zs_init_reg, 16); 171 memcpy(cs->cs_preg, zs_init_reg, 16); 172 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 173 } 174 175 cs->cs_brg_clk = pclk / 16; 176 cs->cs_creg[2] = cs->cs_preg[2] = vector; 177 zs_set_speed(cs, cs->cs_defspeed); 178 cs->cs_creg[12] = cs->cs_preg[12]; 179 cs->cs_creg[13] = cs->cs_preg[13]; 180 cs->cs_defcflag = zs_def_cflag; 181 182 /* Make these correspond to cs_defcflag (-crtscts) */ 183 cs->cs_rr0_dcd = ZSRR0_DCD; 184 cs->cs_rr0_cts = 0; 185 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 186 cs->cs_wr5_rts = 0; 187 188 cs->cs_channel = channel; 189 cs->cs_private = NULL; 190 cs->cs_ops = &zsops_null; 191 192 /* 193 * Clear the master interrupt enable. 194 * The INTENA is common to both channels, 195 * so just do it on the A channel. 196 * Write the interrupt vector while we're at it. 197 */ 198 if (channel == 0) { 199 zs_write_reg(cs, 9, 0); 200 zs_write_reg(cs, 2, vector); 201 } 202 203 /* 204 * Look for a child driver for this channel. 205 * The child attach will setup the hardware. 206 */ 207 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 208 /* No sub-driver. Just reset it. */ 209 u_char reset = (channel == 0) ? 210 ZSWR9_A_RESET : ZSWR9_B_RESET; 211 s = splzs(); 212 zs_write_reg(cs, 9, reset); 213 splx(s); 214 } 215 } 216 217 /* 218 * Allocate a software interrupt cookie. 219 */ 220 zsc->zsc_softintr_cookie = softintr_establish(IPL_SOFTSERIAL, 221 (void (*)(void *)) zsc_intr_soft, zsc); 222 #ifdef DEBUG 223 assert(zsc->zsc_softintr_cookie); 224 #endif 225 } 226 227 static int 228 zsc_print(aux, name) 229 void *aux; 230 const char *name; 231 { 232 struct zsc_attach_args *args = aux; 233 234 if (name != NULL) 235 aprint_normal("%s: ", name); 236 237 if (args->channel != -1) 238 aprint_normal(" channel %d", args->channel); 239 240 return UNCONF; 241 } 242 243 #if defined(MVME162) || defined(MVME172) 244 /* 245 * Our ZS chips each have their own interrupt vector. 246 */ 247 int 248 zshard_unshared(arg) 249 void *arg; 250 { 251 struct zsc_softc *zsc = arg; 252 int rval; 253 254 rval = zsc_intr_hard(zsc); 255 256 if (rval) { 257 if ((zsc->zsc_cs[0]->cs_softreq) || 258 (zsc->zsc_cs[1]->cs_softreq)) 259 softintr_schedule(zsc->zsc_softintr_cookie); 260 zsc->zsc_evcnt.ev_count++; 261 } 262 263 return (rval); 264 } 265 #endif 266 267 #ifdef MVME147 268 /* 269 * Our ZS chips all share a common, PCC-vectored interrupt, 270 * so we have to look at all of them on each interrupt. 271 */ 272 int 273 zshard_shared(arg) 274 void *arg; 275 { 276 struct zsc_softc *zsc; 277 int unit, rval; 278 279 rval = 0; 280 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 281 zsc = zsc_cd.cd_devs[unit]; 282 if (zsc != NULL && zsc_intr_hard(zsc)) { 283 if ((zsc->zsc_cs[0]->cs_softreq) || 284 (zsc->zsc_cs[1]->cs_softreq)) 285 softintr_schedule(zsc->zsc_softintr_cookie); 286 zsc->zsc_evcnt.ev_count++; 287 rval++; 288 } 289 } 290 return (rval); 291 } 292 #endif 293 294 295 #if 0 296 /* 297 * Compute the current baud rate given a ZSCC channel. 298 */ 299 static int 300 zs_get_speed(cs) 301 struct zs_chanstate *cs; 302 { 303 int tconst; 304 305 tconst = zs_read_reg(cs, 12); 306 tconst |= zs_read_reg(cs, 13) << 8; 307 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 308 } 309 #endif 310 311 /* 312 * MD functions for setting the baud rate and control modes. 313 */ 314 int 315 zs_set_speed(cs, bps) 316 struct zs_chanstate *cs; 317 int bps; /* bits per second */ 318 { 319 int tconst, real_bps; 320 321 if (bps == 0) 322 return (0); 323 324 #ifdef DIAGNOSTIC 325 if (cs->cs_brg_clk == 0) 326 panic("zs_set_speed"); 327 #endif 328 329 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 330 if (tconst < 0) 331 return (EINVAL); 332 333 /* Convert back to make sure we can do it. */ 334 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 335 336 /* Allow 2% tolerance WRT the required bps */ 337 if (((abs(real_bps - bps) * 1000) / bps) > 20) 338 return (EINVAL); 339 340 cs->cs_preg[12] = tconst; 341 cs->cs_preg[13] = tconst >> 8; 342 343 /* Caller will stuff the pending registers. */ 344 return (0); 345 } 346 347 int 348 zs_set_modes(cs, cflag) 349 struct zs_chanstate *cs; 350 int cflag; /* bits per second */ 351 { 352 int s; 353 354 /* 355 * Output hardware flow control on the chip is horrendous: 356 * if carrier detect drops, the receiver is disabled, and if 357 * CTS drops, the transmitter is stoped IN MID CHARACTER! 358 * Therefore, NEVER set the HFC bit, and instead use the 359 * status interrupt to detect CTS changes. 360 */ 361 s = splzs(); 362 cs->cs_rr0_pps = 0; 363 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 364 cs->cs_rr0_dcd = 0; 365 if ((cflag & MDMBUF) == 0) 366 cs->cs_rr0_pps = ZSRR0_DCD; 367 } else 368 cs->cs_rr0_dcd = ZSRR0_DCD; 369 if ((cflag & CRTSCTS) != 0) { 370 cs->cs_wr5_dtr = ZSWR5_DTR; 371 cs->cs_wr5_rts = ZSWR5_RTS; 372 cs->cs_rr0_cts = ZSRR0_CTS; 373 } else if ((cflag & MDMBUF) != 0) { 374 cs->cs_wr5_dtr = 0; 375 cs->cs_wr5_rts = ZSWR5_DTR; 376 cs->cs_rr0_cts = ZSRR0_DCD; 377 } else { 378 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 379 cs->cs_wr5_rts = 0; 380 cs->cs_rr0_cts = 0; 381 } 382 splx(s); 383 384 /* Caller will stuff the pending registers. */ 385 return (0); 386 } 387 388 389 /* 390 * Read or write the chip with suitable delays. 391 */ 392 393 u_char 394 zs_read_reg(cs, reg) 395 struct zs_chanstate *cs; 396 u_char reg; 397 { 398 u_char val; 399 400 *cs->cs_reg_csr = reg; 401 ZS_DELAY(); 402 val = *cs->cs_reg_csr; 403 ZS_DELAY(); 404 return val; 405 } 406 407 void 408 zs_write_reg(cs, reg, val) 409 struct zs_chanstate *cs; 410 u_char reg, val; 411 { 412 *cs->cs_reg_csr = reg; 413 ZS_DELAY(); 414 *cs->cs_reg_csr = val; 415 ZS_DELAY(); 416 } 417 418 u_char zs_read_csr(cs) 419 struct zs_chanstate *cs; 420 { 421 u_char val; 422 423 val = *cs->cs_reg_csr; 424 ZS_DELAY(); 425 return val; 426 } 427 428 void zs_write_csr(cs, val) 429 struct zs_chanstate *cs; 430 u_char val; 431 { 432 *cs->cs_reg_csr = val; 433 ZS_DELAY(); 434 } 435 436 u_char zs_read_data(cs) 437 struct zs_chanstate *cs; 438 { 439 u_char val; 440 441 val = *cs->cs_reg_data; 442 ZS_DELAY(); 443 return val; 444 } 445 446 void zs_write_data(cs, val) 447 struct zs_chanstate *cs; 448 u_char val; 449 { 450 *cs->cs_reg_data = val; 451 ZS_DELAY(); 452 } 453 454 /**************************************************************** 455 * Console support functions (MVME specific!) 456 ****************************************************************/ 457 458 /* 459 * Polled input char. 460 */ 461 int 462 zs_getc(arg) 463 void *arg; 464 { 465 struct zs_chanstate *cs = arg; 466 int s, c, rr0, stat; 467 468 s = splhigh(); 469 top: 470 /* Wait for a character to arrive. */ 471 do { 472 rr0 = *cs->cs_reg_csr; 473 ZS_DELAY(); 474 } while ((rr0 & ZSRR0_RX_READY) == 0); 475 476 /* Read error register. */ 477 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 478 if (stat) { 479 zs_write_csr(cs, ZSM_RESET_ERR); 480 goto top; 481 } 482 483 /* Read character. */ 484 c = *cs->cs_reg_data; 485 ZS_DELAY(); 486 splx(s); 487 488 return (c); 489 } 490 491 /* 492 * Polled output char. 493 */ 494 void 495 zs_putc(arg, c) 496 void *arg; 497 int c; 498 { 499 struct zs_chanstate *cs = arg; 500 int s, rr0; 501 502 s = splhigh(); 503 /* Wait for transmitter to become ready. */ 504 do { 505 rr0 = *cs->cs_reg_csr; 506 ZS_DELAY(); 507 } while ((rr0 & ZSRR0_TX_READY) == 0); 508 509 *cs->cs_reg_data = c; 510 ZS_DELAY(); 511 splx(s); 512 } 513 514 /* 515 * Common parts of console init. 516 */ 517 void 518 zs_cnconfig(zsc_unit, channel, zs, pclk) 519 int zsc_unit, channel; 520 struct zsdevice *zs; 521 int pclk; 522 { 523 struct zs_chanstate *cs; 524 struct zschan *zc; 525 526 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 527 528 /* 529 * Pointer to channel state. Later, the console channel 530 * state is copied into the softc, and the console channel 531 * pointer adjusted to point to the new copy. 532 */ 533 zs_conschan = cs = &zs_conschan_store; 534 zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE; 535 536 /* Setup temporary chanstate. */ 537 cs->cs_brg_clk = pclk / 16; 538 cs->cs_reg_csr = zc->zc_csr; 539 cs->cs_reg_data = zc->zc_data; 540 541 /* Initialize the pending registers. */ 542 memcpy(cs->cs_preg, zs_init_reg, 16); 543 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 544 545 #if 0 546 /* XXX: Preserve BAUD rate from boot loader. */ 547 /* XXX: Also, why reset the chip here? -gwr */ 548 cs->cs_defspeed = zs_get_speed(cs); 549 #else 550 cs->cs_defspeed = 9600; /* XXX */ 551 #endif 552 zs_set_speed(cs, cs->cs_defspeed); 553 cs->cs_creg[12] = cs->cs_preg[12]; 554 cs->cs_creg[13] = cs->cs_preg[13]; 555 556 /* Clear the master interrupt enable. */ 557 zs_write_reg(cs, 9, 0); 558 559 /* Reset the whole SCC chip. */ 560 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 561 562 /* Copy "pending" to "current" and H/W. */ 563 zs_loadchannelregs(cs); 564 } 565 566 /* 567 * Polled console input putchar. 568 */ 569 int 570 zsc_pcccngetc(dev) 571 dev_t dev; 572 { 573 struct zs_chanstate *cs = zs_conschan; 574 int c; 575 576 c = zs_getc(cs); 577 return (c); 578 } 579 580 /* 581 * Polled console output putchar. 582 */ 583 void 584 zsc_pcccnputc(dev, c) 585 dev_t dev; 586 int c; 587 { 588 struct zs_chanstate *cs = zs_conschan; 589 590 zs_putc(cs, c); 591 } 592 593 /* 594 * Handle user request to enter kernel debugger. 595 */ 596 void 597 zs_abort(cs) 598 struct zs_chanstate *cs; 599 { 600 int rr0; 601 602 /* Wait for end of break to avoid PROM abort. */ 603 /* XXX - Limit the wait? */ 604 do { 605 rr0 = *cs->cs_reg_csr; 606 ZS_DELAY(); 607 } while (rr0 & ZSRR0_BREAK); 608 609 mvme68k_abort("SERIAL LINE ABORT"); 610 } 611