1 /* $NetBSD: lpt_pccreg.h,v 1.3 2000/03/18 22:33:03 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * MVME147 Parallel Port Register Definitions 41 */ 42 #ifndef _MVME68K_LPT_PCCREG_H 43 #define _MVME68K_LPT_PCCREG_H 44 45 /* 46 * The mvme147's PCC chip has two status/control registers for the 47 * printer port: 48 * 49 * PCCREG_PRNT_INTR_CTRL Printer interrupt control register 50 * 0 - 2 Interrupt Level 51 * 3 Interrupt Enable 52 * 4 ACK Polarity. If set, falling edge of ACK generates 53 * the interrupt. If clear, rising edge of ACK generates 54 * the interrupt. 55 * 5 Indicates an ACK interrupt in progress. Cleared by 56 * writing a one, or disabling lpt interrupts. 57 * 6 Indicates a FAULT interrupt. Set on falling edge 58 * of printer's fault signal. Cleared by writing a one. 59 * 7 Printer Interrupt in progress. Basically just the 60 * logical OR of bits 5 and 6. 61 */ 62 #define LPI_ENABLE (1 << 3) 63 #define LPI_ACKPOL (1 << 4) 64 #define LPI_ACKINT (1 << 5) 65 #define LPI_FAULTINT (1 << 6) 66 #define LPI_INTERRUPT (1 << 7) 67 68 69 /* 70 * PCCREG_PRNT_CONTROL Printer Control Register 71 * 0 Selects auto or manual strobe mode. When low, strobe 72 * is automatically generated by a write to the printer 73 * data register. When set, strobe must be generated 74 * manually using bit 2 of this register. 75 * 1 Controls strobe timing in auto mode. When low, strobe 76 * time is 6.4uS. When high, strobe time is 1.6uS. 77 * 2 Controls strobe in manual mode. 78 * 3 Control Input Prime signal. When set, Input Prime 79 * is activated. 80 * 81 * Two other registers which are not addressed via the global PCC structure, 82 * live at 0xfffe2800. This address is virtualised and passed to the driver 83 * in the pcc_attach_args structure: 84 */ 85 #define LPC_STROBE_MODE (1 << 0) 86 #define LPC_FAST_STROBE (1 << 1) 87 #define LPC_STROBE (1 << 2) 88 #define LPC_INPUT_PRIME (1 << 3) 89 90 #define lpt_control_read() pcc_reg_read(sys_pcc, PCCREG_PRNT_CONTROL) 91 #define lpt_control_write(v) pcc_reg_write(sys_pcc, PCCREG_PRNT_CONTROL, v) 92 93 /* 94 * Data and status registers appear at the same offset. 95 * Write to access the data register. Read to access the status register. 96 */ 97 #define LPREG_DATA 0x00 /* Write only data register */ 98 #define LPREG_STATUS 0x00 /* Read only status register */ 99 100 #define LPREG_SIZE 0x1 101 102 /* 103 * Access macros for the status register 104 */ 105 #define LPS_BUSY (1 << 3) 106 #define LPS_PAPER_EMPTY (1 << 4) 107 #define LPS_SELECT (1 << 5) 108 #define LPS_FAULT (1 << 6) 109 #define LPS_ACK (1 << 7) 110 111 #define lpt_data_write(sc,v) \ 112 bus_space_write_1((sc)->sc_bust, (sc)->sc_bush, LPREG_DATA, (v)) 113 #define lpt_status_read(sc) \ 114 bus_space_read_1((sc)->sc_bust, (sc)->sc_bush, LPREG_STATUS) 115 116 #endif /* _MVME68K_LPT_PCCREG_H */ 117