1 /* $NetBSD: zs.c,v 1.28 2021/09/11 20:28:04 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Zilog Z8530 Dual UART driver (machine-dependent part) 34 * 35 * Runs two serial lines per chip using slave drivers. 36 * Plain tty/async lines use the zs_async slave. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.28 2021/09/11 20:28:04 andvar Exp $"); 41 42 #include "opt_ddb.h" 43 #include "opt_kgdb.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/conf.h> 48 #include <sys/device.h> 49 #include <sys/file.h> 50 #include <sys/ioctl.h> 51 #include <sys/kernel.h> 52 #include <sys/proc.h> 53 #include <sys/tty.h> 54 #include <sys/time.h> 55 #include <sys/syslog.h> 56 #include <sys/cpu.h> 57 #include <sys/intr.h> 58 59 #include <machine/mainboard.h> 60 #include <machine/autoconf.h> 61 #include <machine/prom.h> 62 #include <machine/z8530var.h> 63 64 #include <dev/cons.h> 65 #include <dev/ic/z8530reg.h> 66 67 #include "ioconf.h" 68 #include "zsc.h" /* NZSC */ 69 #define NZS NZSC 70 71 /* Make life easier for the initialized arrays here. */ 72 #if NZS < 2 73 #undef NZS 74 #define NZS 2 75 #endif 76 77 /* 78 * Some warts needed by z8530tty.c - 79 * The default parity REALLY needs to be the same as the PROM uses, 80 * or you can not see messages done with printf during boot-up... 81 */ 82 int zs_def_cflag = (CREAD | CS8 | HUPCL); 83 84 85 #define PCLK 10000000 /* PCLK pin input clock rate */ 86 87 #ifndef ZS_DEFSPEED 88 #define ZS_DEFSPEED 9600 89 #endif 90 91 /* 92 * Define interrupt levels. 93 */ 94 #define ZSHARD_PRI 64 95 96 /* Register recovery time is 3.5 to 4 PCLK Cycles */ 97 #define ZS_RECOVERY 1 /* 1us = 10 PCLK Cycles */ 98 #define ZS_DELAY() delay(ZS_RECOVERY) 99 100 /* The layout of this is hardware-dependent (padding, order). */ 101 struct zschan { 102 uint8_t pad1[3]; 103 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */ 104 uint8_t pad2[3]; 105 volatile uint8_t zc_data; /* data */ 106 }; 107 struct zsdevice { 108 /* Yes, they are backwards. */ 109 struct zschan zs_chan_b; 110 struct zschan zs_chan_a; 111 }; 112 113 /* Return the byte offset of element within a structure */ 114 #define OFFSET(struct_def, el) ((size_t)&((struct_def *)0)->el) 115 116 #define ZS_CHAN_A OFFSET(struct zsdevice, zs_chan_a) 117 #define ZS_CHAN_B OFFSET(struct zsdevice, zs_chan_b) 118 #define ZS_REG_CSR OFFSET(struct zschan, zc_csr) 119 #define ZS_REG_DATA OFFSET(struct zschan, zc_data) 120 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B}; 121 122 /* Flags from cninit() */ 123 static int zs_hwflags[NZS][2]; 124 125 /* Default speed for all channels */ 126 static int zs_defspeed = ZS_DEFSPEED; 127 static volatile int zssoftpending; 128 129 static uint8_t zs_init_reg[16] = { 130 0, /* 0: CMD (reset, etc.) */ 131 0, /* 1: No interrupts yet. */ 132 ZSHARD_PRI, /* 2: IVECT */ 133 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 134 ZSWR4_CLK_X16 | ZSWR4_ONESB, 135 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 136 0, /* 6: TXSYNC/SYNCLO */ 137 0, /* 7: RXSYNC/SYNCHI */ 138 0, /* 8: alias for data port */ 139 ZSWR9_MASTER_IE, 140 0, /*10: Misc. TX/RX control bits */ 141 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA, 142 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */ 143 0, /*13: BAUDHI (default=9600) */ 144 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 145 ZSWR15_BREAK_IE, 146 }; 147 148 149 /**************************************************************** 150 * Autoconfig 151 ****************************************************************/ 152 153 /* Definition of the driver for autoconfig. */ 154 static int zs_match(device_t, cfdata_t, void *); 155 static void zs_attach(device_t, device_t, void *); 156 static int zs_print(void *, const char *name); 157 158 CFATTACH_DECL_NEW(zsc, sizeof(struct zsc_softc), 159 zs_match, zs_attach, NULL, NULL); 160 161 static int zshard(void *); 162 void zssoft(void *); 163 static int zs_get_speed(struct zs_chanstate *); 164 struct zschan *zs_get_chan_addr(int zs_unit, int channel); 165 int zs_getc(void *); 166 void zs_putc(void *, int); 167 168 /* 169 * Is the zs chip present? 170 */ 171 static int 172 zs_match(device_t parent, cfdata_t cf, void *aux) 173 { 174 struct confargs *ca = aux; 175 void *va; 176 177 if (strcmp(ca->ca_name, "zsc")) 178 return 0; 179 180 va = (void *)cf->cf_addr; 181 182 /* This returns -1 on a fault (bus error). */ 183 if (badaddr(va, 1)) 184 return 0; 185 return 1; 186 } 187 188 /* 189 * Attach a found zs. 190 * 191 * Match slave number to zs unit number, so that misconfiguration will 192 * not set up the keyboard as ttya, etc. 193 */ 194 static void 195 zs_attach(device_t parent, device_t self, void *aux) 196 { 197 struct zsc_softc *zsc = device_private(self); 198 struct confargs *ca = aux; 199 struct zsc_attach_args zsc_args; 200 struct zs_chanstate *cs; 201 struct zs_channel *ch; 202 int zs_unit, channel, s; 203 204 zsc->zsc_dev = self; 205 zsc->zsc_bustag = ca->ca_bustag; 206 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 207 sizeof(struct zsdevice), 208 BUS_SPACE_MAP_LINEAR, 209 &zsc->zsc_base) != 0) { 210 aprint_error(": cannot map registers\n"); 211 return; 212 } 213 214 zs_unit = device_unit(self); 215 aprint_normal("\n"); 216 217 /* 218 * Initialize software state for each channel. 219 */ 220 for (channel = 0; channel < 2; channel++) { 221 zsc_args.channel = channel; 222 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 223 ch = &zsc->zsc_cs_store[channel]; 224 cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch; 225 226 zs_lock_init(cs); 227 cs->cs_reg_csr = NULL; 228 cs->cs_reg_data = NULL; 229 cs->cs_channel = channel; 230 cs->cs_private = NULL; 231 cs->cs_ops = &zsops_null; 232 cs->cs_brg_clk = PCLK / 16; 233 234 if (bus_space_subregion(ca->ca_bustag, zsc->zsc_base, 235 zs_chan_offset[channel], 236 sizeof(struct zschan), 237 &ch->cs_regs) != 0) { 238 aprint_error_dev(self, ": cannot map regs\n"); 239 return; 240 } 241 ch->cs_bustag = ca->ca_bustag; 242 243 memcpy(cs->cs_creg, zs_init_reg, 16); 244 memcpy(cs->cs_preg, zs_init_reg, 16); 245 246 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 247 cs->cs_defspeed = zs_get_speed(cs); 248 else 249 cs->cs_defspeed = zs_defspeed; 250 cs->cs_defcflag = zs_def_cflag; 251 252 /* Make these correspond to cs_defcflag (-crtscts) */ 253 cs->cs_rr0_dcd = ZSRR0_DCD; 254 cs->cs_rr0_cts = 0; 255 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 256 cs->cs_wr5_rts = 0; 257 258 /* 259 * Clear the master interrupt enable. 260 * The INTENA is common to both channels, 261 * so just do it on the A channel. 262 */ 263 if (channel == 0) { 264 zs_write_reg(cs, 9, 0); 265 } 266 /* 267 * Look for a child driver for this channel. 268 * The child attach will setup the hardware. 269 */ 270 if (!config_found(self, (void *)&zsc_args, zs_print, 271 CFARGS_NONE)) { 272 /* No sub-driver. Just reset it. */ 273 uint8_t reset = (channel == 0) ? 274 ZSWR9_A_RESET : ZSWR9_B_RESET; 275 276 s = splhigh(); 277 zs_write_reg(cs, 9, reset); 278 splx(s); 279 } 280 } 281 282 283 zsc->sc_si = softint_establish(SOFTINT_SERIAL, zssoft, zsc); 284 bus_intr_establish(zsc->zsc_bustag, SYS_INTR_SCC0, 0, 0, zshard, NULL); 285 286 evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL, 287 device_xname(self), "intr"); 288 289 /* 290 * Set the master interrupt enable and interrupt vector. 291 * (common to both channels, do it on A) 292 */ 293 cs = zsc->zsc_cs[0]; 294 s = splhigh(); 295 /* interrupt vector */ 296 zs_write_reg(cs, 2, zs_init_reg[2]); 297 /* master interrupt control (enable) */ 298 zs_write_reg(cs, 9, zs_init_reg[9]); 299 splx(s); 300 } 301 302 static int 303 zs_print(void *aux, const char *name) 304 { 305 struct zsc_attach_args *args = aux; 306 307 if (name != NULL) 308 aprint_normal("%s: ", name); 309 310 if (args->channel != -1) 311 aprint_normal(" channel %d", args->channel); 312 313 return UNCONF; 314 } 315 316 /* 317 * Our ZS chips all share a common, autovectored interrupt, 318 * so we have to look at all of them on each interrupt. 319 */ 320 static int 321 zshard(void *arg) 322 { 323 struct zsc_softc *zsc; 324 int unit, rval, softreq; 325 326 rval = 0; 327 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 328 zsc = device_lookup_private(&zsc_cd, unit); 329 if (zsc == NULL) 330 continue; 331 rval |= zsc_intr_hard(zsc); 332 softreq = zsc->zsc_cs[0]->cs_softreq; 333 softreq |= zsc->zsc_cs[1]->cs_softreq; 334 if (softreq && (zssoftpending == 0)) { 335 zssoftpending = 1; 336 softint_schedule(zsc->sc_si); 337 } 338 zsc->zs_intrcnt.ev_count++; 339 } 340 return rval; 341 } 342 343 /* 344 * Similar scheme as for zshard (look at all of them) 345 */ 346 void 347 zssoft(void *arg) 348 { 349 struct zsc_softc *zsc; 350 int s, unit; 351 352 /* This is not the only ISR on this IPL. */ 353 if (zssoftpending == 0) 354 return; 355 356 /* 357 * The soft intr. bit will be set by zshard only if 358 * the variable zssoftpending is zero. The order of 359 * these next two statements prevents our clearing 360 * the soft intr bit just after zshard has set it. 361 */ 362 /*isr_soft_clear(ZSSOFT_PRI);*/ 363 zssoftpending = 0; 364 365 /* Make sure we call the tty layer at spltty. */ 366 s = spltty(); 367 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 368 zsc = device_lookup_private(&zsc_cd, unit); 369 if (zsc == NULL) 370 continue; 371 (void)zsc_intr_soft(zsc); 372 } 373 splx(s); 374 return; 375 } 376 377 378 /* 379 * Compute the current baud rate given a ZS channel. 380 */ 381 static int 382 zs_get_speed(struct zs_chanstate *cs) 383 { 384 int tconst; 385 386 tconst = zs_read_reg(cs, 12); 387 tconst |= zs_read_reg(cs, 13) << 8; 388 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 389 } 390 391 /* 392 * MD functions for setting the baud rate and control modes. 393 */ 394 int 395 zs_set_speed(struct zs_chanstate *cs, int bps) 396 { 397 int tconst; 398 #if 0 399 int real_bps; 400 #endif 401 402 #if 0 403 while (!(zs_read_csr(cs) & ZSRR0_TX_READY)) 404 {/*nop*/} 405 #endif 406 /* Wait for transmit buffer to empty */ 407 if (bps == 0) { 408 return (0); 409 } 410 411 #ifdef DIAGNOSTIC 412 if (cs->cs_brg_clk == 0) 413 panic("zs_set_speed"); 414 #endif 415 416 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 417 if (tconst < 0) 418 return (EINVAL); 419 420 #if 0 421 /* Convert back to make sure we can do it. */ 422 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 423 424 /* XXX - Allow some tolerance here? */ 425 if (real_bps != bps) 426 return (EINVAL); 427 #endif 428 429 cs->cs_preg[12] = tconst; 430 cs->cs_preg[13] = tconst >> 8; 431 432 /* Caller will stuff the pending registers. */ 433 return (0); 434 } 435 436 int 437 zs_set_modes(struct zs_chanstate *cs, int cflag) 438 { 439 int s; 440 441 /* 442 * Output hardware flow control on the chip is horrendous: 443 * if carrier detect drops, the receiver is disabled, and if 444 * CTS drops, the transmitter is stopped IN MID CHARACTER! 445 * Therefore, NEVER set the HFC bit, and instead use the 446 * status interrupt to detect CTS changes. 447 */ 448 s = splzs(); 449 cs->cs_rr0_pps = 0; 450 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 451 cs->cs_rr0_dcd = 0; 452 if ((cflag & MDMBUF) == 0) 453 cs->cs_rr0_pps = ZSRR0_DCD; 454 } else 455 cs->cs_rr0_dcd = ZSRR0_DCD; 456 if ((cflag & CRTSCTS) != 0) { 457 cs->cs_wr5_dtr = ZSWR5_DTR; 458 cs->cs_wr5_rts = ZSWR5_RTS; 459 cs->cs_rr0_cts = ZSRR0_CTS; 460 } else if ((cflag & MDMBUF) != 0) { 461 cs->cs_wr5_dtr = 0; 462 cs->cs_wr5_rts = ZSWR5_DTR; 463 cs->cs_rr0_cts = ZSRR0_DCD; 464 } else { 465 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 466 cs->cs_wr5_rts = 0; 467 cs->cs_rr0_cts = 0; 468 } 469 splx(s); 470 471 /* Caller will stuff the pending registers. */ 472 return (0); 473 } 474 475 476 /* 477 * Read or write the chip with suitable delays. 478 */ 479 480 uint8_t 481 zs_read_reg(struct zs_chanstate *cs, uint8_t reg) 482 { 483 uint8_t val; 484 struct zs_channel *zsc = (struct zs_channel *)cs; 485 486 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 487 ZS_DELAY(); 488 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 489 ZS_DELAY(); 490 return val; 491 } 492 493 void 494 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val) 495 { 496 struct zs_channel *zsc = (struct zs_channel *)cs; 497 498 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 499 ZS_DELAY(); 500 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 501 ZS_DELAY(); 502 } 503 504 uint8_t 505 zs_read_csr(struct zs_chanstate *cs) 506 { 507 struct zs_channel *zsc = (struct zs_channel *)cs; 508 uint8_t val; 509 510 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 511 ZS_DELAY(); 512 return val; 513 } 514 515 void 516 zs_write_csr(struct zs_chanstate *cs, uint8_t val) 517 { 518 struct zs_channel *zsc = (struct zs_channel *)cs; 519 520 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 521 ZS_DELAY(); 522 } 523 524 uint8_t 525 zs_read_data(struct zs_chanstate *cs) 526 { 527 struct zs_channel *zsc = (struct zs_channel *)cs; 528 uint8_t val; 529 530 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA); 531 ZS_DELAY(); 532 return val; 533 } 534 535 void 536 zs_write_data(struct zs_chanstate *cs, uint8_t val) 537 { 538 struct zs_channel *zsc = (struct zs_channel *)cs; 539 540 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val); 541 ZS_DELAY(); 542 } 543 544 void 545 zs_abort(struct zs_chanstate *cs) 546 { 547 548 #if defined(KGDB) 549 zskgdb(cs); 550 #elif defined(DDB) 551 Debugger(); 552 #endif 553 } 554 555 556 /*********************************************************/ 557 /* Polled character I/O functions for console and KGDB */ 558 /*********************************************************/ 559 560 struct zschan * 561 zs_get_chan_addr(int zs_unit, int channel) 562 { 563 struct zsdevice *addr; 564 struct zschan *zc; 565 566 if (zs_unit >= NZS) 567 return NULL; 568 569 addr = (struct zsdevice *) ZS0_ADDR; 570 571 if (channel == 0) { 572 zc = &addr->zs_chan_a; 573 } else { 574 zc = &addr->zs_chan_b; 575 } 576 return (zc); 577 } 578 579 int 580 zs_getc(void *arg) 581 { 582 volatile struct zschan *zc = arg; 583 int s, c; 584 uint8_t rr0; 585 586 s = splhigh(); 587 /* Wait for a character to arrive. */ 588 do { 589 rr0 = zc->zc_csr; 590 ZS_DELAY(); 591 } while ((rr0 & ZSRR0_RX_READY) == 0); 592 593 c = zc->zc_data; 594 ZS_DELAY(); 595 splx(s); 596 597 return (c); 598 } 599 600 /* 601 * Polled output char. 602 */ 603 void 604 zs_putc(void *arg, int c) 605 { 606 volatile struct zschan *zc = arg; 607 int s; 608 uint8_t rr0; 609 610 s = splhigh(); 611 /* Wait for transmitter to become ready. */ 612 do { 613 rr0 = zc->zc_csr; 614 ZS_DELAY(); 615 } while ((rr0 & ZSRR0_TX_READY) == 0); 616 617 zc->zc_data = c; 618 wbflush(); 619 ZS_DELAY(); 620 splx(s); 621 } 622 623 /***************************************************************/ 624 625 static void zscnprobe(struct consdev *); 626 static void zscninit(struct consdev *); 627 static int zscngetc(dev_t); 628 static void zscnputc(dev_t, int); 629 static void zscnpollc(dev_t, int); 630 631 static int cons_port; 632 633 struct consdev consdev_zs = { 634 zscnprobe, 635 zscninit, 636 zscngetc, 637 zscnputc, 638 zscnpollc 639 }; 640 641 void 642 zscnprobe(struct consdev *cn) 643 { 644 } 645 646 void 647 zscninit(struct consdev *cn) 648 { 649 extern const struct cdevsw zstty_cdevsw; 650 651 cons_port = prom_getconsole(); 652 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), cons_port); 653 cn->cn_pri = CN_REMOTE; 654 zs_hwflags[0][cons_port] = ZS_HWFLAG_CONSOLE; 655 } 656 657 int 658 zscngetc(dev_t dev) 659 { 660 struct zschan *zs; 661 662 zs = zs_get_chan_addr(0, cons_port); 663 return zs_getc(zs); 664 } 665 666 void 667 zscnputc(dev_t dev, int c) 668 { 669 struct zschan *zs; 670 671 zs = zs_get_chan_addr(0, cons_port); 672 zs_putc(zs, c); 673 } 674 675 void 676 zscnpollc(dev_t dev, int on) 677 { 678 } 679