xref: /netbsd-src/sys/arch/mipsco/obio/zs.c (revision b7b7574d3bf8eeb51a1fa3977b59142ec6434a55) 
1 /*	$NetBSD: zs.c,v 1.25 2014/06/08 10:40:52 he Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Gordon W. Ross and Wayne Knowles
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 /*
33  * Zilog Z8530 Dual UART driver (machine-dependent part)
34  *
35  * Runs two serial lines per chip using slave drivers.
36  * Plain tty/async lines use the zs_async slave.
37  */
38 
39 #include <sys/cdefs.h>
40 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.25 2014/06/08 10:40:52 he Exp $");
41 
42 #include "opt_ddb.h"
43 #include "opt_kgdb.h"
44 
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/conf.h>
48 #include <sys/device.h>
49 #include <sys/file.h>
50 #include <sys/ioctl.h>
51 #include <sys/kernel.h>
52 #include <sys/proc.h>
53 #include <sys/tty.h>
54 #include <sys/time.h>
55 #include <sys/syslog.h>
56 #include <sys/cpu.h>
57 #include <sys/intr.h>
58 
59 #include <machine/mainboard.h>
60 #include <machine/autoconf.h>
61 #include <machine/prom.h>
62 #include <machine/z8530var.h>
63 
64 #include <dev/cons.h>
65 #include <dev/ic/z8530reg.h>
66 
67 #include "ioconf.h"
68 #include "zsc.h"	/* NZSC */
69 #define NZS NZSC
70 
71 /* Make life easier for the initialized arrays here. */
72 #if NZS < 2
73 #undef  NZS
74 #define NZS 2
75 #endif
76 
77 /*
78  * Some warts needed by z8530tty.c -
79  * The default parity REALLY needs to be the same as the PROM uses,
80  * or you can not see messages done with printf during boot-up...
81  */
82 int zs_def_cflag = (CREAD | CS8 | HUPCL);
83 
84 
85 #define PCLK		10000000	/* PCLK pin input clock rate */
86 
87 #ifndef ZS_DEFSPEED
88 #define ZS_DEFSPEED	9600
89 #endif
90 
91 /*
92  * Define interrupt levels.
93  */
94 #define ZSHARD_PRI 64
95 
96 /* Register recovery time is 3.5 to 4 PCLK Cycles */
97 #define ZS_RECOVERY	1		/* 1us = 10 PCLK Cycles */
98 #define ZS_DELAY()	delay(ZS_RECOVERY)
99 
100 /* The layout of this is hardware-dependent (padding, order). */
101 struct zschan {
102 	uint8_t pad1[3];
103 	volatile uint8_t zc_csr;	/* ctrl,status, and indirect access */
104 	uint8_t   pad2[3];
105 	volatile uint8_t zc_data;	/* data */
106 };
107 struct zsdevice {
108 	/* Yes, they are backwards. */
109 	struct	zschan zs_chan_b;
110 	struct	zschan zs_chan_a;
111 };
112 
113 /* Return the byte offset of element within a structure */
114 #define OFFSET(struct_def, el)		((size_t)&((struct_def *)0)->el)
115 
116 #define ZS_CHAN_A	OFFSET(struct zsdevice, zs_chan_a)
117 #define ZS_CHAN_B	OFFSET(struct zsdevice, zs_chan_b)
118 #define ZS_REG_CSR	OFFSET(struct zschan, zc_csr)
119 #define ZS_REG_DATA	OFFSET(struct zschan, zc_data)
120 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B};
121 
122 /* Flags from cninit() */
123 static int zs_hwflags[NZS][2];
124 
125 /* Default speed for all channels */
126 static int zs_defspeed = ZS_DEFSPEED;
127 static volatile int zssoftpending;
128 
129 static uint8_t zs_init_reg[16] = {
130 	0,				/* 0: CMD (reset, etc.) */
131 	0,				/* 1: No interrupts yet. */
132 	ZSHARD_PRI,			/* 2: IVECT */
133 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
134 	ZSWR4_CLK_X16 | ZSWR4_ONESB,
135 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
136 	0,				/* 6: TXSYNC/SYNCLO */
137 	0,				/* 7: RXSYNC/SYNCHI */
138 	0,				/* 8: alias for data port */
139 	ZSWR9_MASTER_IE,
140 	0,				/*10: Misc. TX/RX control bits */
141 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA,
142 	BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */
143 	0,				/*13: BAUDHI (default=9600) */
144 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
145 	ZSWR15_BREAK_IE,
146 };
147 
148 
149 /****************************************************************
150  * Autoconfig
151  ****************************************************************/
152 
153 /* Definition of the driver for autoconfig. */
154 static int	zs_match(device_t, cfdata_t, void *);
155 static void	zs_attach(device_t, device_t, void *);
156 static int	zs_print(void *, const char *name);
157 
158 CFATTACH_DECL_NEW(zsc, sizeof(struct zsc_softc),
159     zs_match, zs_attach, NULL, NULL);
160 
161 static int	zshard(void *);
162 void		zssoft(void *);
163 static int	zs_get_speed(struct zs_chanstate *);
164 struct		zschan *zs_get_chan_addr(int zs_unit, int channel);
165 int		zs_getc(void *);
166 void		zs_putc(void *, int);
167 
168 /*
169  * Is the zs chip present?
170  */
171 static int
172 zs_match(device_t parent, cfdata_t cf, void *aux)
173 {
174 	struct confargs *ca = aux;
175 	void *va;
176 
177 	if (strcmp(ca->ca_name, "zsc"))
178 		return 0;
179 
180 	va = (void *)cf->cf_addr;
181 
182 	/* This returns -1 on a fault (bus error). */
183 	if (badaddr(va, 1))
184 		return 0;
185 	return 1;
186 }
187 
188 /*
189  * Attach a found zs.
190  *
191  * Match slave number to zs unit number, so that misconfiguration will
192  * not set up the keyboard as ttya, etc.
193  */
194 static void
195 zs_attach(device_t parent, device_t self, void *aux)
196 {
197 	struct zsc_softc *zsc = device_private(self);
198 	struct confargs *ca = aux;
199 	struct zsc_attach_args zsc_args;
200 	struct zs_chanstate *cs;
201 	struct zs_channel *ch;
202 	int    zs_unit, channel, s;
203 
204 	zsc->zsc_dev = self;
205 	zsc->zsc_bustag = ca->ca_bustag;
206 	if (bus_space_map(ca->ca_bustag, ca->ca_addr,
207 			  sizeof(struct zsdevice),
208 			  BUS_SPACE_MAP_LINEAR,
209 			  &zsc->zsc_base) != 0) {
210 		aprint_error(": cannot map registers\n");
211 		return;
212 	}
213 
214 	zs_unit = device_unit(self);
215 	aprint_normal("\n");
216 
217 	/*
218 	 * Initialize software state for each channel.
219 	 */
220 	for (channel = 0; channel < 2; channel++) {
221 		zsc_args.channel = channel;
222 		zsc_args.hwflags = zs_hwflags[zs_unit][channel];
223 		ch = &zsc->zsc_cs_store[channel];
224 		cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch;
225 
226 		zs_lock_init(cs);
227 		cs->cs_reg_csr = NULL;
228 		cs->cs_reg_data = NULL;
229 		cs->cs_channel = channel;
230 		cs->cs_private = NULL;
231 		cs->cs_ops = &zsops_null;
232 		cs->cs_brg_clk = PCLK / 16;
233 
234 		if (bus_space_subregion(ca->ca_bustag, zsc->zsc_base,
235 					zs_chan_offset[channel],
236 					sizeof(struct zschan),
237 					&ch->cs_regs) != 0) {
238 			aprint_error_dev(self, ": cannot map regs\n");
239 			return;
240 		}
241 		ch->cs_bustag = ca->ca_bustag;
242 
243 		memcpy(cs->cs_creg, zs_init_reg, 16);
244 		memcpy(cs->cs_preg, zs_init_reg, 16);
245 
246 		if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
247 			cs->cs_defspeed = zs_get_speed(cs);
248 		else
249 			cs->cs_defspeed = zs_defspeed;
250 		cs->cs_defcflag = zs_def_cflag;
251 
252 		/* Make these correspond to cs_defcflag (-crtscts) */
253 		cs->cs_rr0_dcd = ZSRR0_DCD;
254 		cs->cs_rr0_cts = 0;
255 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
256 		cs->cs_wr5_rts = 0;
257 
258 		/*
259 		 * Clear the master interrupt enable.
260 		 * The INTENA is common to both channels,
261 		 * so just do it on the A channel.
262 		 */
263 		if (channel == 0) {
264 			zs_write_reg(cs, 9, 0);
265 		}
266 		/*
267 		 * Look for a child driver for this channel.
268 		 * The child attach will setup the hardware.
269 		 */
270 		if (!config_found(self, (void *)&zsc_args, zs_print)) {
271 			/* No sub-driver.  Just reset it. */
272 			uint8_t reset = (channel == 0) ?
273 				ZSWR9_A_RESET : ZSWR9_B_RESET;
274 
275 			s = splhigh();
276  			zs_write_reg(cs,  9, reset);
277 			splx(s);
278 		}
279 	}
280 
281 
282 	zsc->sc_si = softint_establish(SOFTINT_SERIAL, zssoft, zsc);
283 	bus_intr_establish(zsc->zsc_bustag, SYS_INTR_SCC0, 0, 0, zshard, NULL);
284 
285 	evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL,
286 			     device_xname(self), "intr");
287 
288 	/*
289 	 * Set the master interrupt enable and interrupt vector.
290 	 * (common to both channels, do it on A)
291 	 */
292 	cs = zsc->zsc_cs[0];
293 	s = splhigh();
294 	/* interrupt vector */
295 	zs_write_reg(cs, 2, zs_init_reg[2]);
296 	/* master interrupt control (enable) */
297 	zs_write_reg(cs, 9, zs_init_reg[9]);
298 	splx(s);
299 }
300 
301 static int
302 zs_print(void *aux, const char *name)
303 {
304 	struct zsc_attach_args *args = aux;
305 
306 	if (name != NULL)
307 		aprint_normal("%s: ", name);
308 
309 	if (args->channel != -1)
310 		aprint_normal(" channel %d", args->channel);
311 
312 	return UNCONF;
313 }
314 
315 /*
316  * Our ZS chips all share a common, autovectored interrupt,
317  * so we have to look at all of them on each interrupt.
318  */
319 static int
320 zshard(void *arg)
321 {
322 	struct zsc_softc *zsc;
323 	int unit, rval, softreq;
324 
325 	rval = 0;
326 	for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
327 		zsc = device_lookup_private(&zsc_cd, unit);
328 		if (zsc == NULL)
329 			continue;
330 		rval |= zsc_intr_hard(zsc);
331 		softreq = zsc->zsc_cs[0]->cs_softreq;
332 		softreq |= zsc->zsc_cs[1]->cs_softreq;
333 		if (softreq && (zssoftpending == 0)) {
334 		    zssoftpending = 1;
335 		    softint_schedule(zsc->sc_si);
336 		}
337 		zsc->zs_intrcnt.ev_count++;
338 	}
339 	return rval;
340 }
341 
342 /*
343  * Similar scheme as for zshard (look at all of them)
344  */
345 void
346 zssoft(void *arg)
347 {
348 	struct zsc_softc *zsc;
349 	int s, unit;
350 
351 	/* This is not the only ISR on this IPL. */
352 	if (zssoftpending == 0)
353 		return;
354 
355 	/*
356 	 * The soft intr. bit will be set by zshard only if
357 	 * the variable zssoftpending is zero.  The order of
358 	 * these next two statements prevents our clearing
359 	 * the soft intr bit just after zshard has set it.
360 	 */
361 	/*isr_soft_clear(ZSSOFT_PRI);*/
362 	zssoftpending = 0;
363 
364 	/* Make sure we call the tty layer at spltty. */
365 	s = spltty();
366 	for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
367 		zsc = device_lookup_private(&zsc_cd, unit);
368 		if (zsc == NULL)
369 			continue;
370 		(void)zsc_intr_soft(zsc);
371 	}
372 	splx(s);
373 	return;
374 }
375 
376 
377 /*
378  * Compute the current baud rate given a ZS channel.
379  */
380 static int
381 zs_get_speed(struct zs_chanstate *cs)
382 {
383 	int tconst;
384 
385 	tconst = zs_read_reg(cs, 12);
386 	tconst |= zs_read_reg(cs, 13) << 8;
387 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
388 }
389 
390 /*
391  * MD functions for setting the baud rate and control modes.
392  */
393 int
394 zs_set_speed(struct zs_chanstate *cs, int bps)
395 {
396 	int tconst;
397 #if 0
398 	int real_bps;
399 #endif
400 
401 #if 0
402 	while (!(zs_read_csr(cs) & ZSRR0_TX_READY))
403 	        {/*nop*/}
404 #endif
405 	/* Wait for transmit buffer to empty */
406 	if (bps == 0) {
407 		return (0);
408 	}
409 
410 #ifdef	DIAGNOSTIC
411 	if (cs->cs_brg_clk == 0)
412 		panic("zs_set_speed");
413 #endif
414 
415 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
416 	if (tconst < 0)
417 		return (EINVAL);
418 
419 #if 0
420 	/* Convert back to make sure we can do it. */
421 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
422 
423 	/* XXX - Allow some tolerance here? */
424 	if (real_bps != bps)
425 		return (EINVAL);
426 #endif
427 
428 	cs->cs_preg[12] = tconst;
429 	cs->cs_preg[13] = tconst >> 8;
430 
431 	/* Caller will stuff the pending registers. */
432 	return (0);
433 }
434 
435 int
436 zs_set_modes(struct zs_chanstate *cs, int cflag)
437 {
438 	int s;
439 
440 	/*
441 	 * Output hardware flow control on the chip is horrendous:
442 	 * if carrier detect drops, the receiver is disabled, and if
443 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
444 	 * Therefore, NEVER set the HFC bit, and instead use the
445 	 * status interrupt to detect CTS changes.
446 	 */
447 	s = splzs();
448 	cs->cs_rr0_pps = 0;
449 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
450 		cs->cs_rr0_dcd = 0;
451 		if ((cflag & MDMBUF) == 0)
452 			cs->cs_rr0_pps = ZSRR0_DCD;
453 	} else
454 		cs->cs_rr0_dcd = ZSRR0_DCD;
455 	if ((cflag & CRTSCTS) != 0) {
456 		cs->cs_wr5_dtr = ZSWR5_DTR;
457 		cs->cs_wr5_rts = ZSWR5_RTS;
458 		cs->cs_rr0_cts = ZSRR0_CTS;
459 	} else if ((cflag & MDMBUF) != 0) {
460 		cs->cs_wr5_dtr = 0;
461 		cs->cs_wr5_rts = ZSWR5_DTR;
462 		cs->cs_rr0_cts = ZSRR0_DCD;
463 	} else {
464 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
465 		cs->cs_wr5_rts = 0;
466 		cs->cs_rr0_cts = 0;
467 	}
468 	splx(s);
469 
470 	/* Caller will stuff the pending registers. */
471 	return (0);
472 }
473 
474 
475 /*
476  * Read or write the chip with suitable delays.
477  */
478 
479 uint8_t
480 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
481 {
482 	uint8_t val;
483 	struct zs_channel *zsc = (struct zs_channel *)cs;
484 
485 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg);
486 	ZS_DELAY();
487 	val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR);
488 	ZS_DELAY();
489 	return val;
490 }
491 
492 void
493 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
494 {
495 	struct zs_channel *zsc = (struct zs_channel *)cs;
496 
497 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg);
498 	ZS_DELAY();
499 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val);
500 	ZS_DELAY();
501 }
502 
503 uint8_t
504 zs_read_csr(struct zs_chanstate *cs)
505 {
506 	struct zs_channel *zsc = (struct zs_channel *)cs;
507 	uint8_t val;
508 
509 	val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR);
510 	ZS_DELAY();
511 	return val;
512 }
513 
514 void
515 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
516 {
517 	struct zs_channel *zsc = (struct zs_channel *)cs;
518 
519 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val);
520 	ZS_DELAY();
521 }
522 
523 uint8_t
524 zs_read_data(struct zs_chanstate *cs)
525 {
526 	struct zs_channel *zsc = (struct zs_channel *)cs;
527 	uint8_t val;
528 
529 	val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA);
530 	ZS_DELAY();
531 	return val;
532 }
533 
534 void
535 zs_write_data(struct zs_chanstate *cs, uint8_t val)
536 {
537 	struct zs_channel *zsc = (struct zs_channel *)cs;
538 
539 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val);
540 	ZS_DELAY();
541 }
542 
543 void
544 zs_abort(struct zs_chanstate *cs)
545 {
546 
547 #if defined(KGDB)
548 	zskgdb(cs);
549 #elif defined(DDB)
550 	Debugger();
551 #endif
552 }
553 
554 
555 /*********************************************************/
556 /*  Polled character I/O functions for console and KGDB  */
557 /*********************************************************/
558 
559 struct zschan *
560 zs_get_chan_addr(int zs_unit, int channel)
561 {
562         struct zsdevice *addr;
563         struct zschan *zc;
564 
565         if (zs_unit >= NZS)
566                 return NULL;
567 
568         addr = (struct zsdevice *) ZS0_ADDR;
569 
570         if (channel == 0) {
571                 zc = &addr->zs_chan_a;
572         } else {
573                 zc = &addr->zs_chan_b;
574         }
575         return (zc);
576 }
577 
578 int
579 zs_getc(void *arg)
580 {
581 	volatile struct zschan *zc = arg;
582 	int s, c;
583 	uint8_t rr0;
584 
585 	s = splhigh();
586 	/* Wait for a character to arrive. */
587 	do {
588 		rr0 = zc->zc_csr;
589 		ZS_DELAY();
590 	} while ((rr0 & ZSRR0_RX_READY) == 0);
591 
592 	c = zc->zc_data;
593 	ZS_DELAY();
594 	splx(s);
595 
596 	return (c);
597 }
598 
599 /*
600  * Polled output char.
601  */
602 void
603 zs_putc(void *arg, int c)
604 {
605 	volatile struct zschan *zc = arg;
606 	int s;
607 	uint8_t rr0;
608 
609 	s = splhigh();
610 	/* Wait for transmitter to become ready. */
611 	do {
612 		rr0 = zc->zc_csr;
613 		ZS_DELAY();
614 	} while ((rr0 & ZSRR0_TX_READY) == 0);
615 
616 	zc->zc_data = c;
617 	wbflush();
618 	ZS_DELAY();
619 	splx(s);
620 }
621 
622 /***************************************************************/
623 
624 static void zscnprobe(struct consdev *);
625 static void zscninit(struct consdev *);
626 static int  zscngetc(dev_t);
627 static void zscnputc(dev_t, int);
628 static void zscnpollc(dev_t, int);
629 
630 static int  cons_port;
631 
632 struct consdev consdev_zs = {
633 	zscnprobe,
634 	zscninit,
635 	zscngetc,
636 	zscnputc,
637 	zscnpollc
638 };
639 
640 void
641 zscnprobe(struct consdev *cn)
642 {
643 }
644 
645 void
646 zscninit(struct consdev *cn)
647 {
648 	extern const struct cdevsw zstty_cdevsw;
649 
650 	cons_port = prom_getconsole();
651 	cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), cons_port);
652 	cn->cn_pri = CN_REMOTE;
653 	zs_hwflags[0][cons_port] = ZS_HWFLAG_CONSOLE;
654 }
655 
656 int
657 zscngetc(dev_t dev)
658 {
659 	struct zschan *zs;
660 
661 	zs = zs_get_chan_addr(0, cons_port);
662 	return zs_getc(zs);
663 }
664 
665 void
666 zscnputc(dev_t dev, int c)
667 {
668 	struct zschan *zs;
669 
670 	zs = zs_get_chan_addr(0, cons_port);
671 	zs_putc(zs, c);
672 }
673 
674 void
675 zscnpollc(dev_t dev, int on)
676 {
677 }
678