1 /* $NetBSD: zs.c,v 1.18 2005/12/11 12:18:13 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.18 2005/12/11 12:18:13 christos Exp $"); 48 49 #include "opt_ddb.h" 50 #include "opt_kgdb.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/file.h> 57 #include <sys/ioctl.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> 60 #include <sys/tty.h> 61 #include <sys/time.h> 62 #include <sys/syslog.h> 63 64 #include <machine/cpu.h> 65 #include <machine/mainboard.h> 66 #include <machine/autoconf.h> 67 #include <machine/prom.h> 68 #include <machine/z8530var.h> 69 70 #include <dev/cons.h> 71 #include <dev/ic/z8530reg.h> 72 73 #include "zsc.h" /* NZSC */ 74 #define NZS NZSC 75 76 /* Make life easier for the initialized arrays here. */ 77 #if NZS < 2 78 #undef NZS 79 #define NZS 2 80 #endif 81 82 /* 83 * Some warts needed by z8530tty.c - 84 * The default parity REALLY needs to be the same as the PROM uses, 85 * or you can not see messages done with printf during boot-up... 86 */ 87 int zs_def_cflag = (CREAD | CS8 | HUPCL); 88 89 90 #define PCLK 10000000 /* PCLK pin input clock rate */ 91 92 #ifndef ZS_DEFSPEED 93 #define ZS_DEFSPEED 9600 94 #endif 95 96 /* 97 * Define interrupt levels. 98 */ 99 #define ZSHARD_PRI 64 100 101 /* Register recovery time is 3.5 to 4 PCLK Cycles */ 102 #define ZS_RECOVERY 1 /* 1us = 10 PCLK Cycles */ 103 #define ZS_DELAY() delay(ZS_RECOVERY) 104 105 /* The layout of this is hardware-dependent (padding, order). */ 106 struct zschan { 107 u_char pad1[3]; 108 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 109 u_char pad2[3]; 110 volatile u_char zc_data; /* data */ 111 }; 112 struct zsdevice { 113 /* Yes, they are backwards. */ 114 struct zschan zs_chan_b; 115 struct zschan zs_chan_a; 116 }; 117 118 /* Return the byte offset of element within a structure */ 119 #define OFFSET(struct_def, el) ((size_t)&((struct_def *)0)->el) 120 121 #define ZS_CHAN_A OFFSET(struct zsdevice, zs_chan_a) 122 #define ZS_CHAN_B OFFSET(struct zsdevice, zs_chan_b) 123 #define ZS_REG_CSR OFFSET(struct zschan, zc_csr) 124 #define ZS_REG_DATA OFFSET(struct zschan, zc_data) 125 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B}; 126 127 /* Flags from cninit() */ 128 static int zs_hwflags[NZS][2]; 129 130 /* Default speed for all channels */ 131 static int zs_defspeed = ZS_DEFSPEED; 132 static volatile int zssoftpending; 133 134 static u_char zs_init_reg[16] = { 135 0, /* 0: CMD (reset, etc.) */ 136 0, /* 1: No interrupts yet. */ 137 ZSHARD_PRI, /* 2: IVECT */ 138 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 139 ZSWR4_CLK_X16 | ZSWR4_ONESB, 140 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 141 0, /* 6: TXSYNC/SYNCLO */ 142 0, /* 7: RXSYNC/SYNCHI */ 143 0, /* 8: alias for data port */ 144 ZSWR9_MASTER_IE, 145 0, /*10: Misc. TX/RX control bits */ 146 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA, 147 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */ 148 0, /*13: BAUDHI (default=9600) */ 149 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 150 ZSWR15_BREAK_IE, 151 }; 152 153 154 /**************************************************************** 155 * Autoconfig 156 ****************************************************************/ 157 158 /* Definition of the driver for autoconfig. */ 159 static int zs_match __P((struct device *, struct cfdata *, void *)); 160 static void zs_attach __P((struct device *, struct device *, void *)); 161 static int zs_print __P((void *, const char *name)); 162 163 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 164 zs_match, zs_attach, NULL, NULL); 165 166 extern struct cfdriver zsc_cd; 167 168 static int zshard __P((void *)); 169 void zssoft __P((void *)); 170 static int zs_get_speed __P((struct zs_chanstate *)); 171 struct zschan *zs_get_chan_addr (int zs_unit, int channel); 172 int zs_getc __P((void *)); 173 void zs_putc __P((void *, int)); 174 175 /* 176 * Is the zs chip present? 177 */ 178 static int 179 zs_match(parent, cf, aux) 180 struct device *parent; 181 struct cfdata *cf; 182 void *aux; 183 { 184 struct confargs *ca = aux; 185 void *va; 186 187 if (strcmp(ca->ca_name, "zsc")) 188 return 0; 189 190 va = (void *)cf->cf_addr; 191 192 /* This returns -1 on a fault (bus error). */ 193 if (badaddr(va, 1)) 194 return 0; 195 return 1; 196 } 197 198 /* 199 * Attach a found zs. 200 * 201 * Match slave number to zs unit number, so that misconfiguration will 202 * not set up the keyboard as ttya, etc. 203 */ 204 static void 205 zs_attach(parent, self, aux) 206 struct device *parent; 207 struct device *self; 208 void *aux; 209 { 210 struct zsc_softc *zsc = (void *) self; 211 struct confargs *ca = aux; 212 struct zsc_attach_args zsc_args; 213 struct zs_chanstate *cs; 214 struct zs_channel *ch; 215 int zs_unit, channel, s; 216 217 zsc->zsc_bustag = ca->ca_bustag; 218 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 219 sizeof(struct zsdevice), 220 BUS_SPACE_MAP_LINEAR, 221 &zsc->zsc_base) != 0) { 222 printf(": cannot map registers\n"); 223 return; 224 } 225 226 zs_unit = zsc->zsc_dev.dv_unit; 227 printf("\n"); 228 229 /* 230 * Initialize software state for each channel. 231 */ 232 for (channel = 0; channel < 2; channel++) { 233 zsc_args.channel = channel; 234 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 235 ch = &zsc->zsc_cs_store[channel]; 236 cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch; 237 238 simple_lock_init(&cs->cs_lock); 239 cs->cs_reg_csr = NULL; 240 cs->cs_reg_data = NULL; 241 cs->cs_channel = channel; 242 cs->cs_private = NULL; 243 cs->cs_ops = &zsops_null; 244 cs->cs_brg_clk = PCLK / 16; 245 246 if (bus_space_subregion(ca->ca_bustag, zsc->zsc_base, 247 zs_chan_offset[channel], 248 sizeof(struct zschan), 249 &ch->cs_regs) != 0) { 250 printf(": cannot map regs\n"); 251 return; 252 } 253 ch->cs_bustag = ca->ca_bustag; 254 255 memcpy(cs->cs_creg, zs_init_reg, 16); 256 memcpy(cs->cs_preg, zs_init_reg, 16); 257 258 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 259 cs->cs_defspeed = zs_get_speed(cs); 260 else 261 cs->cs_defspeed = zs_defspeed; 262 cs->cs_defcflag = zs_def_cflag; 263 264 /* Make these correspond to cs_defcflag (-crtscts) */ 265 cs->cs_rr0_dcd = ZSRR0_DCD; 266 cs->cs_rr0_cts = 0; 267 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 268 cs->cs_wr5_rts = 0; 269 270 /* 271 * Clear the master interrupt enable. 272 * The INTENA is common to both channels, 273 * so just do it on the A channel. 274 */ 275 if (channel == 0) { 276 zs_write_reg(cs, 9, 0); 277 } 278 /* 279 * Look for a child driver for this channel. 280 * The child attach will setup the hardware. 281 */ 282 if (!config_found(self, (void *)&zsc_args, zs_print)) { 283 /* No sub-driver. Just reset it. */ 284 u_char reset = (channel == 0) ? 285 ZSWR9_A_RESET : ZSWR9_B_RESET; 286 287 s = splhigh(); 288 zs_write_reg(cs, 9, reset); 289 splx(s); 290 } 291 } 292 293 294 zsc->sc_si = softintr_establish(IPL_SOFTSERIAL, zssoft, zsc); 295 bus_intr_establish(zsc->zsc_bustag, SYS_INTR_SCC0, 0, 0, zshard, NULL); 296 297 evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL, 298 self->dv_xname, "intr"); 299 300 /* 301 * Set the master interrupt enable and interrupt vector. 302 * (common to both channels, do it on A) 303 */ 304 cs = zsc->zsc_cs[0]; 305 s = splhigh(); 306 /* interrupt vector */ 307 zs_write_reg(cs, 2, zs_init_reg[2]); 308 /* master interrupt control (enable) */ 309 zs_write_reg(cs, 9, zs_init_reg[9]); 310 splx(s); 311 } 312 313 static int 314 zs_print(aux, name) 315 void *aux; 316 const char *name; 317 { 318 struct zsc_attach_args *args = aux; 319 320 if (name != NULL) 321 aprint_normal("%s: ", name); 322 323 if (args->channel != -1) 324 aprint_normal(" channel %d", args->channel); 325 326 return UNCONF; 327 } 328 329 /* 330 * Our ZS chips all share a common, autovectored interrupt, 331 * so we have to look at all of them on each interrupt. 332 */ 333 static int 334 zshard(arg) 335 void *arg; 336 { 337 register struct zsc_softc *zsc; 338 register int unit, rval, softreq; 339 340 rval = 0; 341 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 342 zsc = zsc_cd.cd_devs[unit]; 343 if (zsc == NULL) 344 continue; 345 rval |= zsc_intr_hard(zsc); 346 softreq = zsc->zsc_cs[0]->cs_softreq; 347 softreq |= zsc->zsc_cs[1]->cs_softreq; 348 if (softreq && (zssoftpending == 0)) { 349 zssoftpending = 1; 350 softintr_schedule(zsc->sc_si); 351 } 352 zsc->zs_intrcnt.ev_count++; 353 } 354 return rval; 355 } 356 357 /* 358 * Similar scheme as for zshard (look at all of them) 359 */ 360 void 361 zssoft(arg) 362 void *arg; 363 { 364 register struct zsc_softc *zsc; 365 register int s, unit; 366 367 /* This is not the only ISR on this IPL. */ 368 if (zssoftpending == 0) 369 return; 370 371 /* 372 * The soft intr. bit will be set by zshard only if 373 * the variable zssoftpending is zero. The order of 374 * these next two statements prevents our clearing 375 * the soft intr bit just after zshard has set it. 376 */ 377 /*isr_soft_clear(ZSSOFT_PRI);*/ 378 zssoftpending = 0; 379 380 /* Make sure we call the tty layer at spltty. */ 381 s = spltty(); 382 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 383 zsc = zsc_cd.cd_devs[unit]; 384 if (zsc == NULL) 385 continue; 386 (void) zsc_intr_soft(zsc); 387 } 388 splx(s); 389 return; 390 } 391 392 393 /* 394 * Compute the current baud rate given a ZS channel. 395 */ 396 static int 397 zs_get_speed(cs) 398 struct zs_chanstate *cs; 399 { 400 int tconst; 401 402 tconst = zs_read_reg(cs, 12); 403 tconst |= zs_read_reg(cs, 13) << 8; 404 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 405 } 406 407 /* 408 * MD functions for setting the baud rate and control modes. 409 */ 410 int 411 zs_set_speed(cs, bps) 412 struct zs_chanstate *cs; 413 int bps; /* bits per second */ 414 { 415 int tconst, real_bps; 416 417 #if 0 418 while (!(zs_read_csr(cs) & ZSRR0_TX_READY)) 419 {/*nop*/} 420 #endif 421 /* Wait for transmit buffer to empty */ 422 if (bps == 0) { 423 return (0); 424 } 425 426 #ifdef DIAGNOSTIC 427 if (cs->cs_brg_clk == 0) 428 panic("zs_set_speed"); 429 #endif 430 431 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 432 if (tconst < 0) 433 return (EINVAL); 434 435 /* Convert back to make sure we can do it. */ 436 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 437 438 /* XXX - Allow some tolerance here? */ 439 #if 0 440 if (real_bps != bps) 441 return (EINVAL); 442 #endif 443 444 cs->cs_preg[12] = tconst; 445 cs->cs_preg[13] = tconst >> 8; 446 447 /* Caller will stuff the pending registers. */ 448 return (0); 449 } 450 451 int 452 zs_set_modes(cs, cflag) 453 struct zs_chanstate *cs; 454 int cflag; /* bits per second */ 455 { 456 int s; 457 458 /* 459 * Output hardware flow control on the chip is horrendous: 460 * if carrier detect drops, the receiver is disabled, and if 461 * CTS drops, the transmitter is stoped IN MID CHARACTER! 462 * Therefore, NEVER set the HFC bit, and instead use the 463 * status interrupt to detect CTS changes. 464 */ 465 s = splzs(); 466 cs->cs_rr0_pps = 0; 467 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 468 cs->cs_rr0_dcd = 0; 469 if ((cflag & MDMBUF) == 0) 470 cs->cs_rr0_pps = ZSRR0_DCD; 471 } else 472 cs->cs_rr0_dcd = ZSRR0_DCD; 473 if ((cflag & CRTSCTS) != 0) { 474 cs->cs_wr5_dtr = ZSWR5_DTR; 475 cs->cs_wr5_rts = ZSWR5_RTS; 476 cs->cs_rr0_cts = ZSRR0_CTS; 477 } else if ((cflag & MDMBUF) != 0) { 478 cs->cs_wr5_dtr = 0; 479 cs->cs_wr5_rts = ZSWR5_DTR; 480 cs->cs_rr0_cts = ZSRR0_DCD; 481 } else { 482 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 483 cs->cs_wr5_rts = 0; 484 cs->cs_rr0_cts = 0; 485 } 486 splx(s); 487 488 /* Caller will stuff the pending registers. */ 489 return (0); 490 } 491 492 493 /* 494 * Read or write the chip with suitable delays. 495 */ 496 497 u_char 498 zs_read_reg(cs, reg) 499 struct zs_chanstate *cs; 500 u_char reg; 501 { 502 u_char val; 503 struct zs_channel *zsc = (struct zs_channel *)cs; 504 505 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 506 ZS_DELAY(); 507 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 508 ZS_DELAY(); 509 return val; 510 } 511 512 void 513 zs_write_reg(cs, reg, val) 514 struct zs_chanstate *cs; 515 u_char reg, val; 516 { 517 struct zs_channel *zsc = (struct zs_channel *)cs; 518 519 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 520 ZS_DELAY(); 521 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 522 ZS_DELAY(); 523 } 524 525 u_char zs_read_csr(cs) 526 struct zs_chanstate *cs; 527 { 528 struct zs_channel *zsc = (struct zs_channel *)cs; 529 register u_char val; 530 531 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 532 ZS_DELAY(); 533 return val; 534 } 535 536 void zs_write_csr(cs, val) 537 struct zs_chanstate *cs; 538 u_char val; 539 { 540 struct zs_channel *zsc = (struct zs_channel *)cs; 541 542 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 543 ZS_DELAY(); 544 } 545 546 u_char zs_read_data(cs) 547 struct zs_chanstate *cs; 548 { 549 struct zs_channel *zsc = (struct zs_channel *)cs; 550 register u_char val; 551 552 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA); 553 ZS_DELAY(); 554 return val; 555 } 556 557 void zs_write_data(cs, val) 558 struct zs_chanstate *cs; 559 u_char val; 560 { 561 struct zs_channel *zsc = (struct zs_channel *)cs; 562 563 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val); 564 ZS_DELAY(); 565 } 566 567 void 568 zs_abort(cs) 569 struct zs_chanstate *cs; 570 { 571 #if defined(KGDB) 572 zskgdb(cs); 573 #elif defined(DDB) 574 Debugger(); 575 #endif 576 } 577 578 579 /*********************************************************/ 580 /* Polled character I/O functions for console and KGDB */ 581 /*********************************************************/ 582 583 struct zschan * 584 zs_get_chan_addr(zs_unit, channel) 585 int zs_unit, channel; 586 { 587 struct zsdevice *addr; 588 struct zschan *zc; 589 590 if (zs_unit >= NZS) 591 return NULL; 592 593 addr = (struct zsdevice *) ZS0_ADDR; 594 595 if (channel == 0) { 596 zc = &addr->zs_chan_a; 597 } else { 598 zc = &addr->zs_chan_b; 599 } 600 return (zc); 601 } 602 603 int 604 zs_getc(arg) 605 void *arg; 606 { 607 register volatile struct zschan *zc = arg; 608 register int s, c, rr0; 609 610 s = splhigh(); 611 /* Wait for a character to arrive. */ 612 do { 613 rr0 = zc->zc_csr; 614 ZS_DELAY(); 615 } while ((rr0 & ZSRR0_RX_READY) == 0); 616 617 c = zc->zc_data; 618 ZS_DELAY(); 619 splx(s); 620 621 return (c); 622 } 623 624 /* 625 * Polled output char. 626 */ 627 void 628 zs_putc(arg, c) 629 void *arg; 630 int c; 631 { 632 register volatile struct zschan *zc = arg; 633 register int s, rr0; 634 635 s = splhigh(); 636 /* Wait for transmitter to become ready. */ 637 do { 638 rr0 = zc->zc_csr; 639 ZS_DELAY(); 640 } while ((rr0 & ZSRR0_TX_READY) == 0); 641 642 zc->zc_data = c; 643 wbflush(); 644 ZS_DELAY(); 645 splx(s); 646 } 647 648 /***************************************************************/ 649 650 static void zscnprobe __P((struct consdev *)); 651 static void zscninit __P((struct consdev *)); 652 static int zscngetc __P((dev_t)); 653 static void zscnputc __P((dev_t, int)); 654 static void zscnpollc __P((dev_t, int)); 655 656 static int cons_port; 657 658 struct consdev consdev_zs = { 659 zscnprobe, 660 zscninit, 661 zscngetc, 662 zscnputc, 663 zscnpollc 664 }; 665 666 void 667 zscnprobe(cn) 668 struct consdev *cn; 669 { 670 } 671 672 void 673 zscninit(cn) 674 struct consdev *cn; 675 { 676 extern const struct cdevsw zstty_cdevsw; 677 678 cons_port = prom_getconsole(); 679 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), cons_port); 680 cn->cn_pri = CN_REMOTE; 681 zs_hwflags[0][cons_port] = ZS_HWFLAG_CONSOLE; 682 } 683 684 int 685 zscngetc(dev) 686 dev_t dev; 687 { 688 struct zschan *zs; 689 690 zs = zs_get_chan_addr(0, cons_port); 691 return zs_getc(zs); 692 } 693 694 void 695 zscnputc(dev, c) 696 dev_t dev; 697 int c; 698 { 699 struct zschan *zs; 700 701 zs = zs_get_chan_addr(0, cons_port); 702 zs_putc(zs, c); 703 } 704 705 void 706 zscnpollc(dev, on) 707 dev_t dev; 708 int on; 709 { 710 } 711