1 /* $NetBSD: intr.h,v 1.16 2007/12/03 15:33:56 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _MACHINE_INTR_H_ 34 #define _MACHINE_INTR_H_ 35 36 #define IPL_NONE 0 /* disable only this interrupt */ 37 #define IPL_SOFTCLOCK 1 /* generic software interrupts */ 38 #define IPL_SOFTBIO 1 /* clock software interrupts */ 39 #define IPL_SOFTNET 2 /* network software interrupts */ 40 #define IPL_SOFTSERIAL 2 /* serial software interrupts */ 41 #define IPL_VM 3 42 #define IPL_SCHED 4 43 #define IPL_HIGH 4 /* disable all interrupts */ 44 45 #define IPL_N 5 46 47 /* Interrupt sharing types. */ 48 #define IST_NONE 0 /* none */ 49 #define IST_PULSE 1 /* pulsed */ 50 #define IST_EDGE 2 /* edge-triggered */ 51 #define IST_LEVEL 3 /* level-triggered */ 52 53 #ifdef _KERNEL 54 #ifndef _LOCORE 55 #include <sys/types.h> 56 #include <sys/device.h> 57 #include <sys/queue.h> 58 #include <mips/locore.h> 59 60 /* 61 * software simulated interrupt 62 */ 63 #define setsoft(x) do { \ 64 extern u_int ssir; \ 65 int _s; \ 66 \ 67 _s = splhigh(); \ 68 ssir |= 1 << (x); \ 69 _setsoftintr(MIPS_SOFT_INT_MASK_1); \ 70 splx(_s); \ 71 } while (0) 72 73 /* 74 * nesting interrupt masks. 75 */ 76 #define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0 77 #define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0) 78 #define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1) 79 #define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0) 80 #define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1) 81 #define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2) 82 #define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3) 83 #define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4) 84 85 #define spl0() (void)_spllower(0) 86 #define splx(s) (void)_splset(s) 87 #define splvm() _splraise(MIPS_INT_MASK_SPL2) 88 #define splsched() _splraise(MIPS_INT_MASK_SPL2) 89 #define splhigh() _splraise(MIPS_INT_MASK_SPL2) 90 91 #define splsoftclock() _splraise(MIPS_INT_MASK_SPL_SOFT0) 92 #define splsoftbio() _splraise(MIPS_INT_MASK_SPL_SOFT0) 93 #define splsoftnet() _splraise(MIPS_INT_MASK_SPL_SOFT1) 94 #define splsoftserial() _splraise(MIPS_INT_MASK_SPL_SOFT1) 95 96 typedef int ipl_t; 97 typedef struct { 98 int _sr; 99 } ipl_cookie_t; 100 101 ipl_cookie_t makeiplcookie(ipl_t ipl); 102 103 static inline int 104 splraiseipl(ipl_cookie_t icookie) 105 { 106 107 return _splraise(icookie._sr); 108 } 109 110 struct mipsco_intrhand { 111 LIST_ENTRY(mipsco_intrhand) 112 ih_q; 113 int (*ih_fun) __P((void *)); 114 void *ih_arg; 115 struct mipsco_intr *ih_intrhead; 116 int ih_pending; 117 }; 118 119 struct mipsco_intr { 120 LIST_HEAD(,mipsco_intrhand) 121 intr_q; 122 struct evcnt ih_evcnt; 123 unsigned long intr_siq; 124 }; 125 126 127 extern struct mipsco_intrhand intrtab[]; 128 129 #define SYS_INTR_LEVEL0 0 130 #define SYS_INTR_LEVEL1 1 131 #define SYS_INTR_LEVEL2 2 132 #define SYS_INTR_LEVEL3 3 133 #define SYS_INTR_LEVEL4 4 134 #define SYS_INTR_LEVEL5 5 135 #define SYS_INTR_SCSI 6 136 #define SYS_INTR_TIMER 7 137 #define SYS_INTR_ETHER 8 138 #define SYS_INTR_SCC0 9 139 #define SYS_INTR_FDC 10 140 #define SYS_INTR_ATBUS 11 141 142 #define MAX_INTR_COOKIES 16 143 144 #define CALL_INTR(lev) ((*intrtab[lev].ih_fun)(intrtab[lev].ih_arg)) 145 146 #endif /* !_LOCORE */ 147 #endif /* _KERNEL */ 148 #endif /* _MACHINE_INTR_H_ */ 149