1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * SCD Constants and Macros File: sb1250_scd.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the System Control and Debug module on the 1250. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50 #ifndef _SB1250_SCD_H 51 #define _SB1250_SCD_H 52 53 #include "sb1250_defs.h" 54 55 /* ********************************************************************* 56 * System control/debug registers 57 ********************************************************************* */ 58 59 /* 60 * System Revision Register (Table 4-1) 61 */ 62 63 #define M_SYS_RESERVED _SB_MAKEMASK(8,0) 64 65 #define S_SYS_REVISION _SB_MAKE64(8) 66 #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) 67 #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 68 #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 69 70 #if SIBYTE_HDR_FEATURE_CHIP(1250) 71 #define K_SYS_REVISION_BCM1250_PASS1 0x01 72 #define K_SYS_REVISION_BCM1250_PASS2 0x03 73 #define K_SYS_REVISION_BCM1250_A10 0x0b 74 #define K_SYS_REVISION_BCM1250_PASS2_2 0x10 75 #define K_SYS_REVISION_BCM1250_B2 0x11 76 #define K_SYS_REVISION_BCM1250_PASS3 0x20 77 #define K_SYS_REVISION_BCM1250_C1 0x21 78 #define K_SYS_REVISION_BCM1250_C2 0x22 79 80 /* XXX: discourage people from using these constants. */ 81 #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 82 #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 83 #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 84 #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 85 #endif /* 1250 */ 86 87 #if SIBYTE_HDR_FEATURE_CHIP(112x) 88 #define K_SYS_REVISION_BCM112x_A1 0x20 89 #define K_SYS_REVISION_BCM112x_A2 0x21 90 #endif /* 112x */ 91 92 /* XXX: discourage people from using these constants. */ 93 #define S_SYS_PART _SB_MAKE64(16) 94 #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) 95 #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) 96 #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) 97 98 /* XXX: discourage people from using these constants. */ 99 #define K_SYS_PART_SB1250 0x1250 100 #define K_SYS_PART_BCM1120 0x1121 101 #define K_SYS_PART_BCM1125 0x1123 102 #define K_SYS_PART_BCM1125H 0x1124 103 104 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 105 #define S_SYS_SOC_TYPE _SB_MAKE64(16) 106 #define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) 107 #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) 108 #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) 109 110 #define K_SYS_SOC_TYPE_BCM1250 0x0 111 #define K_SYS_SOC_TYPE_BCM1120 0x1 112 #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ 113 #define K_SYS_SOC_TYPE_BCM1125 0x3 114 #define K_SYS_SOC_TYPE_BCM1125H 0x4 115 #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ 116 #define K_SYS_SOC_TYPE_BCM1x80 0x6 117 #define K_SYS_SOC_TYPE_BCM1x55 0x7 118 119 /* 120 * Calculate correct SOC type given a copy of system revision register. 121 * 122 * (For the assembler version, sysrev and dest may be the same register. 123 * Also, it clobbers AT.) 124 */ 125 #ifdef __ASSEMBLER__ 126 #define SYS_SOC_TYPE(dest, sysrev) \ 127 .set push ; \ 128 .set reorder ; \ 129 dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ 130 andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ 131 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ 132 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ 133 b 992f ; \ 134 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ 135 992: \ 136 .set pop 137 #else 138 #define SYS_SOC_TYPE(sysrev) \ 139 ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ 140 || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ 141 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) 142 #endif 143 144 #define S_SYS_WID _SB_MAKE64(32) 145 #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) 146 #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 147 #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 148 149 /* System Manufacturing Register 150 * Register: SCD_SYSTEM_MANUF 151 */ 152 153 /* Wafer ID: bits 31:0 */ 154 #define S_SYS_WAFERID1_200 _SB_MAKE64(0) 155 #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) 156 #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) 157 #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) 158 159 #define S_SYS_BIN _SB_MAKE64(32) 160 #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) 161 #define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) 162 #define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) 163 164 /* Wafer ID: bits 39:36 */ 165 #define S_SYS_WAFERID2_200 _SB_MAKE64(36) 166 #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) 167 #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) 168 #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) 169 170 /* Wafer ID: bits 39:0 */ 171 #define S_SYS_WAFERID_300 _SB_MAKE64(0) 172 #define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) 173 #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) 174 #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) 175 176 #define S_SYS_XPOS _SB_MAKE64(40) 177 #define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) 178 #define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) 179 #define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) 180 181 #define S_SYS_YPOS _SB_MAKE64(46) 182 #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) 183 #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) 184 #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 185 186 /* 187 * System Config Register (Table 4-2) 188 * Register: SCD_SYSTEM_CFG 189 */ 190 191 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) 192 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) 193 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) 194 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 195 196 #define S_SYS_PLL_DIV _SB_MAKE64(7) 197 #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) 198 #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) 199 #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) 200 201 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 202 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 203 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) 204 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) 205 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 206 207 #define S_SYS_BOOT_MODE _SB_MAKE64(17) 208 #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) 209 #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) 210 #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) 211 #define K_SYS_BOOT_MODE_ROM32 0 212 #define K_SYS_BOOT_MODE_ROM8 1 213 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 214 #define K_SYS_BOOT_MODE_SMBUS_BIG 3 215 216 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19) 217 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) 218 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) 219 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 220 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) 221 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) 222 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 223 224 #define S_SYS_CONFIG 26 225 #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) 226 #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) 227 #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) 228 229 /* The following bits are writeable by JTAG only. */ 230 231 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32) 232 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 233 234 #define S_SYS_CLKCOUNT 34 235 #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) 236 #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) 237 #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) 238 239 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 240 241 #define S_SYS_PLL_IREF 43 242 #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) 243 244 #define S_SYS_PLL_VCO 45 245 #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) 246 247 #define S_SYS_PLL_VREG 47 248 #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) 249 250 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 251 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 252 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) 253 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) 254 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53) 255 256 /* End of bits writable by JTAG only. */ 257 258 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) 259 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) 260 261 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56) 262 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57) 263 264 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) 265 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59) 266 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) 267 268 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61) 269 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62) 270 271 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 272 #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) 273 #endif /* 1250 PASS2 || 112x PASS1 */ 274 275 276 /* 277 * Mailbox Registers (Table 4-3) 278 * Registers: SCD_MBOX_CPU_x 279 */ 280 281 #define S_MBOX_INT_3 0 282 #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) 283 #define S_MBOX_INT_2 16 284 #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) 285 #define S_MBOX_INT_1 32 286 #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) 287 #define S_MBOX_INT_0 48 288 #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) 289 290 /* 291 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 292 * Registers: SCD_WDOG_INIT_CNT_x 293 */ 294 295 #define V_SCD_WDOG_FREQ 1000000 296 297 #define S_SCD_WDOG_INIT 0 298 #define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) 299 300 #define S_SCD_WDOG_CNT 0 301 #define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) 302 303 #define S_SCD_WDOG_ENABLE 0 304 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) 305 306 #define S_SCD_WDOG_RESET_TYPE 2 307 #define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) 308 #define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) 309 #define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) 310 311 #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 312 #define K_SCD_WDOG_RESET_SOFT 1 313 #define K_SCD_WDOG_RESET_CPU0 3 314 #define K_SCD_WDOG_RESET_CPU1 5 315 #define K_SCD_WDOG_RESET_BOTH_CPUS 7 316 317 /* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ 318 #if SIBYTE_HDR_FEATURE(1250, PASS3) 319 #define S_SCD_WDOG_HAS_RESET 8 320 #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) 321 #endif 322 323 324 /* 325 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) 326 */ 327 328 #define V_SCD_TIMER_FREQ 1000000 329 330 #define S_SCD_TIMER_INIT 0 331 #define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) 332 #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 333 #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 334 335 #define S_SCD_TIMER_CNT 0 336 #define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) 337 #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 338 #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 339 340 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 341 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 342 #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE 343 344 /* 345 * System Performance Counters 346 */ 347 348 #define S_SPC_CFG_SRC0 0 349 #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 350 #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 351 #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) 352 353 #define S_SPC_CFG_SRC1 8 354 #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) 355 #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) 356 #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) 357 358 #define S_SPC_CFG_SRC2 16 359 #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) 360 #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) 361 #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) 362 363 #define S_SPC_CFG_SRC3 24 364 #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) 365 #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 366 #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 367 368 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 369 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 370 371 372 /* 373 * Bus Watcher 374 */ 375 376 #define S_SCD_BERR_TID 8 377 #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) 378 #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) 379 #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) 380 381 #define S_SCD_BERR_RID 18 382 #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) 383 #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) 384 #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) 385 386 #define S_SCD_BERR_DCODE 22 387 #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) 388 #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) 389 #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) 390 391 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 392 393 394 #define S_SCD_L2ECC_CORR_D 0 395 #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) 396 #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) 397 #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) 398 399 #define S_SCD_L2ECC_BAD_D 8 400 #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) 401 #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) 402 #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) 403 404 #define S_SCD_L2ECC_CORR_T 16 405 #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) 406 #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) 407 #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) 408 409 #define S_SCD_L2ECC_BAD_T 24 410 #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) 411 #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) 412 #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) 413 414 #define S_SCD_MEM_ECC_CORR 0 415 #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) 416 #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) 417 #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) 418 419 #define S_SCD_MEM_ECC_BAD 8 420 #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) 421 #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) 422 #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) 423 424 #define S_SCD_MEM_BUSERR 16 425 #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) 426 #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) 427 #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) 428 429 430 /* 431 * Address Trap Registers 432 */ 433 434 #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 435 #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 436 437 #define S_ATRAP_CFG_CNT 0 438 #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) 439 #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) 440 #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) 441 442 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 443 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 444 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) 445 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 446 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 447 448 #define S_ATRAP_CFG_AGENTID 8 449 #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) 450 #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) 451 #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) 452 453 #define K_BUS_AGENT_CPU0 0 454 #define K_BUS_AGENT_CPU1 1 455 #define K_BUS_AGENT_IOB0 2 456 #define K_BUS_AGENT_IOB1 3 457 #define K_BUS_AGENT_SCD 4 458 #define K_BUS_AGENT_RESERVED 5 459 #define K_BUS_AGENT_L2C 6 460 #define K_BUS_AGENT_MC 7 461 462 #define S_ATRAP_CFG_CATTR 12 463 #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) 464 #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) 465 #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) 466 467 #define K_ATRAP_CFG_CATTR_IGNORE 0 468 #define K_ATRAP_CFG_CATTR_UNC 1 469 #define K_ATRAP_CFG_CATTR_CACHEABLE 2 470 #define K_ATRAP_CFG_CATTR_NONCOH 3 471 #define K_ATRAP_CFG_CATTR_COHERENT 4 472 #define K_ATRAP_CFG_CATTR_NOTUNC 5 473 #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 474 #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 475 476 /* 477 * Trace Buffer Config register 478 */ 479 480 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 481 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 482 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 483 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) 484 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) 485 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 486 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 487 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 488 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 489 #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 490 #endif /* 1250 PASS2 || 112x PASS1 */ 491 492 #define S_SCD_TRACE_CFG_CUR_ADDR 10 493 #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 494 #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 495 #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 496 497 /* 498 * Trace Event registers 499 */ 500 501 #define S_SCD_TREVT_ADDR_MATCH 0 502 #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) 503 #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) 504 #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) 505 506 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 507 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 508 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) 509 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) 510 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) 511 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) 512 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 513 514 #define S_SCD_TREVT_REQID 12 515 #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) 516 #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) 517 #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) 518 519 #define S_SCD_TREVT_RESPID 16 520 #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) 521 #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) 522 #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) 523 524 #define S_SCD_TREVT_DATAID 20 525 #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) 526 #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) 527 #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) 528 529 #define S_SCD_TREVT_COUNT 24 530 #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) 531 #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) 532 #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) 533 534 /* 535 * Trace Sequence registers 536 */ 537 538 #define S_SCD_TRSEQ_EVENT4 0 539 #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) 540 #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) 541 #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) 542 543 #define S_SCD_TRSEQ_EVENT3 4 544 #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) 545 #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) 546 #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) 547 548 #define S_SCD_TRSEQ_EVENT2 8 549 #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) 550 #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) 551 #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) 552 553 #define S_SCD_TRSEQ_EVENT1 12 554 #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) 555 #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) 556 #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) 557 558 #define K_SCD_TRSEQ_E0 0 559 #define K_SCD_TRSEQ_E1 1 560 #define K_SCD_TRSEQ_E2 2 561 #define K_SCD_TRSEQ_E3 3 562 #define K_SCD_TRSEQ_E0_E1 4 563 #define K_SCD_TRSEQ_E1_E2 5 564 #define K_SCD_TRSEQ_E2_E3 6 565 #define K_SCD_TRSEQ_E0_E1_E2 7 566 #define K_SCD_TRSEQ_E0_E1_E2_E3 8 567 #define K_SCD_TRSEQ_E0E1 9 568 #define K_SCD_TRSEQ_E0E1E2 10 569 #define K_SCD_TRSEQ_E0E1E2E3 11 570 #define K_SCD_TRSEQ_E0E1_E2 12 571 #define K_SCD_TRSEQ_E0E1_E2E3 13 572 #define K_SCD_TRSEQ_E0E1_E2_E3 14 573 #define K_SCD_TRSEQ_IGNORED 15 574 575 #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ 576 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ 577 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ 578 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 579 580 #define S_SCD_TRSEQ_FUNCTION 16 581 #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) 582 #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) 583 #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) 584 585 #define K_SCD_TRSEQ_FUNC_NOP 0 586 #define K_SCD_TRSEQ_FUNC_START 1 587 #define K_SCD_TRSEQ_FUNC_STOP 2 588 #define K_SCD_TRSEQ_FUNC_FREEZE 3 589 590 #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) 591 #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) 592 #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) 593 #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) 594 595 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) 596 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) 597 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) 598 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) 599 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) 600 601 #endif 602