1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Memory Controller constants File: sb1250_mc.h 5 * 6 * This module contains constants and macros useful for 7 * programming the memory controller. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50 51 #ifndef _SB1250_MC_H 52 #define _SB1250_MC_H 53 54 #include "sb1250_defs.h" 55 56 /* 57 * Memory Channel Config Register (table 6-14) 58 */ 59 60 #define S_MC_RESERVED0 0 61 #define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) 62 63 #define S_MC_CHANNEL_SEL 8 64 #define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) 65 #define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) 66 #define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) 67 68 #define S_MC_BANK0_MAP 16 69 #define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) 70 #define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) 71 #define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) 72 73 #define K_MC_BANK0_MAP_DEFAULT 0x00 74 #define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) 75 76 #define S_MC_BANK1_MAP 20 77 #define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) 78 #define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) 79 #define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) 80 81 #define K_MC_BANK1_MAP_DEFAULT 0x08 82 #define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) 83 84 #define S_MC_BANK2_MAP 24 85 #define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) 86 #define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) 87 #define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) 88 89 #define K_MC_BANK2_MAP_DEFAULT 0x09 90 #define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) 91 92 #define S_MC_BANK3_MAP 28 93 #define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) 94 #define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) 95 #define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) 96 97 #define K_MC_BANK3_MAP_DEFAULT 0x0C 98 #define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) 99 100 #define M_MC_RESERVED1 _SB_MAKEMASK(8,32) 101 102 #define S_MC_QUEUE_SIZE 40 103 #define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) 104 #define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) 105 #define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) 106 #define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) 107 108 #define S_MC_AGE_LIMIT 44 109 #define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) 110 #define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) 111 #define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) 112 #define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) 113 114 #define S_MC_WR_LIMIT 48 115 #define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) 116 #define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) 117 #define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) 118 #define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) 119 120 #define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) 121 122 #define M_MC_RESERVED2 _SB_MAKEMASK(3,53) 123 124 #define S_MC_CS_MODE 56 125 #define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) 126 #define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) 127 #define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) 128 129 #define K_MC_CS_MODE_MSB_CS 0 130 #define K_MC_CS_MODE_INTLV_CS 15 131 #define K_MC_CS_MODE_MIXED_CS_10 12 132 #define K_MC_CS_MODE_MIXED_CS_30 6 133 #define K_MC_CS_MODE_MIXED_CS_32 3 134 135 #define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) 136 #define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) 137 #define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10) 138 #define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30) 139 #define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32) 140 141 #define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) 142 #define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) 143 #define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) 144 #define M_MC_DEBUG _SB_MAKEMASK1(63) 145 146 #define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \ 147 V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \ 148 V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \ 149 M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT 150 151 152 /* 153 * Memory clock config register (Table 6-15) 154 * 155 * Note: this field has been updated to be consistent with the errata to 0.2 156 */ 157 158 #define S_MC_CLK_RATIO 0 159 #define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) 160 #define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) 161 #define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) 162 163 #define K_MC_CLK_RATIO_2X 4 164 #define K_MC_CLK_RATIO_25X 5 165 #define K_MC_CLK_RATIO_3X 6 166 #define K_MC_CLK_RATIO_35X 7 167 #define K_MC_CLK_RATIO_4X 8 168 #define K_MC_CLK_RATIO_45X 9 169 170 #define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X) 171 #define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) 172 #define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) 173 #define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) 174 #define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) 175 #define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) 176 #define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X 177 178 #define S_MC_REF_RATE 8 179 #define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) 180 #define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) 181 #define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) 182 183 #define K_MC_REF_RATE_100MHz 0x62 184 #define K_MC_REF_RATE_133MHz 0x81 185 #define K_MC_REF_RATE_200MHz 0xC4 186 187 #define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) 188 #define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) 189 #define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) 190 #define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz 191 192 #define S_MC_CLOCK_DRIVE 16 193 #define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) 194 #define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) 195 #define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) 196 #define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) 197 198 #define S_MC_DATA_DRIVE 20 199 #define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) 200 #define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) 201 #define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) 202 #define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) 203 204 #define S_MC_ADDR_DRIVE 24 205 #define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) 206 #define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) 207 #define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) 208 #define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) 209 210 #if SIBYTE_HDR_FEATURE(112x, PASS1) 211 #define M_MC_REF_DISABLE _SB_MAKEMASK1(30) 212 #endif /* 112x PASS1 */ 213 214 #define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) 215 216 #define S_MC_DQI_SKEW 32 217 #define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) 218 #define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) 219 #define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) 220 #define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) 221 222 #define S_MC_DQO_SKEW 40 223 #define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) 224 #define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) 225 #define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) 226 #define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) 227 228 #define S_MC_ADDR_SKEW 48 229 #define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) 230 #define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) 231 #define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) 232 #define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) 233 234 #define S_MC_DLL_DEFAULT 56 235 #define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) 236 #define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) 237 #define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) 238 #define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) 239 240 #define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ 241 V_MC_ADDR_SKEW_DEFAULT | \ 242 V_MC_DQO_SKEW_DEFAULT | \ 243 V_MC_DQI_SKEW_DEFAULT | \ 244 V_MC_ADDR_DRIVE_DEFAULT | \ 245 V_MC_DATA_DRIVE_DEFAULT | \ 246 V_MC_CLOCK_DRIVE_DEFAULT | \ 247 V_MC_REF_RATE_DEFAULT 248 249 250 251 /* 252 * DRAM Command Register (Table 6-13) 253 */ 254 255 #define S_MC_COMMAND 0 256 #define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) 257 #define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) 258 #define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) 259 260 #define K_MC_COMMAND_EMRS 0 261 #define K_MC_COMMAND_MRS 1 262 #define K_MC_COMMAND_PRE 2 263 #define K_MC_COMMAND_AR 3 264 #define K_MC_COMMAND_SETRFSH 4 265 #define K_MC_COMMAND_CLRRFSH 5 266 #define K_MC_COMMAND_SETPWRDN 6 267 #define K_MC_COMMAND_CLRPWRDN 7 268 269 #define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) 270 #define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) 271 #define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) 272 #define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) 273 #define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) 274 #define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) 275 #define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) 276 #define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) 277 278 #define M_MC_CS0 _SB_MAKEMASK1(4) 279 #define M_MC_CS1 _SB_MAKEMASK1(5) 280 #define M_MC_CS2 _SB_MAKEMASK1(6) 281 #define M_MC_CS3 _SB_MAKEMASK1(7) 282 283 /* 284 * DRAM Mode Register (Table 6-14) 285 */ 286 287 #define S_MC_EMODE 0 288 #define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) 289 #define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) 290 #define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) 291 #define V_MC_EMODE_DEFAULT V_MC_EMODE(0) 292 293 #define S_MC_MODE 16 294 #define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) 295 #define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) 296 #define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) 297 #define V_MC_MODE_DEFAULT V_MC_MODE(0x22) 298 299 #define S_MC_DRAM_TYPE 32 300 #define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) 301 #define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) 302 #define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) 303 304 #define K_MC_DRAM_TYPE_JEDEC 0 305 #define K_MC_DRAM_TYPE_FCRAM 1 306 #define K_MC_DRAM_TYPE_SGRAM 2 307 308 #define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) 309 #define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) 310 #define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) 311 312 #define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35) 313 314 #if SIBYTE_HDR_FEATURE(112x, PASS1) 315 #define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) 316 #define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(38) 317 #endif /* 112x PASS1 */ 318 319 320 321 /* 322 * SDRAM Timing Register (Table 6-15) 323 */ 324 325 #define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60) 326 #define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61) 327 #define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) 328 329 #define S_MC_tFIFO 56 330 #define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) 331 #define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) 332 #define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO) 333 #define K_MC_tFIFO_DEFAULT 1 334 #define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) 335 336 #define S_MC_tRFC 52 337 #define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) 338 #define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) 339 #define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC) 340 #define K_MC_tRFC_DEFAULT 12 341 #define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) 342 343 #define S_MC_tCwCr 40 344 #define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) 345 #define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) 346 #define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr) 347 #define K_MC_tCwCr_DEFAULT 4 348 #define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) 349 350 #define S_MC_tRCr 28 351 #define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) 352 #define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) 353 #define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr) 354 #define K_MC_tRCr_DEFAULT 9 355 #define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) 356 357 #define S_MC_tRCw 24 358 #define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) 359 #define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) 360 #define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw) 361 #define K_MC_tRCw_DEFAULT 10 362 #define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) 363 364 #define S_MC_tRRD 20 365 #define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) 366 #define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) 367 #define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD) 368 #define K_MC_tRRD_DEFAULT 2 369 #define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) 370 371 #define S_MC_tRP 16 372 #define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) 373 #define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) 374 #define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP) 375 #define K_MC_tRP_DEFAULT 4 376 #define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) 377 378 #define S_MC_tCwD 8 379 #define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) 380 #define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) 381 #define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD) 382 #define K_MC_tCwD_DEFAULT 1 383 #define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) 384 385 #define M_tCrDh _SB_MAKEMASK1(7) 386 #define M_MC_tCrDh M_tCrDh 387 388 #define S_MC_tCrD 4 389 #define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) 390 #define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) 391 #define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD) 392 #define K_MC_tCrD_DEFAULT 2 393 #define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) 394 395 #define S_MC_tRCD 0 396 #define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) 397 #define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) 398 #define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD) 399 #define K_MC_tRCD_DEFAULT 3 400 #define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) 401 402 #define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ 403 V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ 404 V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ 405 V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ 406 V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ 407 V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ 408 V_MC_tRP(K_MC_tRP_DEFAULT) | \ 409 V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ 410 V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ 411 V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ 412 M_MC_r2rIDLE_TWOCYCLES 413 414 /* 415 * Errata says these are not the default 416 * M_MC_w2rIDLE_TWOCYCLES | \ 417 * M_MC_r2wIDLE_TWOCYCLES | \ 418 */ 419 420 421 /* 422 * Chip Select Start Address Register (Table 6-17) 423 */ 424 425 #define S_MC_CS0_START 0 426 #define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) 427 #define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) 428 #define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) 429 430 #define S_MC_CS1_START 16 431 #define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) 432 #define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) 433 #define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) 434 435 #define S_MC_CS2_START 32 436 #define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) 437 #define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) 438 #define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) 439 440 #define S_MC_CS3_START 48 441 #define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) 442 #define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) 443 #define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) 444 445 /* 446 * Chip Select End Address Register (Table 6-18) 447 */ 448 449 #define S_MC_CS0_END 0 450 #define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) 451 #define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) 452 #define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) 453 454 #define S_MC_CS1_END 16 455 #define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) 456 #define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) 457 #define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) 458 459 #define S_MC_CS2_END 32 460 #define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) 461 #define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) 462 #define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) 463 464 #define S_MC_CS3_END 48 465 #define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) 466 #define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) 467 #define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) 468 469 /* 470 * Chip Select Interleave Register (Table 6-19) 471 */ 472 473 #define S_MC_INTLV_RESERVED 0 474 #define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) 475 476 #define S_MC_INTERLEAVE 7 477 #define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) 478 #define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) 479 480 #define S_MC_INTLV_MBZ 25 481 #define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) 482 483 /* 484 * Row Address Bits Register (Table 6-20) 485 */ 486 487 #define S_MC_RAS_RESERVED 0 488 #define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) 489 490 #define S_MC_RAS_SELECT 12 491 #define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) 492 #define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) 493 494 #define S_MC_RAS_MBZ 37 495 #define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) 496 497 498 /* 499 * Column Address Bits Register (Table 6-21) 500 */ 501 502 #define S_MC_CAS_RESERVED 0 503 #define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) 504 505 #define S_MC_CAS_SELECT 5 506 #define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) 507 #define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) 508 509 #define S_MC_CAS_MBZ 23 510 #define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) 511 512 513 /* 514 * Bank Address Address Bits Register (Table 6-22) 515 */ 516 517 #define S_MC_BA_RESERVED 0 518 #define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) 519 520 #define S_MC_BA_SELECT 5 521 #define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) 522 #define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) 523 524 #define S_MC_BA_MBZ 25 525 #define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) 526 527 /* 528 * Chip Select Attribute Register (Table 6-23) 529 */ 530 531 #define K_MC_CS_ATTR_CLOSED 0 532 #define K_MC_CS_ATTR_CASCHECK 1 533 #define K_MC_CS_ATTR_HINT 2 534 #define K_MC_CS_ATTR_OPEN 3 535 536 #define S_MC_CS0_PAGE 0 537 #define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) 538 #define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) 539 #define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) 540 541 #define S_MC_CS1_PAGE 16 542 #define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) 543 #define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) 544 #define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) 545 546 #define S_MC_CS2_PAGE 32 547 #define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) 548 #define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) 549 #define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) 550 551 #define S_MC_CS3_PAGE 48 552 #define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) 553 #define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) 554 #define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) 555 556 /* 557 * ECC Test ECC Register (Table 6-25) 558 */ 559 560 #define S_MC_ECC_INVERT 0 561 #define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) 562 563 564 #endif 565