1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Generic Bus Constants File: sb1250_genbus.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the SB1250's Generic Bus interface 8 * 9 * SB1250 specification level: User's manual 10/21/02 10 * BCM1280 specification level: User's Manual 11/14/03 11 * 12 * Author: Mitch Lichtenberg 13 * 14 ********************************************************************* 15 * 16 * Copyright 2000,2001,2002,2003 17 * Broadcom Corporation. All rights reserved. 18 * 19 * This software is furnished under license and may be used and 20 * copied only in accordance with the following terms and 21 * conditions. Subject to these conditions, you may download, 22 * copy, install, use, modify and distribute modified or unmodified 23 * copies of this software in source and/or binary form. No title 24 * or ownership is transferred hereby. 25 * 26 * 1) Any source code used, modified or distributed must reproduce 27 * and retain this copyright notice and list of conditions 28 * as they appear in the source file. 29 * 30 * 2) No right is granted to use any trade name, trademark, or 31 * logo of Broadcom Corporation. The "Broadcom Corporation" 32 * name may not be used to endorse or promote products derived 33 * from this software without the prior written permission of 34 * Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 52 #ifndef _SB1250_GENBUS_H 53 #define _SB1250_GENBUS_H 54 55 #include "sb1250_defs.h" 56 57 /* 58 * Generic Bus Region Configuration Registers (Table 11-4) 59 */ 60 61 #define S_IO_RDY_ACTIVE 0 62 #define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) 63 64 #define S_IO_ENA_RDY 1 65 #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) 66 67 #define S_IO_WIDTH_SEL 2 68 #define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) 69 #define K_IO_WIDTH_SEL_1 0 70 #define K_IO_WIDTH_SEL_2 1 71 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 72 #define K_IO_WIDTH_SEL_1L 2 73 #endif /* 1250 PASS2 || 112x PASS1 */ 74 #define K_IO_WIDTH_SEL_4 3 75 #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) 76 #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) 77 78 #define S_IO_PARITY_ENA 4 79 #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) 80 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 81 #define S_IO_BURST_EN 5 82 #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) 83 #endif /* 1250 PASS2 || 112x PASS1 */ 84 #define S_IO_PARITY_ODD 6 85 #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) 86 #define S_IO_NONMUX 7 87 #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) 88 89 #define S_IO_TIMEOUT 8 90 #define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) 91 #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) 92 #define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) 93 94 /* 95 * Generic Bus Region Size register (Table 11-5) 96 */ 97 98 #define S_IO_MULT_SIZE 0 99 #define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) 100 #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) 101 #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) 102 103 #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ 104 105 /* 106 * Generic Bus Region Address (Table 11-6) 107 */ 108 109 #define S_IO_START_ADDR 0 110 #define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) 111 #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) 112 #define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) 113 114 #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ 115 116 #define M_IO_BLK_CACHE _SB_MAKEMASK1(15) 117 118 119 /* 120 * Generic Bus Timing 0 Registers (Table 11-7) 121 */ 122 123 #define S_IO_ALE_WIDTH 0 124 #define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) 125 #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) 126 #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) 127 128 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 129 #define M_IO_EARLY_CS _SB_MAKEMASK1(3) 130 #endif /* 1250 PASS2 || 112x PASS1 */ 131 132 #define S_IO_ALE_TO_CS 4 133 #define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) 134 #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) 135 #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) 136 137 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 138 #define S_IO_BURST_WIDTH _SB_MAKE64(6) 139 #define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) 140 #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) 141 #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) 142 #endif /* 1250 PASS2 || 112x PASS1 */ 143 144 #define S_IO_CS_WIDTH 8 145 #define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) 146 #define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) 147 #define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) 148 149 #define S_IO_RDY_SMPLE 13 150 #define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) 151 #define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) 152 #define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) 153 154 155 /* 156 * Generic Bus Timing 1 Registers (Table 11-8) 157 */ 158 159 #define S_IO_ALE_TO_WRITE 0 160 #define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) 161 #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) 162 #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) 163 164 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 165 #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) 166 #endif /* 1250 PASS2 || 112x PASS1 */ 167 168 #define S_IO_WRITE_WIDTH 4 169 #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) 170 #define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) 171 #define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) 172 173 #define S_IO_IDLE_CYCLE 8 174 #define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) 175 #define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) 176 #define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) 177 178 #define S_IO_OE_TO_CS 12 179 #define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) 180 #define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) 181 #define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) 182 183 #define S_IO_CS_TO_OE 14 184 #define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) 185 #define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) 186 #define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) 187 188 /* 189 * Generic Bus Interrupt Status Register (Table 11-9) 190 */ 191 192 #define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) 193 #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) 194 #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) 195 #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) 196 #define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3) 197 #define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4) 198 #define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5) 199 #define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6) 200 #define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7) 201 202 #define M_IO_RD_PAR_INT _SB_MAKEMASK1(9) 203 #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) 204 #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) 205 #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) 206 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 207 #define M_IO_COH_ERR _SB_MAKEMASK1(14) 208 #endif /* 1250 PASS2 || 112x PASS1 */ 209 210 211 /* 212 * Generic Bus Output Drive Control Register 0 (Table 14-18) 213 */ 214 215 #define S_IO_SLEW0 0 216 #define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0) 217 #define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0) 218 #define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0) 219 220 #define S_IO_DRV_A 2 221 #define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A) 222 #define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A) 223 #define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A) 224 225 #define S_IO_DRV_B 6 226 #define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B) 227 #define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B) 228 #define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B) 229 230 #define S_IO_DRV_C 10 231 #define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C) 232 #define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C) 233 #define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C) 234 235 #define S_IO_DRV_D 14 236 #define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D) 237 #define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D) 238 #define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D) 239 240 /* 241 * Generic Bus Output Drive Control Register 1 (Table 14-19) 242 */ 243 244 #define S_IO_DRV_E 2 245 #define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E) 246 #define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E) 247 #define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E) 248 249 #define S_IO_DRV_F 6 250 #define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F) 251 #define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F) 252 #define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F) 253 254 #define S_IO_SLEW1 8 255 #define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1) 256 #define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1) 257 #define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1) 258 259 #define S_IO_DRV_G 10 260 #define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G) 261 #define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G) 262 #define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G) 263 264 #define S_IO_SLEW2 12 265 #define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2) 266 #define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2) 267 #define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2) 268 269 #define S_IO_DRV_H 14 270 #define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H) 271 #define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H) 272 #define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H) 273 274 /* 275 * Generic Bus Output Drive Control Register 2 (Table 14-20) 276 */ 277 278 #define S_IO_DRV_J 2 279 #define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J) 280 #define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J) 281 #define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J) 282 283 #define S_IO_DRV_K 6 284 #define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K) 285 #define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K) 286 #define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K) 287 288 #define S_IO_DRV_L 10 289 #define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L) 290 #define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L) 291 #define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L) 292 293 #define S_IO_DRV_M 14 294 #define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M) 295 #define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M) 296 #define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M) 297 298 /* 299 * Generic Bus Output Drive Control Register 3 (Table 14-21) 300 */ 301 302 #define S_IO_SLEW3 0 303 #define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3) 304 #define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3) 305 #define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3) 306 307 #define S_IO_DRV_N 2 308 #define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N) 309 #define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N) 310 #define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N) 311 312 #define S_IO_DRV_P 6 313 #define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P) 314 #define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P) 315 #define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P) 316 317 #define S_IO_DRV_Q 10 318 #define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q) 319 #define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q) 320 #define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q) 321 322 #define S_IO_DRV_R 14 323 #define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R) 324 #define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R) 325 #define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R) 326 327 328 /* 329 * PCMCIA configuration register (Table 12-6) 330 */ 331 332 #define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0) 333 #define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1) 334 #define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2) 335 #define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3) 336 #define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4) 337 #define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5) 338 #define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6) 339 #define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7) 340 #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) 341 #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) 342 343 #if SIBYTE_HDR_FEATURE_CHIP(1280) 344 #define S_PCMCIA_MODE 16 345 #define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE) 346 #define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE) 347 #define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE) 348 349 #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ 350 #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ 351 #define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */ 352 #define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */ 353 #define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */ 354 #define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */ 355 #define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */ 356 #endif 357 358 359 /* 360 * PCMCIA status register (Table 12-7) 361 */ 362 363 #define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0) 364 #define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1) 365 #define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2) 366 #define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3) 367 #define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4) 368 #define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5) 369 #define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6) 370 #define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7) 371 #define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8) 372 #define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9) 373 #define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10) 374 375 /* 376 * GPIO Interrupt Type Register (table 13-3) 377 */ 378 379 #define K_GPIO_INTR_DISABLE 0 380 #define K_GPIO_INTR_EDGE 1 381 #define K_GPIO_INTR_LEVEL 2 382 #define K_GPIO_INTR_SPLIT 3 383 384 #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) 385 #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) 386 #define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) 387 #define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) 388 389 #define S_GPIO_INTR_TYPE0 0 390 #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) 391 #define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) 392 #define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) 393 394 #define S_GPIO_INTR_TYPE2 2 395 #define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) 396 #define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) 397 #define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) 398 399 #define S_GPIO_INTR_TYPE4 4 400 #define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) 401 #define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) 402 #define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) 403 404 #define S_GPIO_INTR_TYPE6 6 405 #define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) 406 #define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) 407 #define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) 408 409 #define S_GPIO_INTR_TYPE8 8 410 #define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) 411 #define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) 412 #define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) 413 414 #define S_GPIO_INTR_TYPE10 10 415 #define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) 416 #define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) 417 #define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) 418 419 #define S_GPIO_INTR_TYPE12 12 420 #define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) 421 #define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) 422 #define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) 423 424 #define S_GPIO_INTR_TYPE14 14 425 #define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) 426 #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) 427 #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) 428 429 #if SIBYTE_HDR_FEATURE_CHIP(1280) 430 431 /* 432 * GPIO Interrupt Additional Type Register 433 */ 434 435 #define K_GPIO_INTR_BOTHEDGE 0 436 #define K_GPIO_INTR_RISEEDGE 1 437 #define K_GPIO_INTR_UNPRED1 2 438 #define K_GPIO_INTR_UNPRED2 3 439 440 #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) 441 #define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n)) 442 #define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n)) 443 #define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n)) 444 445 #define S_GPIO_INTR_ATYPE0 0 446 #define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0) 447 #define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0) 448 #define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0) 449 450 #define S_GPIO_INTR_ATYPE2 2 451 #define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2) 452 #define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2) 453 #define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2) 454 455 #define S_GPIO_INTR_ATYPE4 4 456 #define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4) 457 #define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4) 458 #define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4) 459 460 #define S_GPIO_INTR_ATYPE6 6 461 #define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6) 462 #define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6) 463 #define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6) 464 465 #define S_GPIO_INTR_ATYPE8 8 466 #define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8) 467 #define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8) 468 #define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8) 469 470 #define S_GPIO_INTR_ATYPE10 10 471 #define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10) 472 #define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10) 473 #define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10) 474 475 #define S_GPIO_INTR_ATYPE12 12 476 #define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12) 477 #define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12) 478 #define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12) 479 480 #define S_GPIO_INTR_ATYPE14 14 481 #define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14) 482 #define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14) 483 #define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14) 484 #endif 485 486 487 #endif 488