xref: /netbsd-src/sys/arch/mips/sibyte/dev/sbbuswatch.c (revision a5847cc334d9a7029f6352b847e9e8d71a0f9e0c)
1 /*	$NetBSD: sbbuswatch.c,v 1.2 2011/02/20 07:47:39 matt Exp $	*/
2 /*
3  * Copyright (c) 2010, The NetBSD Foundation, Inc.  All rights reserved.
4  *
5  * This code is derived from software contributed to The NetBSD Foundation
6  * by Cliff Neighbors.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27  * POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/cpu.h>
33 
34 #include <mips/cpu.h>
35 #include <mips/locore.h>
36 
37 #include <mips/sibyte/include/sb1250_int.h>
38 #include <mips/sibyte/include/sb1250_regs.h>
39 #include <mips/sibyte/dev/sbbuswatchvar.h>
40 
41 #define READ_REG(rp)            (mips3_ld((volatile uint64_t *)(rp)))
42 #define WRITE_REG(rp, val)      (mips3_sd((volatile uint64_t *)(rp), (val)))
43 
44 static void sibyte_bus_watch_intr(void *, uint32_t, vaddr_t);
45 
46 void
47 sibyte_bus_watch_init(void)
48 {
49 	(void)READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
50 	WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
51 	WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
52 
53 	(void)cpu_intr_establish(K_INT_BAD_ECC, IPL_DDB,
54 		sibyte_bus_watch_intr, (void *)K_INT_BAD_ECC);
55 	(void)cpu_intr_establish(K_INT_COR_ECC, IPL_DDB,
56 		sibyte_bus_watch_intr, (void *)K_INT_COR_ECC);
57 	(void)cpu_intr_establish(K_INT_IO_BUS, IPL_DDB,
58 		sibyte_bus_watch_intr, (void *)K_INT_IO_BUS);
59 }
60 
61 int
62 sibyte_bus_watch_check(unsigned int cause)
63 {
64 	uint64_t err_ctl;
65 	uint64_t cache_err_i;
66 	uint64_t cache_err_d;
67 	uint64_t cache_err_dpa;
68 	uint64_t bus_err_dpa;
69 	uint32_t bus_err_status;
70 	uint32_t l2_errors;
71 	uint32_t mem_io_errors;
72 
73 	bus_err_status = READ_REG(
74 		MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
75 
76 	if (bus_err_status == 0)
77 		return 0;
78 
79 	l2_errors = READ_REG(
80 		MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS));
81 	if (l2_errors != 0)
82 		WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
83 
84 	mem_io_errors = READ_REG(
85 		MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS));
86 	if (mem_io_errors != 0)
87 		WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
88 
89 	asm volatile("dmfc0 %0, $26, 0;" : "=r"(err_ctl));
90 	asm volatile("dmfc0 %0, $26, 1;" : "=r"(bus_err_dpa));
91 	asm volatile("dmfc0 %0, $27, 0;" : "=r"(cache_err_i));
92 	asm volatile("dmfc0 %0, $27, 1;" : "=r"(cache_err_d));
93 	asm volatile("dmfc0 %0, $27, 3;" : "=r"(cache_err_dpa));
94 
95 	printf("bus_err_status=%#x\n", bus_err_status);
96 	printf("l2_errors=%#x\n", l2_errors);
97 	printf("mem_io_errors=%#x\n", mem_io_errors);
98 	printf("err_ctl=%#"PRIx64"\n", err_ctl);
99 	printf("bus_err_dpa=%#"PRIx64"\n", bus_err_dpa);
100 	printf("cache_err_i=%#"PRIx64"\n", cache_err_i);
101 	printf("cache_err_d=%#"PRIx64"\n", cache_err_d);
102 	printf("cache_err_dpa=%#"PRIx64"\n", cache_err_dpa);
103 
104 	return -1;
105 }
106 
107 static void
108 sibyte_bus_watch_intr(void *arg, uint32_t status, vaddr_t pc)
109 {
110 	printf("%s: %p\n", __func__, arg);
111 	(void)sibyte_bus_watch_check(0);
112 }
113