1 /* $NetBSD: ralink_gpio.c,v 1.5 2014/03/12 22:21:07 mrg Exp $ */ 2 /*- 3 * Copyright (c) 2011 CradlePoint Technology, Inc. 4 * All rights reserved. 5 * 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* ra_gpio.c -- Ralink 3052 gpio driver */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ralink_gpio.c,v 1.5 2014/03/12 22:21:07 mrg Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/callout.h> 37 #include <sys/device.h> 38 #include <sys/event.h> 39 #include <sys/intr.h> 40 #include <sys/kernel.h> 41 #include <sys/systm.h> 42 43 #include <dev/cons.h> 44 45 #include <mips/cpuregs.h> 46 #include <sys/gpio.h> 47 #include <dev/gpio/gpiovar.h> 48 49 #define SLICKROCK 50 51 #include <mips/ralink/ralink_reg.h> 52 #include <mips/ralink/ralink_var.h> 53 #include <mips/ralink/ralink_gpio.h> 54 55 #if 0 56 #define ENABLE_RALINK_DEBUG_ERROR 1 57 #define ENABLE_RALINK_DEBUG_MISC 1 58 #define ENABLE_RALINK_DEBUG_INFO 1 59 #define ENABLE_RALINK_DEBUG_FORCE 1 60 #define ENABLE_RALINK_DEBUG_FUNC 1 61 #endif 62 63 #include <mips/ralink/ralink_debug.h> 64 65 /* 66 * From the RT3052 datasheet, the GPIO pins are 67 * shared with a number of other functions. Not 68 * all will be available for GPIO. To make sure 69 * pins are in GPIO mode, the GPIOMODE purpose 70 * select register must be set (reset defaults all pins 71 * as GPIO except for JTAG) 72 * 73 * Note, GPIO0 is not shared, it is the single dedicated 74 * GPIO pin. 75 * 76 * 52 pins: 77 * 78 * 40 - 51 RGMII (GE0_* pins) 79 * 24 - 39 SDRAM (MD31:MD16 pins) 80 * 22 - 23 MDIO (MDC/MDIO pins) 81 * 17 - 21 JTAG (JTAG_* pins) 82 * 15 - 16 UART Light (RXD2/TXD2 pins) 83 * 7 - 14 UART Full (8 pins) 84 * (7 - 14) UARTF_7 (3'b111 in Share mode reg) 85 * (11 - 14) UARTF_5 (3'b110 in Share mode reg, same with 6) 86 * (7 - 9) UARTF_4 (3'b100 in Share mode reg) 87 * 3 - 6 SPI (SPI_* pins) 88 * 1 - 2 I2C (I2C_SCLK/I2C_SD pins) 89 */ 90 91 #if defined(SLICKROCK) 92 #define GPIO_PINS 96 93 #else 94 #define GPIO_PINS 52 95 #endif 96 97 /* 98 * Special commands are pseudo pin numbers used to pass data to bootloader, 99 */ 100 #define BOOT_COUNT GPIO_PINS 101 #define UPGRADE (BOOT_COUNT + 1) 102 #define SPECIAL_COMMANDS (UPGRADE + 1 - GPIO_PINS) 103 104 /* 105 * The pin_share array maps to the highest pin used for each of the 10 106 * GPIO mode bit settings. 107 */ 108 #if defined(SLICKROCK) 109 #define SR_GPIO_MODE 0xc1c1f 110 #else 111 #define GPIO_MODE_SETTINGS 10 112 const static u_int8_t pin_share[GPIO_MODE_SETTINGS] = { 113 2, 6, 9, 14, 14, 16, 21, 23, 39, 51 114 }; 115 #endif 116 117 #define DEBOUNCE_TIME 150 /* Milliseconds */ 118 119 #if defined(TABLEROCK) || defined(SPOT2) || defined(PUCK) || defined(MOAB) 120 121 static const u_int32_t debounce_pin[DEBOUNCED_PINS] = { 122 WPS_BUTTON, 123 POWER_OFF_BUTTON, 124 DOCK_SENSE, 125 IN_5V, 126 LAN_WAN_SW 127 }; 128 static struct timeval debounce_time[DEBOUNCED_PINS]; 129 130 /* LED defines for display during boot */ 131 static const char led_array1[] = { 132 LED_BATT_7, 133 LED_BATT_8, 134 LED_BATT_9, 135 LED_BATT_10, 136 LED_SS_11, 137 LED_SS_12, 138 LED_SS_13, 139 LED_SS_14 140 }; 141 142 #define SET_SS_LED_REG RA_PIO_24_39_SET_BIT 143 #define CLEAR_SS_LED_REG RA_PIO_24_39_CLR_BIT 144 #define SS_OFFSET 24 145 #define BOOT_LED_TIMING 3000 146 147 #endif /* TABLEROCK || SPOT2 || PUCK || MOAB */ 148 149 #if defined(PEBBLES500) || defined (PEBBLES35) 150 151 static const u_int32_t debounce_pin[DEBOUNCED_PINS] = { 152 WPS_BUTTON, 153 SOFT_RST_IN_BUTTON, 154 CURRENT_LIMIT_FLAG1_3_3v, 155 CURRENT_LIMIT_FLAG_USB1, 156 CURRENT_LIMIT_FLAG1_1_5v, 157 EXCARD_ATTACH 158 }; 159 static struct timeval debounce_time[DEBOUNCED_PINS]; 160 161 /* LED defines for display during boot */ 162 #if defined(PEBBLES500) 163 static const char led_array1[] = { 164 LED_SS_13, 165 LED_SS_12, 166 LED_SS_11, 167 LED_SS_10 168 }; 169 #else 170 static const char led_array1[] = {}; 171 #endif 172 173 #define SET_SS_LED_REG RA_PIO_40_51_SET_BIT 174 #define CLEAR_SS_LED_REG RA_PIO_40_51_CLR_BIT 175 #define SS_OFFSET 40 176 #define BOOT_LED_TIMING 5500 177 178 #endif /* PEBBLES500 || PEBBLES35 */ 179 180 181 #if defined(SLICKROCK) 182 183 static const u_int32_t debounce_pin[DEBOUNCED_PINS] = { 184 WPS_BUTTON, 185 SOFT_RST_IN_BUTTON, 186 SS_BUTTON, 187 CURRENT_LIMIT_FLAG_USB1, 188 CURRENT_LIMIT_FLAG_USB2, 189 CURRENT_LIMIT_FLAG_USB3, 190 CURRENT_LIMIT_FLAG_EX1, 191 CURRENT_LIMIT_FLAG_EX2, 192 WIFI_ENABLE 193 }; 194 static struct timeval debounce_time[DEBOUNCED_PINS]; 195 196 /* LED defines for display during boot */ 197 static const char led_array1[] = { 198 LED_SS_13, 199 LED_SS_12, 200 LED_SS_11, 201 LED_SS_10 202 }; 203 204 #define SET_SS_LED_REG RA_PIO_40_51_SET_BIT 205 #define CLEAR_SS_LED_REG RA_PIO_40_51_CLR_BIT 206 #define SS_OFFSET 40 207 #define BOOT_LED_TIMING 3250 208 209 #endif /* SLICKROCK */ 210 211 #ifndef DEBOUNCED_PINS 212 static const u_int32_t debounce_pin[] = {}; 213 static struct timeval debounce_time[] = {}; 214 #endif 215 #ifndef BOOT_LED_TIMING 216 static const char led_array1[] = {}; 217 #endif 218 219 #define RA_GPIO_PIN_INIT(sc, var, pin, ptp, regname) \ 220 do { \ 221 const u_int _reg_bit = 1 << (pin - ptp->pin_reg_base); \ 222 const u_int _mask_bit = 1 << (pin - ptp->pin_mask_base);\ 223 var = gp_read(sc, ptp->regname.reg); \ 224 if ((ptp->regname.mask & _mask_bit) != 0) { \ 225 var |= _reg_bit; \ 226 } else { \ 227 var &= ~_reg_bit; \ 228 } \ 229 gp_write(sc, ptp->regname.reg, var); \ 230 } while (0) 231 232 #define RA_GPIO_PIN_INIT_DIR(sc, var, pin, ptp) \ 233 do { \ 234 const u_int _reg_bit = 1 << (pin - ptp->pin_reg_base); \ 235 const u_int _mask_bit = 1 << (pin - ptp->pin_mask_base);\ 236 var = gp_read(sc, ptp->pin_dir.reg); \ 237 if ((ptp->pin_dir.mask & _mask_bit) != 0) { \ 238 var |= _reg_bit; \ 239 sc->sc_pins[pin].pin_flags = GPIO_PIN_OUTPUT; \ 240 } else { \ 241 var &= ~_reg_bit; \ 242 sc->sc_pins[pin].pin_flags = GPIO_PIN_INPUT; \ 243 } \ 244 gp_write(sc, ptp->pin_dir.reg, var); \ 245 } while (0) 246 247 248 249 typedef struct ra_gpio_softc { 250 device_t sc_dev; 251 struct gpio_chipset_tag sc_gc; 252 gpio_pin_t sc_pins[GPIO_PINS + SPECIAL_COMMANDS]; 253 254 bus_space_tag_t sc_memt; /* bus space tag */ 255 256 bus_space_handle_t sc_sy_memh; /* Sysctl bus space handle */ 257 int sc_sy_size; /* size of Sysctl register space */ 258 259 bus_space_handle_t sc_gp_memh; /* PIO bus space handle */ 260 int sc_gp_size; /* size of PIO register space */ 261 262 void *sc_ih; /* interrupt handle */ 263 void *sc_si; /* softintr handle */ 264 265 struct callout sc_tick_callout; /* For debouncing inputs */ 266 267 /* 268 * These track gpio pins that have interrupted 269 */ 270 uint32_t sc_intr_status00_23; 271 uint32_t sc_intr_status24_39; 272 uint32_t sc_intr_status40_51; 273 uint32_t sc_intr_status72_95; 274 275 } ra_gpio_softc_t; 276 277 static int ra_gpio_match(device_t, cfdata_t , void *); 278 static void ra_gpio_attach(device_t, device_t, void *); 279 #ifdef NOTYET 280 static int ra_gpio_open(void *, device_t); 281 static int ra_gpio_close(void *, device_t); 282 #endif 283 static void ra_gpio_pin_init(ra_gpio_softc_t *, int); 284 static void ra_gpio_pin_ctl(void *, int, int); 285 286 static int ra_gpio_intr(void *); 287 static void ra_gpio_softintr(void *); 288 static void ra_gpio_debounce_process(void *); 289 static void ra_gpio_debounce_setup(ra_gpio_softc_t *); 290 291 static void disable_gpio_interrupt(ra_gpio_softc_t *, int); 292 static void enable_gpio_interrupt(ra_gpio_softc_t *, int); 293 294 static void gpio_reset_registers(ra_gpio_softc_t *); 295 #if 0 296 static void gpio_register_dump(ra_gpio_softc_t *); 297 #endif 298 299 typedef struct pin_reg { 300 u_int mask; 301 u_int reg; 302 } pin_reg_t; 303 304 typedef struct pin_tab { 305 int pin_reg_base; 306 int pin_reg_limit; 307 int pin_mask_base; 308 u_int pin_enabled; 309 u_int pin_input; 310 u_int pin_output_clr; 311 u_int pin_output_set; 312 pin_reg_t pin_dir; 313 pin_reg_t pin_rise; 314 pin_reg_t pin_fall; 315 pin_reg_t pin_pol; 316 } pin_tab_t; 317 318 /* 319 * use pin_tab[] in conjunction with pin_tab_index[] 320 * to look up register offsets, masks, etc. for a given GPIO pin, 321 * instead of lots of if/then/else test & branching 322 */ 323 static const pin_tab_t pin_tab[] = { 324 { 325 0, 24, 0, GPIO_PIN_MASK, 326 RA_PIO_00_23_DATA, 327 RA_PIO_00_23_CLR_BIT, 328 RA_PIO_00_23_SET_BIT, 329 { GPIO_OUTPUT_PIN_MASK, RA_PIO_00_23_DIR, }, 330 { GPIO_INT_PIN_MASK, RA_PIO_00_23_INT_RISE_EN, }, 331 { GPIO_INT_FEDGE_PIN_MASK, RA_PIO_00_23_INT_RISE_EN, }, 332 { GPIO_POL_MASK, RA_PIO_00_23_POLARITY, }, 333 }, 334 { 335 24, 40, 24, GPIO_PIN_MASK_24_51, 336 RA_PIO_24_39_DATA, 337 RA_PIO_24_39_CLR_BIT, 338 RA_PIO_24_39_SET_BIT, 339 { GPIO_OUTPUT_PIN_MASK_24_51, RA_PIO_24_39_DIR, }, 340 { GPIO_INT_PIN_MASK_24_51, RA_PIO_24_39_INT_RISE_EN, }, 341 { GPIO_INT_FEDGE_PIN_MASK_24_51, RA_PIO_24_39_INT_FALL_EN, }, 342 { GPIO_POL_MASK_24_51, RA_PIO_24_39_POLARITY, }, 343 }, 344 { 345 40, 52, 24, GPIO_PIN_MASK_24_51, 346 RA_PIO_40_51_DATA, 347 RA_PIO_40_51_CLR_BIT, 348 RA_PIO_40_51_SET_BIT, 349 { GPIO_OUTPUT_PIN_MASK_24_51, RA_PIO_40_51_DIR, }, 350 { GPIO_INT_PIN_MASK_24_51, RA_PIO_40_51_INT_RISE_EN, }, 351 { GPIO_INT_FEDGE_PIN_MASK_24_51, RA_PIO_40_51_INT_FALL_EN, }, 352 { GPIO_POL_MASK_24_51, RA_PIO_40_51_POLARITY, }, 353 }, 354 #if defined(SLICKROCK) 355 { 356 72, 96, 72, GPIO_PIN_MASK_72_95, 357 RA_PIO_72_95_DATA, 358 RA_PIO_72_95_CLR_BIT, 359 RA_PIO_72_95_SET_BIT, 360 { GPIO_OUTPUT_PIN_MASK_72_95, RA_PIO_72_95_DIR, }, 361 { GPIO_INT_PIN_MASK_72_95, RA_PIO_72_95_INT_RISE_EN, }, 362 { GPIO_INT_FEDGE_PIN_MASK_72_95, RA_PIO_72_95_INT_FALL_EN, }, 363 { GPIO_POL_MASK_72_95, RA_PIO_72_95_POLARITY, }, 364 }, 365 #endif 366 }; 367 368 /* 369 * use pin_tab_index[] to determine index in pin_tab[] 370 * for a given pin. -1 means there is no pin there. 371 */ 372 static const int pin_tab_index[GPIO_PINS] = { 373 /* 0 1 2 3 4 5 6 7 8 9 */ 374 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 375 /* 10 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 376 /* 20 */ 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 377 /* 30 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 378 /* 40 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 379 /* 50 */ 2, 2, 380 #if defined(SLICKROCK) 381 /* 50 */ -1, -1, -1, -1, -1, -1, -1, -1, 382 /* 60 */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 383 /* 70 */ -1, -1, 384 /* 72 */ 3, 3, 3, 3, 3, 3, 3, 3, 385 /* 80 */ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 386 /* 90 */ 3, 3, 3, 3, 3, 3 387 #endif 388 }; 389 390 CFATTACH_DECL_NEW(rgpio, sizeof(struct ra_gpio_softc), ra_gpio_match, 391 ra_gpio_attach, NULL, NULL); 392 393 /* 394 * Event handler calls and structures 395 */ 396 static int gpio_event_app_user_attach(struct knote *); 397 static void gpio_event_app_user_detach(struct knote *); 398 static int gpio_event_app_user_event(struct knote *, long); 399 400 static struct klist knotes; 401 static int app_filter_id; 402 static struct filterops app_fops = { 403 0, 404 gpio_event_app_user_attach, 405 gpio_event_app_user_detach, 406 gpio_event_app_user_event 407 }; 408 static struct callout led_tick_callout; 409 static int gpio_driver_blink_leds = 1; 410 411 static inline uint32_t 412 sy_read(ra_gpio_softc_t *sc, bus_size_t off) 413 { 414 KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n", 415 __func__, off); 416 return bus_space_read_4(sc->sc_memt, sc->sc_sy_memh, off); 417 } 418 419 static inline void 420 sy_write(ra_gpio_softc_t *sc, bus_size_t off, uint32_t val) 421 { 422 KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n", 423 __func__, off); 424 bus_space_write_4(sc->sc_memt, sc->sc_sy_memh, off, val); 425 } 426 427 static inline uint32_t 428 gp_read(ra_gpio_softc_t *sc, bus_size_t off) 429 { 430 KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n", 431 __func__, off); 432 return bus_space_read_4(sc->sc_memt, sc->sc_gp_memh, off); 433 } 434 435 static inline void 436 gp_write(ra_gpio_softc_t *sc, bus_size_t off, uint32_t val) 437 { 438 KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n", 439 __func__, off); 440 bus_space_write_4(sc->sc_memt, sc->sc_gp_memh, off, val); 441 } 442 443 /* 444 * Basic debug function, dump all PIO registers 445 */ 446 #if 0 447 static void 448 gpio_register_dump(ra_gpio_softc_t *sc) 449 { 450 for (int i=0; i < 0xb0; i+=4) 451 RALINK_DEBUG(RALINK_DEBUG_INFO, "Reg: 0x%x, Value: 0x%x\n", 452 (RA_PIO_BASE + i), gp_read(sc, i)); 453 } 454 #endif 455 456 static void 457 gpio_reset_registers(ra_gpio_softc_t *sc) 458 { 459 #if 0 460 for (int i=0; i < 0x88; i+=4) 461 gp_write(sc, i, 0); 462 #endif 463 } 464 465 466 static int 467 ra_gpio_match(device_t parent, cfdata_t cf, void *aux) 468 { 469 RALINK_DEBUG_FUNC_ENTRY(); 470 471 return 1; 472 } 473 474 static void 475 ra_gpio_attach(device_t parent, device_t self, void *aux) 476 { 477 478 struct gpiobus_attach_args gba; 479 ra_gpio_softc_t * const sc = device_private(self); 480 const struct mainbus_attach_args *ma = aux; 481 int error; 482 483 aprint_naive(": Ralink GPIO controller\n"); 484 aprint_normal(": Ralink GPIO controller\n"); 485 486 sc->sc_dev = self; 487 sc->sc_memt = ma->ma_memt; 488 sc->sc_sy_size = 0x10000; 489 sc->sc_gp_size = 0x1000; 490 491 /* 492 * map the registers 493 * 494 * we map the Sysctl, and PIO registers seperately so we can use the 495 * defined register offsets sanely; just use the correct corresponding 496 * bus_space_handle 497 */ 498 499 if ((error = bus_space_map(sc->sc_memt, RA_SYSCTL_BASE, 500 sc->sc_sy_size, 0, &sc->sc_sy_memh)) != 0) { 501 aprint_error_dev(sc->sc_dev, 502 "unable to map Sysctl registers, error=%d\n", error); 503 goto fail_0; 504 } 505 506 if ((error = bus_space_map(sc->sc_memt, RA_PIO_BASE, 507 sc->sc_gp_size, 0, &sc->sc_gp_memh)) != 0) { 508 aprint_error_dev(sc->sc_dev, 509 "unable to map PIO registers, error=%d\n", error); 510 goto fail_1; 511 } 512 513 /* Reset some registers */ 514 gp_write(sc, RA_PIO_00_23_INT, 0xffffff); 515 gp_write(sc, RA_PIO_00_23_EDGE_INT, 0xffffff); 516 gp_write(sc, RA_PIO_24_39_INT, 0xffff); 517 gp_write(sc, RA_PIO_24_39_EDGE_INT, 0xffff); 518 gp_write(sc, RA_PIO_40_51_INT, 0xfff); 519 gp_write(sc, RA_PIO_40_51_EDGE_INT, 0xfff); 520 gp_write(sc, RA_PIO_00_23_POLARITY, 0); 521 #if defined(SLICKROCK) 522 gp_write(sc, RA_PIO_72_95_INT, 0xffffff); 523 gp_write(sc, RA_PIO_72_95_EDGE_INT, 0xffffff); 524 #endif 525 526 /* Set up for interrupt handling, low priority interrupt queue */ 527 sc->sc_ih = ra_intr_establish(RA_IRQ_PIO, 528 ra_gpio_intr, sc, 0); 529 if (sc->sc_ih == NULL) { 530 RALINK_DEBUG(RALINK_DEBUG_ERROR, 531 "%s: unable to establish interrupt\n", 532 device_xname(sc->sc_dev)); 533 goto fail_2; 534 } 535 536 /* Soft int setup */ 537 sc->sc_si = softint_establish(SOFTINT_BIO, ra_gpio_softintr, sc); 538 if (sc->sc_si == NULL) { 539 ra_intr_disestablish(sc->sc_ih); 540 RALINK_DEBUG(RALINK_DEBUG_ERROR, 541 "%s: unable to establish soft interrupt\n", 542 device_xname(sc->sc_dev)); 543 goto fail_3; 544 } 545 546 SLIST_INIT(&knotes); 547 if (kfilter_register("CP_GPIO_EVENT", &app_fops, &app_filter_id) != 0) { 548 RALINK_DEBUG(RALINK_DEBUG_ERROR, 549 "%s: kfilter_register for CP_GPIO_EVENT failed\n", 550 __func__); 551 goto fail_4; 552 } 553 554 sc->sc_gc.gp_cookie = sc; 555 sc->sc_gc.gp_pin_read = ra_gpio_pin_read; 556 sc->sc_gc.gp_pin_write = ra_gpio_pin_write; 557 sc->sc_gc.gp_pin_ctl = ra_gpio_pin_ctl; 558 559 #if 0 560 gpio_register_dump(sc); 561 #endif 562 gpio_reset_registers(sc); 563 564 /* Initialize the GPIO pins */ 565 for (int pin=0; pin < GPIO_PINS; pin++) 566 ra_gpio_pin_init(sc, pin); 567 568 #if 0 569 /* debug check */ 570 KASSERT((sy_read(sc, RA_SYSCTL_GPIOMODE) == 0x31c) != 0); 571 RALINK_DEBUG(RALINK_DEBUG_INFO, "SYSCTL_GPIOMODE = 0x%x\n", 572 sy_read(sc, RA_SYSCTL_GPIOMODE)); 573 #endif 574 575 /* 576 * Some simple board setup actions: 577 * Check if we're attached to the dock. If so, enable dock power. 578 * BIG NOTE: Dock power is dependent on USB5V_EN! 579 */ 580 #if defined(PEBBLES500) || defined (PEBBLES35) 581 RALINK_DEBUG(RALINK_DEBUG_INFO, "Enabling USB power\n"); 582 ra_gpio_pin_write(sc, VBUS_EN, 1); 583 ra_gpio_pin_write(sc, POWER_EN_USB, 1); 584 #if defined(PEBBLES500) 585 /* 586 * Is an express card attached? Enable power if it is 587 * or it isn't 588 */ 589 #if 0 590 if (ra_gpio_pin_read(sc, EXCARD_ATTACH) == 0) { 591 #endif 592 ra_gpio_pin_write(sc, POWER_EN_EXCARD1_3_3v, 1); 593 ra_gpio_pin_write(sc, POWER_EN_EXCARD1_1_5v, 1); 594 #if 0 595 } 596 #endif /* 0 */ 597 #endif /* PEBBLES500 */ 598 #endif /* PEBBLES500 || PEBBLES35 */ 599 600 #if defined(TABLEROCK) || defined(SPOT2) || defined(PUCK) || defined(MOAB) 601 /* CHARGER_OFF pin matches the IN_5V */ 602 if (ra_gpio_pin_read(sc, IN_5V) == 0) { 603 ra_gpio_pin_write(sc, CHARGER_OFF, 0); 604 } else { 605 ra_gpio_pin_write(sc, CHARGER_OFF, 1); 606 } 607 #endif 608 609 #if defined(SLICKROCK) 610 /* Enable all modem slots */ 611 ra_gpio_pin_write(sc, POWER_EN_USB1, 1); 612 ra_gpio_pin_write(sc, POWER_EN_USB2, 1); 613 ra_gpio_pin_write(sc, POWER_EN_USB3, 1); 614 ra_gpio_pin_write(sc, POWER_EN_EX1, 1); 615 ra_gpio_pin_write(sc, EX1_CPUSB_RST, 0); 616 ra_gpio_pin_write(sc, POWER_EN_EX2, 1); 617 ra_gpio_pin_write(sc, EX2_CPUSB_RST, 0); 618 619 /* Wake up with an overcurrent on EX1. Try to shut it down. */ 620 gp_write(sc, RA_PIO_72_95_INT, 0xffffff); 621 gp_write(sc, RA_PIO_72_95_EDGE_INT, 0xffffff); 622 #endif 623 624 sc->sc_pins[BOOT_COUNT].pin_flags = GPIO_PIN_OUTPUT; 625 sc->sc_pins[BOOT_COUNT].pin_mapped = 0; 626 sc->sc_pins[UPGRADE].pin_flags = GPIO_PIN_OUTPUT; 627 sc->sc_pins[UPGRADE].pin_mapped = 0; 628 gba.gba_gc = &sc->sc_gc; 629 gba.gba_pins = sc->sc_pins; 630 631 /* Note, > 52nd pin isn't a gpio, it is a special command */ 632 gba.gba_npins = (GPIO_PINS + SPECIAL_COMMANDS); 633 634 config_found_ia(sc->sc_dev, "gpiobus", &gba, gpiobus_print); 635 636 #if 0 637 gpio_register_dump(sc); 638 #endif 639 640 /* init our gpio debounce */ 641 callout_init(&sc->sc_tick_callout, 0); 642 callout_setfunc(&sc->sc_tick_callout, ra_gpio_debounce_process, sc); 643 644 /* LED blinking during boot */ 645 callout_init(&led_tick_callout, 0); 646 647 ra_gpio_toggle_LED(sc); 648 return; 649 650 fail_4: 651 softint_disestablish(sc->sc_si); 652 fail_3: 653 ra_intr_disestablish(sc->sc_ih); 654 fail_2: 655 bus_space_unmap(sc->sc_memt, sc->sc_gp_memh, sc->sc_sy_size); 656 fail_1: 657 bus_space_unmap(sc->sc_memt, sc->sc_sy_memh, sc->sc_sy_size); 658 fail_0: 659 return; 660 } 661 662 /* 663 * ra_gpio_pin_init - initialize the given gpio pin 664 */ 665 static void 666 ra_gpio_pin_init(ra_gpio_softc_t *sc, int pin) 667 { 668 uint32_t r; 669 670 sc->sc_pins[pin].pin_caps = 0; 671 sc->sc_pins[pin].pin_flags = 0; 672 sc->sc_pins[pin].pin_state = 0; 673 sc->sc_pins[pin].pin_mapped = 0; 674 675 /* ensure pin number is in range */ 676 KASSERT(pin < GPIO_PINS); 677 if (pin >= GPIO_PINS) 678 return; 679 680 /* if pin number is in a gap in the range, just return */ 681 const int index = pin_tab_index[pin]; 682 if (index == -1) 683 return; 684 685 /* if pin is not enabled, just return */ 686 const pin_tab_t * const ptp = &pin_tab[index]; 687 const u_int mask_bit = 1 << (pin - ptp->pin_mask_base); 688 if ((ptp->pin_enabled & mask_bit) == 0) 689 return; 690 691 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 692 GPIO_PIN_INVIN | GPIO_PIN_INVOUT; 693 sc->sc_pins[pin].pin_state = GPIO_PIN_INPUT; 694 695 #if defined(SLICKROCK) 696 r = sy_read(sc, RA_SYSCTL_GPIOMODE); 697 r |= SR_GPIO_MODE; 698 sy_write(sc, RA_SYSCTL_GPIOMODE, r); 699 #else 700 /* 701 * Set the SYSCTL_GPIOMODE register to 1 for 702 * the PIO block of any mapped GPIO 703 * (most have reset defaults of 1 already). 704 * GPIO0 doesn't have an associated MODE register. 705 */ 706 if (pin != 0) { 707 u_int gpio_mode = 0; 708 709 for (gpio_mode; gpio_mode < GPIO_MODE_SETTINGS; gpio_mode++) { 710 if (pin <= pin_share[gpio_mode]) { 711 r = sy_read(sc, RA_SYSCTL_GPIOMODE); 712 if (10 == pin) { 713 /* 714 * Special case: 715 * GPIO 10 requires GPIOMODE_UARTF0-2 716 */ 717 r |= GPIOMODE_UARTF_0_2; 718 } else { 719 /* standard case */ 720 r |= (1 << gpio_mode); 721 } 722 sy_write(sc, RA_SYSCTL_GPIOMODE, r); 723 break; 724 } 725 } 726 } 727 #endif 728 729 /* set direction */ 730 RA_GPIO_PIN_INIT_DIR(sc, r, pin, ptp); 731 732 /* rising edge interrupt */ 733 RA_GPIO_PIN_INIT(sc, r, pin, ptp, pin_rise); 734 735 /* falling edge interrupt */ 736 RA_GPIO_PIN_INIT(sc, r, pin, ptp, pin_fall); 737 738 /* polarirty */ 739 RA_GPIO_PIN_INIT(sc, r, pin, ptp, pin_pol); 740 } 741 742 /* 743 * Note: This has special hacks in it. If pseudo-pin BOOT_COUNT 744 * is requested, it is a signal check the memo register for a special key 745 * that means run Wi-Fi in no security mode. 746 */ 747 int 748 ra_gpio_pin_read(void *arg, int pin) 749 { 750 RALINK_DEBUG_FUNC_ENTRY(); 751 const ra_gpio_softc_t * const sc = arg; 752 int rv; 753 754 KASSERT(sc != NULL); 755 756 if (pin < GPIO_PINS) { 757 /* 758 * normal case: a regular GPIO pin 759 * if pin number is in a gap in the range, 760 * then warn and return 0 761 */ 762 const int index = pin_tab_index[pin]; 763 KASSERTMSG(index != -1, "%s: non-existant pin=%d\n", 764 __func__, pin); 765 if (index == -1) { 766 rv = 0; 767 } else { 768 const pin_tab_t * const ptp = &pin_tab[index]; 769 const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base); 770 const bus_size_t off = ptp->pin_input; 771 uint32_t r; 772 773 r = bus_space_read_4(sc->sc_memt, sc->sc_gp_memh, off); 774 rv = ((r & (1 << reg_bit)) != 0); 775 } 776 } else { 777 /* 778 * Special hack: a pseudo-pin used for signaling 779 */ 780 rv = 0; 781 switch(pin) { 782 case BOOT_COUNT: 783 if (1 == ra_check_memo_reg(NO_SECURITY)) 784 rv = 1; 785 break; 786 default: 787 #ifdef DIAGNOSTIC 788 aprint_normal_dev(sc->sc_dev, "%s: bad pin=%d\n", 789 __func__, pin); 790 #endif 791 break; 792 } 793 } 794 795 RALINK_DEBUG_0(RALINK_DEBUG_INFO, "pin %d, value %x\n", pin, rv); 796 return rv; 797 } 798 799 /* 800 * There are three ways to change the value of a pin. 801 * You can write to the DATA register, which will set 802 * or reset a pin. But you need to store it locally and 803 * read/mask/set it, which is potentially racy without locks. 804 * There are also SET and RESET registers, which allow you to write 805 * a value to a single pin and not affect any other pins 806 * by accident. 807 * 808 * NOTE: This has special hacks in it. If pin 52 (which does not exist) 809 * is written, it is a signal to clear the boot count register. If pin 810 * 53 is written, it is a upgrade signal to the bootloader. 811 * 812 */ 813 #define MAGIC 0x27051956 814 #define UPGRADE_MAGIC 0x27051957 815 void 816 ra_gpio_pin_write(void *arg, int pin, int value) 817 { 818 RALINK_DEBUG_FUNC_ENTRY(); 819 ra_gpio_softc_t * const sc = arg; 820 uint32_t r; 821 822 KASSERT(sc != NULL); 823 RALINK_DEBUG(RALINK_DEBUG_INFO, "pin %d, val %d\n", pin, value); 824 825 if (pin >= GPIO_PINS) { 826 /* 827 * Special hack: a pseudo-pin used for signaling 828 */ 829 switch(pin) { 830 case BOOT_COUNT: 831 /* Reset boot count */ 832 r = sy_read(sc, RA_SYSCTL_MEMO0); 833 if (r == MAGIC) 834 sy_write(sc, RA_SYSCTL_MEMO1, 0); 835 break; 836 case UPGRADE: 837 /* Set upgrade flag */ 838 sy_write(sc, RA_SYSCTL_MEMO0, UPGRADE_MAGIC); 839 sy_write(sc, RA_SYSCTL_MEMO1, UPGRADE_MAGIC); 840 break; 841 default: 842 #ifdef DIAGNOSTIC 843 aprint_normal_dev(sc->sc_dev, "%s: bad pin=%d\n", 844 __func__, pin); 845 #endif 846 } 847 return; 848 } 849 850 /* 851 * normal case: a regular GPIO pin 852 * if pin number is in a gap in the range, 853 * then warn and return 854 */ 855 const int index = pin_tab_index[pin]; 856 KASSERTMSG(index != -1, "%s: non-existant pin=%d\n", __func__, pin); 857 if (index == -1) 858 return; 859 860 const pin_tab_t * const ptp = &pin_tab[index]; 861 const u_int mask_bit = 1 << (pin - ptp->pin_mask_base); 862 const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base); 863 const bus_size_t off = (value == 0) ? 864 ptp->pin_output_clr : ptp->pin_output_set; 865 866 if ((ptp->pin_dir.mask & mask_bit) == 0) { 867 #ifdef DIAGNOSTIC 868 aprint_normal_dev(sc->sc_dev, 869 "%s: Writing non-output pin: %d\n", __func__, pin); 870 #endif 871 return; 872 } 873 874 bus_space_write_4(sc->sc_memt, sc->sc_gp_memh, off, reg_bit); 875 } 876 877 static void 878 ra_gpio_pin_ctl(void *arg, int pin, int flags) 879 { 880 RALINK_DEBUG_FUNC_ENTRY(); 881 882 /* 883 * For now, this lets us know that user-space is using the GPIOs 884 * and the kernel shouldn't blink LEDs any more 885 */ 886 gpio_driver_blink_leds = 0; 887 } 888 889 /* 890 * Check the three interrupt registers and ack them 891 * immediately. If a button is pushed, use the 892 * handle_key_press call to debounce it. Otherwise, 893 * call the softint handler to send any necessary 894 * events. 895 */ 896 static int 897 ra_gpio_intr(void *arg) 898 { 899 RALINK_DEBUG_FUNC_ENTRY(); 900 ra_gpio_softc_t * const sc = arg; 901 902 #if 0 903 /* Read the 3 interrupt registers */ 904 if (sc->sc_intr_status00_23 || sc->sc_intr_status24_39 || 905 sc->sc_intr_status40_51) { 906 printf("\n0-23 %x, 24-39 %x, 40_51 %x\n", 907 sc->sc_intr_status00_23, 908 sc->sc_ntr_status24_39, 909 sc->sc_ntr_status40_51); 910 } 911 #endif 912 913 sc->sc_intr_status00_23 |= gp_read(sc, RA_PIO_00_23_INT); 914 sc->sc_intr_status24_39 |= gp_read(sc, RA_PIO_24_39_INT); 915 sc->sc_intr_status40_51 |= gp_read(sc, RA_PIO_40_51_INT); 916 #if defined(SLICKROCK) 917 sc->sc_intr_status72_95 |= gp_read(sc, RA_PIO_72_95_INT); 918 #endif 919 920 #if 0 921 /* Trivial error checking, some interrupt had to have fired */ 922 KASSERT((sc->sc_intr_status00_23 | sc->sc_intr_status24_39 | 923 sc->sc_intr_status40_51) != 0); 924 #endif 925 926 /* Debounce interrupt */ 927 ra_gpio_debounce_setup(sc); 928 929 /* 930 * and ACK the interrupt. 931 * OR the values in case the softint handler hasn't 932 * been scheduled and handled any previous int 933 * I don't know if resetting the EDGE register is 934 * necessary, but the Ralink Linux driver does it. 935 */ 936 gp_write(sc, RA_PIO_00_23_INT, sc->sc_intr_status00_23); 937 gp_write(sc, RA_PIO_00_23_EDGE_INT, sc->sc_intr_status00_23); 938 gp_write(sc, RA_PIO_24_39_INT, sc->sc_intr_status24_39); 939 gp_write(sc, RA_PIO_24_39_EDGE_INT, sc->sc_intr_status24_39); 940 gp_write(sc, RA_PIO_40_51_INT, sc->sc_intr_status40_51); 941 gp_write(sc, RA_PIO_40_51_EDGE_INT, sc->sc_intr_status40_51); 942 #if defined(SLICKROCK) 943 gp_write(sc, RA_PIO_72_95_INT, sc->sc_intr_status72_95); 944 gp_write(sc, RA_PIO_72_95_EDGE_INT, sc->sc_intr_status72_95); 945 #endif 946 947 /* Reset until next time */ 948 sc->sc_intr_status00_23 = 0; 949 sc->sc_intr_status24_39 = 0; 950 sc->sc_intr_status40_51 = 0; 951 sc->sc_intr_status72_95 = 0; 952 953 return 1; 954 } 955 956 /* 957 * Handle key debouncing for the given pin 958 */ 959 static bool 960 ra_gpio_debounce_pin(ra_gpio_softc_t *sc, struct timeval *tv, u_int pin) 961 { 962 RALINK_DEBUG_FUNC_ENTRY(); 963 964 /* 965 * If a pin has a time set, it is waiting for 966 * a debounce period. Check if it is ready 967 * to send its event and clean up. Otherwise, 968 * reschedule 10mSec and try again later. 969 */ 970 if (0 != debounce_time[pin].tv_sec) { 971 if (timercmp(tv, &debounce_time[pin], <)) { 972 /* 973 * Haven't hit debounce time, 974 * need to reschedule 975 */ 976 return true; 977 } 978 #if defined(SLICKROCK) 979 switch (debounce_pin[pin]) { 980 case SOFT_RST_IN_BUTTON: 981 KNOTE(&knotes, RESET_BUTTON_EVT); 982 break; 983 984 case SS_BUTTON: 985 KNOTE(&knotes, SS_BUTTON_EVT); 986 break; 987 988 case WPS_BUTTON: 989 KNOTE(&knotes, WPS_BUTTON_EVT); 990 break; 991 992 case WIFI_ENABLE: 993 KNOTE(&knotes, WIFI_ENABLE_EVT); 994 break; 995 996 /* 997 * These events are in case of overcurrent 998 * on USB/ExpressCard devices. 999 * If we receive an overcurrent signal, 1000 * turn off power to the device and 1001 * let the USB driver know. 1002 */ 1003 case CURRENT_LIMIT_FLAG_USB1: 1004 ra_gpio_pin_write(sc, POWER_EN_USB1, 0); 1005 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1006 #if 0 1007 cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB1); 1008 #endif 1009 printf("\nUSB1 current limit received!\n"); 1010 break; 1011 1012 case CURRENT_LIMIT_FLAG_USB2: 1013 ra_gpio_pin_write(sc, POWER_EN_USB2, 0); 1014 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1015 #if 0 1016 cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB2); 1017 #endif 1018 printf("\nUSB2 current limit received!\n"); 1019 break; 1020 1021 case CURRENT_LIMIT_FLAG_USB3: 1022 ra_gpio_pin_write(sc, POWER_EN_USB3, 0); 1023 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1024 #if 0 1025 cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB3); 1026 #endif 1027 printf("\nUSB3 current limit received!\n"); 1028 break; 1029 1030 case CURRENT_LIMIT_FLAG_EX1: 1031 ra_gpio_pin_write(sc, POWER_EN_EX1, 0); 1032 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1033 #if 0 1034 cpusb_overcurrent_occurred(debounce_pin[pin]); 1035 #endif 1036 printf("\nExpressCard1 current limit received!\n"); 1037 break; 1038 1039 case CURRENT_LIMIT_FLAG_EX2: 1040 ra_gpio_pin_write(sc, POWER_EN_EX2, 0); 1041 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1042 #if 0 1043 cpusb_overcurrent_occurred(debounce_pin[pin]); 1044 #endif 1045 printf("\nExpressCard2 current limit received!\n"); 1046 break; 1047 1048 default: 1049 printf("\nUnknown debounce pin %d received.\n", 1050 debounce_pin[pin]); 1051 } 1052 #endif/* SLICKROCK */ 1053 #if defined(PEBBLES500) || defined(PEBBLES35) 1054 switch (debounce_pin[pin]) { 1055 case SOFT_RST_IN_BUTTON: 1056 KNOTE(&knotes, RESET_BUTTON_EVT); 1057 break; 1058 1059 case WPS_BUTTON: 1060 KNOTE(&knotes, WPS_BUTTON_EVT); 1061 break; 1062 1063 case EXCARD_ATTACH: 1064 KNOTE(&knotes, EXCARD_ATTACH_EVT); 1065 break; 1066 1067 /* 1068 * These events are in case of overcurrent 1069 * on USB/ExpressCard devices. 1070 * If we receive an overcurrent signal, 1071 * turn off power to the device and 1072 * let the USB driver know. 1073 */ 1074 case CURRENT_LIMIT_FLAG_USB1: 1075 ra_gpio_pin_write(sc, POWER_EN_USB, 0); 1076 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1077 cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB1); 1078 printf("\nUSB current limit received!\n"); 1079 break; 1080 1081 /* 1082 * If either voltage is over current, 1083 * turn off all ExpressCard power 1084 */ 1085 case CURRENT_LIMIT_FLAG1_3_3v: 1086 case CURRENT_LIMIT_FLAG1_1_5v: 1087 ra_gpio_pin_write(sc, POWER_EN_EXCARD1_3_3v, 0); 1088 ra_gpio_pin_write(sc, POWER_EN_EXCARD1_1_5v, 0); 1089 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1090 cpusb_overcurrent_occurred(debounce_pin[pin]); 1091 printf("\nExpressCard current limit received!\n"); 1092 break; 1093 1094 default: 1095 printf("\nUnknown debounce pin received.\n"); 1096 } 1097 #endif/* PEBBLES500 || PEBBLES35 */ 1098 #if defined(TABLEROCK) || defined(SPOT2) || defined(PUCK) || defined(MOAB) 1099 if (POWER_OFF_BUTTON == debounce_pin[pin]) { 1100 KNOTE(&knotes, POWER_BUTTON_EVT); 1101 } 1102 if (LAN_WAN_SW == debounce_pin[pin]) { 1103 KNOTE(&knotes, LAN_WAN_SW_EVT); 1104 } 1105 if (DOCK_SENSE == debounce_pin[pin]) { 1106 KNOTE(&knotes, DOCK_SENSE_EVT); 1107 } 1108 if (WPS_BUTTON == debounce_pin[pin]) { 1109 KNOTE(&knotes, WPS_BUTTON_EVT); 1110 } 1111 if (IN_5V == debounce_pin[pin]) { 1112 /* Set the charger to match the in 5V line */ 1113 if (ra_gpio_pin_read(sc, IN_5V) == 0) { 1114 ra_gpio_pin_write(sc, CHARGER_OFF, 0); 1115 } else { 1116 ra_gpio_pin_write(sc, CHARGER_OFF, 1); 1117 } 1118 KNOTE(&knotes, IN_5V_EVT); 1119 } 1120 #endif/* TABLEROCK || SPOT2 || PUCK || MOAB */ 1121 /* Re-enable interrupt and reset time */ 1122 enable_gpio_interrupt(sc, debounce_pin[pin]); 1123 debounce_time[pin].tv_sec = 0; 1124 1125 } 1126 return false; 1127 } 1128 1129 /* 1130 * Handle key debouncing. 1131 * Re-enable the key interrupt after DEBOUNCE_TIME 1132 */ 1133 static void 1134 ra_gpio_debounce_process(void *arg) 1135 { 1136 RALINK_DEBUG_FUNC_ENTRY(); 1137 ra_gpio_softc_t * const sc = arg; 1138 bool reschedule = false; 1139 struct timeval now; 1140 1141 microtime(&now); 1142 1143 for (u_int pin=0; pin < __arraycount(debounce_pin); pin++) 1144 if (ra_gpio_debounce_pin(sc, &now, pin)) 1145 reschedule = true; 1146 1147 if (reschedule) 1148 callout_schedule(&sc->sc_tick_callout, MS_TO_HZ(10)); 1149 } 1150 1151 /* 1152 * Handle key and other interrupt debouncing. 1153 */ 1154 static void 1155 ra_gpio_debounce_setup(ra_gpio_softc_t *sc) 1156 { 1157 RALINK_DEBUG_FUNC_ENTRY(); 1158 u_int32_t pin; 1159 struct timeval now; 1160 struct timeval wait = { 1161 .tv_sec = 0, 1162 .tv_usec = (DEBOUNCE_TIME * 1000) 1163 }; 1164 1165 /* 1166 * The 371/372 series are a bit more complex. They have 1167 * interrupt sources across all three interrupt 1168 * registers. 1169 */ 1170 for (int i=0; i < __arraycount(debounce_pin); i++) { 1171 u_int32_t *intr_status; 1172 int offset; 1173 if (debounce_pin[i] < 24) { 1174 intr_status = &sc->sc_intr_status00_23; 1175 offset = 0; 1176 } else if (debounce_pin[i] < 40) { 1177 intr_status = &sc->sc_intr_status24_39; 1178 offset = 24; 1179 } else if (debounce_pin[i] < 71) { 1180 intr_status = &sc->sc_intr_status40_51; 1181 offset = 40; 1182 } else { 1183 intr_status = &sc->sc_intr_status72_95; 1184 offset = 72; 1185 } 1186 if (*intr_status & (1 << (debounce_pin[i] - offset))) { 1187 pin = debounce_pin[i]; 1188 1189 #ifdef ENABLE_RALINK_DEBUG_INFO 1190 if (ra_gpio_pin_read(sc, pin)) { 1191 RALINK_DEBUG(RALINK_DEBUG_INFO, 1192 "%s() button 0x%x, pin %d released\n", 1193 __func__, *intr_status, pin); 1194 } else { 1195 RALINK_DEBUG(RALINK_DEBUG_INFO, 1196 "%s() button 0x%x, pin %d pressed\n", 1197 __func__, *intr_status, pin); 1198 } 1199 #endif 1200 1201 #if 0 1202 /* Mask pin that is being handled */ 1203 *intr_status &= ~((1 << (debounce_pin[i] - offset))); 1204 #endif 1205 1206 /* Handle debouncing. */ 1207 disable_gpio_interrupt(sc, pin); 1208 microtime(&now); 1209 1210 #if defined(TABLEROCK) 1211 /* 1212 * The dock's LAN_WAN switch can cause a fire of 1213 * interrupts if it sticks in the half-way position. 1214 * Ignore it for longer than other buttons. 1215 */ 1216 if (pin == LAN_WAN_SW) { 1217 wait.tv_usec *= 2; 1218 } 1219 #endif 1220 1221 timeradd(&now, &wait, &debounce_time[i]); 1222 } 1223 } 1224 1225 /* If the debounce callout hasn't been scheduled, start it up. */ 1226 if (FALSE == callout_pending(&sc->sc_tick_callout)) { 1227 callout_schedule(&sc->sc_tick_callout, MS_TO_HZ(DEBOUNCE_TIME)); 1228 } 1229 } 1230 1231 /* 1232 * Disable both rising and falling 1233 */ 1234 static void 1235 disable_gpio_interrupt(ra_gpio_softc_t *sc, int pin) 1236 { 1237 RALINK_DEBUG_FUNC_ENTRY(); 1238 const int index = pin_tab_index[pin]; 1239 KASSERTMSG(index != -1, "%s: non-existant pin=%d\n", __func__, pin); 1240 if (index == -1) 1241 return; 1242 1243 const pin_tab_t * const ptp = &pin_tab[index]; 1244 const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base); 1245 uint32_t r; 1246 1247 r = gp_read(sc, ptp->pin_rise.reg); 1248 r &= ~reg_bit; 1249 gp_write(sc, ptp->pin_rise.reg, r); 1250 1251 r = gp_read(sc, ptp->pin_fall.reg); 1252 r &= ~reg_bit; 1253 gp_write(sc, ptp->pin_fall.reg, r); 1254 } 1255 1256 /* 1257 * Restore GPIO interrupt setting 1258 */ 1259 static void 1260 enable_gpio_interrupt(ra_gpio_softc_t *sc, int pin) 1261 { 1262 const int index = pin_tab_index[pin]; 1263 KASSERTMSG(index != -1, "%s: non-existant pin=%d\n", __func__, pin); 1264 if (index == -1) 1265 return; 1266 1267 const pin_tab_t * const ptp = &pin_tab[index]; 1268 const uint32_t mask_bit = 1 << (pin - ptp->pin_mask_base); 1269 const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base); 1270 uint32_t r; 1271 1272 if (ptp->pin_rise.mask & mask_bit) { 1273 r = gp_read(sc, ptp->pin_rise.reg); 1274 r |= reg_bit; 1275 gp_write(sc, ptp->pin_rise.reg, r); 1276 } 1277 1278 if (ptp->pin_fall.mask & mask_bit) { 1279 r = gp_read(sc, ptp->pin_fall.reg); 1280 r |= reg_bit; 1281 gp_write(sc, ptp->pin_fall.reg, r); 1282 } 1283 } 1284 1285 /* 1286 * XXX this function is obsolete/unused? XXX 1287 * 1288 * Go through each of the interrupts and send the appropriate 1289 * event. 1290 */ 1291 static void 1292 ra_gpio_softintr(void *arg) 1293 { 1294 RALINK_DEBUG(RALINK_DEBUG_INFO, 1295 "gpio softintr called with 0x%x, 0x%x, 0x%x, 0x%x\n", 1296 sc->sc_intr_status00_23, sc->sc_intr_status24_39, 1297 sc->sc_intr_status40_51, sc->sc_intr_status72_95); 1298 } 1299 1300 /* 1301 * gpio_event_app_user_attach - called when knote is ADDed 1302 */ 1303 static int 1304 gpio_event_app_user_attach(struct knote *kn) 1305 { 1306 RALINK_DEBUG_0(RALINK_DEBUG_INFO, "%s() %p\n", __func__, kn); 1307 1308 if (NULL == kn) { 1309 RALINK_DEBUG(RALINK_DEBUG_ERROR, "Null kn found\n"); 1310 return 0; 1311 } 1312 1313 kn->kn_flags |= EV_CLEAR; /* automatically set */ 1314 SLIST_INSERT_HEAD(&knotes, kn, kn_selnext); 1315 1316 return 0; 1317 } 1318 1319 /* 1320 * gpio_event_app_user_detach - called when knote is DELETEd 1321 */ 1322 static void 1323 gpio_event_app_user_detach(struct knote *kn) 1324 { 1325 RALINK_DEBUG_0(RALINK_DEBUG_INFO, "%s() %p\n", __func__, kn); 1326 if (NULL == kn) { 1327 RALINK_DEBUG(RALINK_DEBUG_ERROR, "Null kn found\n"); 1328 return; 1329 } 1330 SLIST_REMOVE(&knotes, kn, knote, kn_selnext); 1331 } 1332 1333 /* 1334 * gpio_event_app_user_event - called when event is triggered 1335 */ 1336 static int 1337 gpio_event_app_user_event(struct knote *kn, long hint) 1338 { 1339 RALINK_DEBUG_0(RALINK_DEBUG_INFO, "%s() %p hint: %ld\n", __func__, kn, hint); 1340 1341 if (NULL == kn) { 1342 RALINK_DEBUG(RALINK_DEBUG_ERROR, "Null kn found\n"); 1343 return 0; 1344 } 1345 1346 if (hint != 0) { 1347 kn->kn_data = kn->kn_sdata; 1348 kn->kn_fflags |= hint; 1349 } 1350 1351 return 1; 1352 } 1353 1354 /* 1355 * Blinky light control during boot. 1356 * This marches through the SS/BATT LEDS 1357 * to give an indication something is going on. 1358 */ 1359 void 1360 ra_gpio_toggle_LED(void *arg) 1361 { 1362 RALINK_DEBUG_FUNC_ENTRY(); 1363 ra_gpio_softc_t * const sc = arg; 1364 static int led_index = 0; 1365 static int led_timing_hack = 1; 1366 1367 if ((led_timing_hack >= 6) || 1368 (0 == gpio_driver_blink_leds)) { 1369 /* We're out of boot timing, don't blink LEDs any more */ 1370 return; 1371 } 1372 1373 #if 0 1374 /* Disable lit LED */ 1375 gp_write(sc, SET_SS_LED_REG, 1376 (1 << (led_array1[led_index++] - SS_OFFSET))); 1377 #endif 1378 1379 if (led_index == (sizeof(led_array1))) { 1380 led_index = 0; 1381 for (int i=0; i < sizeof(led_array1); i++) { 1382 ra_gpio_pin_write(sc, led_array1[i], 1); 1383 } 1384 } 1385 1386 /* Light next LED */ 1387 ra_gpio_pin_write(sc, led_array1[led_index++], 0); 1388 1389 #if 0 1390 if (led_index == 4) { 1391 led_timing_hack = 1; 1392 } 1393 #endif 1394 1395 #ifdef BOOT_LED_TIMING 1396 /* Setting 3.5 second per LED */ 1397 if ((led_timing_hack) && 1398 (led_timing_hack < 6)) { 1399 led_timing_hack++; 1400 callout_reset(&led_tick_callout, MS_TO_HZ(BOOT_LED_TIMING), 1401 ra_gpio_toggle_LED, sc); 1402 } 1403 #endif 1404 } 1405