1 /* $NetBSD: pte.h,v 1.5 1997/06/21 04:10:42 mhitch Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright 1996 The Board of Trustees of The Leland Stanford 42 * Junior University. All Rights Reserved. 43 * 44 * Permission to use, copy, modify, and distribute this 45 * software and its documentation for any purpose and without 46 * fee is hereby granted, provided that the above copyright 47 * notice appear in all copies. Stanford University 48 * makes no representations about the suitability of this 49 * software for any purpose. It is provided "as is" without 50 * express or implied warranty. 51 */ 52 53 #ifndef __MIPS_PTE_H__ 54 #define __MIPS_PTE_H__ 55 56 #include <mips/mips1_pte.h> 57 #include <mips/mips3_pte.h> 58 59 #if !defined(MIPS1) && !defined(MIPS3) 60 #error Must include at least one MIPS architecture. 61 #endif 62 63 #define PG_ASID 0x000000ff /* Address space ID */ 64 65 #ifndef _LOCORE 66 #include <mips/cpu.h> 67 68 typedef union pt_entry { 69 unsigned int pt_entry; /* for copying, etc. */ 70 struct mips1_pte pt_mips1_pte; /* for getting to bits by name */ 71 struct mips3_pte pt_mips3_pte; 72 } pt_entry_t; 73 74 #define PT_ENTRY_NULL ((pt_entry_t *) 0) 75 76 /* 77 * Macros/inline functions to hide PTE format differences. 78 */ 79 80 #define mips_pg_nv_bit() (MIPS1_PG_NV) /* same on mips1 and mips3 */ 81 82 83 int pmap_is_page_ro(pmap_t, vm_offset_t, int); 84 85 86 /* MIPS1-only */ 87 #if defined(MIPS1) && !defined(MIPS3) 88 #define mips_pg_v(entry) ((entry) & MIPS1_PG_V) 89 #define mips_pg_wired(entry) ((entry) & MIPS1_PG_WIRED) 90 91 #define mips_pg_m_bit() (MIPS1_PG_M) 92 #define mips_pg_rw_bit() (MIPS1_PG_RW) /* no RW bits for mips1 */ 93 #define mips_pg_ro_bit() (MIPS1_PG_RO) 94 #define mips_pg_ropage_bit() (MIPS1_PG_RO) /* XXX not MIPS1_PG_ROPAGE? */ 95 #define mips_pg_rwpage_bit() (MIPS1_PG_RWPAGE) 96 #define mips_pg_cwpage_bit() (MIPS1_PG_CWPAGE) 97 #define mips_pg_global_bit() (MIPS1_PG_G) 98 #define mips_pg_wired_bit() (MIPS1_PG_WIRED) 99 100 #define PTE_TO_PADDR(pte) MIPS1_PTE_TO_PADDR((pte)) 101 #define PAGE_IS_RDONLY(pte, va) MIPS1_PAGE_IS_RDONLY((pte), (va)) 102 103 #define pfn_to_vad(x) mips1_pfn_to_vad((vm_offset_t)(x)) 104 #define vad_to_pfn(x) mips1_vad_to_pfn((x)) 105 #endif /* mips1 */ 106 107 108 /* MIPS3-only */ 109 #if !defined(MIPS1) && defined(MIPS3) 110 #define mips_pg_v(entry) ((entry) & MIPS3_PG_V) 111 #define mips_pg_wired(entry) ((entry) & MIPS3_PG_WIRED) 112 113 #define mips_pg_m_bit() (MIPS3_PG_M) 114 #define mips_pg_rw_bit() (MIPS3_PG_M) 115 #define mips_pg_ro_bit() (MIPS3_PG_RO) 116 #define mips_pg_ropage_bit() (MIPS3_PG_ROPAGE) 117 #define mips_pg_rwpage_bit() (MIPS3_PG_RWPAGE) 118 #define mips_pg_cwpage_bit() (MIPS3_PG_CWPAGE) 119 #define mips_pg_global_bit() (MIPS3_PG_G) 120 #define mips_pg_wired_bit() (MIPS3_PG_WIRED) 121 122 #define PTE_TO_PADDR(pte) MIPS3_PTE_TO_PADDR((pte)) 123 #define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va)) 124 125 #define pfn_to_vad(x) mips3_pfn_to_vad((vm_offset_t)(x)) 126 #define vad_to_pfn(x) mips3_vad_to_pfn((x)) 127 #endif /* mips3 */ 128 129 /* MIPS1 and MIPS3 */ 130 #if defined(MIPS1) && defined(MIPS3) 131 132 static __inline int 133 mips_pg_v(unsigned int entry), 134 mips_pg_wired(unsigned int entry), 135 PAGE_IS_RDONLY(unsigned int pte, vm_offset_t va); 136 137 static __inline unsigned int 138 mips_pg_wired_bit(void), mips_pg_m_bit(void), 139 mips_pg_ro_bit(void), mips_pg_rw_bit(void), 140 mips_pg_ropage_bit(void), 141 mips_pg_cwpage_bit(void), 142 mips_pg_rwpage_bit(void), 143 mips_pg_global_bit(void), 144 PTE_TO_PADDR(unsigned int entry); 145 146 static __inline vm_offset_t pfn_to_vad(unsigned int x); 147 static __inline int vad_to_pfn(vm_offset_t x); 148 149 150 static __inline int 151 mips_pg_v(entry) 152 unsigned int entry; 153 { 154 if (CPUISMIPS3) 155 return (entry & MIPS3_PG_V); 156 return (entry & MIPS1_PG_V); 157 } 158 159 static __inline int 160 mips_pg_wired(entry) 161 unsigned int entry; 162 { 163 if (CPUISMIPS3) 164 return (entry & MIPS3_PG_WIRED); 165 return (entry & MIPS1_PG_WIRED); 166 } 167 168 static __inline unsigned int 169 mips_pg_m_bit() 170 { 171 if (CPUISMIPS3) 172 return (MIPS3_PG_M); 173 return (MIPS1_PG_M); 174 } 175 176 static __inline unsigned int 177 mips_pg_ro_bit() 178 { 179 if (CPUISMIPS3) 180 return (MIPS3_PG_RO); 181 return (MIPS1_PG_RO); 182 } 183 184 static __inline unsigned int 185 mips_pg_rw_bit() 186 { 187 if (CPUISMIPS3) 188 return (MIPS3_PG_M); 189 return (MIPS1_PG_RW); 190 } 191 192 static __inline unsigned int 193 mips_pg_ropage_bit() 194 { 195 if (CPUISMIPS3) 196 return (MIPS3_PG_ROPAGE); 197 return (MIPS1_PG_RO); 198 } 199 200 static __inline unsigned int 201 mips_pg_rwpage_bit() 202 { 203 if (CPUISMIPS3) 204 return (MIPS3_PG_RWPAGE); 205 return (MIPS1_PG_RWPAGE); 206 } 207 208 static __inline unsigned int 209 mips_pg_cwpage_bit() 210 { 211 if (CPUISMIPS3) 212 return (MIPS3_PG_CWPAGE); 213 return (MIPS1_PG_CWPAGE); 214 } 215 216 217 static __inline unsigned int 218 mips_pg_global_bit() 219 { 220 if (CPUISMIPS3) 221 return (MIPS3_PG_G); 222 return (MIPS1_PG_G); 223 } 224 225 static __inline unsigned int 226 mips_pg_wired_bit() 227 { 228 if (CPUISMIPS3) 229 return (MIPS3_PG_WIRED); 230 return (MIPS1_PG_WIRED); 231 } 232 233 static __inline unsigned int 234 PTE_TO_PADDR(pte) 235 unsigned int pte; 236 { 237 if (CPUISMIPS3) 238 return (MIPS3_PTE_TO_PADDR(pte)); 239 return (MIPS1_PTE_TO_PADDR(pte)); 240 } 241 242 static __inline int 243 PAGE_IS_RDONLY(pte, va) 244 unsigned int pte; 245 vm_offset_t va; 246 { 247 if (CPUISMIPS3) 248 return (MIPS3_PAGE_IS_RDONLY(pte, va)); 249 return (MIPS1_PAGE_IS_RDONLY(pte, va)); 250 } 251 252 static __inline vm_offset_t 253 pfn_to_vad(x) 254 unsigned int x; 255 { 256 if (CPUISMIPS3) 257 return (mips3_pfn_to_vad(x)); 258 return (mips1_pfn_to_vad(x)); 259 } 260 261 static __inline int 262 vad_to_pfn(x) 263 vm_offset_t x; 264 { 265 if (CPUISMIPS3) 266 return (mips3_vad_to_pfn(x)); 267 return (mips1_vad_to_pfn(x)); 268 } 269 #endif 270 271 #endif /* ! _LOCORE */ 272 273 #if defined(_KERNEL) && !defined(_LOCORE) 274 /* 275 * Kernel virtual address to page table entry and visa versa. 276 */ 277 #define kvtopte(va) \ 278 (Sysmap + (((vm_offset_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT)) 279 #define ptetokv(pte) \ 280 ((((pt_entry_t *)(pte) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) 281 282 extern pt_entry_t *Sysmap; /* kernel pte table */ 283 extern u_int Sysmapsize; /* number of pte's in Sysmap */ 284 #endif /* defined(_KERNEL) && !defined(_LOCORE) */ 285 286 /* 287 * User virtual to pte page entry. Same on mips1 and mips3. 288 */ 289 #define uvtopte(adr) (((adr) >> PGSHIFT) & (NPTEPG - 1)) 290 291 292 #endif /* __MIPS_PTE_H__ */ 293