1 /* $NetBSD: pte.h,v 1.20 2011/02/20 07:45:47 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright 1996 The Board of Trustees of The Leland Stanford 35 * Junior University. All Rights Reserved. 36 * 37 * Permission to use, copy, modify, and distribute this 38 * software and its documentation for any purpose and without 39 * fee is hereby granted, provided that the above copyright 40 * notice appear in all copies. Stanford University 41 * makes no representations about the suitability of this 42 * software for any purpose. It is provided "as is" without 43 * express or implied warranty. 44 */ 45 46 #ifndef __MIPS_PTE_H__ 47 #define __MIPS_PTE_H__ 48 49 #include <mips/mips1_pte.h> 50 #include <mips/mips3_pte.h> 51 52 #define PG_ASID 0x000000ff /* Address space ID */ 53 54 #ifndef _LOCORE 55 #include <mips/cpu.h> 56 57 typedef union pt_entry { 58 uint32_t pt_entry; /* for copying, etc. */ 59 struct mips1_pte pt_mips1_pte; /* for getting to bits by name */ 60 struct mips3_pte pt_mips3_pte; 61 } pt_entry_t; 62 63 /* 64 * Macros/inline functions to hide PTE format differences. 65 */ 66 67 #define mips_pg_nv_bit() (MIPS1_PG_NV) /* same on mips1 and mips3 */ 68 69 70 bool pmap_is_page_ro_p(struct pmap *pmap, vaddr_t, uint32_t); 71 72 73 /* MIPS1-only */ 74 #if defined(MIPS1) && !defined(MIPS3_PLUS) 75 #define mips_pg_v(entry) ((entry) & MIPS1_PG_V) 76 #define mips_pg_wired(entry) ((entry) & MIPS1_PG_WIRED) 77 78 #define mips_pg_m_bit() (MIPS1_PG_D) 79 #define mips_pg_rw_bit() (MIPS1_PG_RW) /* no RW bits for mips1 */ 80 #define mips_pg_ro_bit() (MIPS1_PG_RO) 81 #define mips_pg_ropage_bit() (MIPS1_PG_RO) /* XXX not MIPS1_PG_ROPAGE? */ 82 #define mips_pg_rwpage_bit() (MIPS1_PG_RWPAGE) 83 #define mips_pg_rwncpage_bit() (MIPS1_PG_RWNCPAGE) 84 #define mips_pg_cwpage_bit() (MIPS1_PG_CWPAGE) 85 #define mips_pg_cwncpage_bit() (MIPS1_PG_CWNCPAGE) 86 #define mips_pg_global_bit() (MIPS1_PG_G) 87 #define mips_pg_wired_bit() (MIPS1_PG_WIRED) 88 89 #define PTE_TO_PADDR(pte) MIPS1_PTE_TO_PADDR((pte)) 90 #define PAGE_IS_RDONLY(pte, va) MIPS1_PAGE_IS_RDONLY((pte), (va)) 91 92 #define mips_tlbpfn_to_paddr(x) mips1_tlbpfn_to_paddr((vaddr_t)(x)) 93 #define mips_paddr_to_tlbpfn(x) mips1_paddr_to_tlbpfn((x)) 94 #endif /* mips1 */ 95 96 97 /* MIPS3 (or greater) only */ 98 #if !defined(MIPS1) && defined(MIPS3_PLUS) 99 #define mips_pg_v(entry) ((entry) & MIPS3_PG_V) 100 #define mips_pg_wired(entry) ((entry) & MIPS3_PG_WIRED) 101 102 #define mips_pg_m_bit() (MIPS3_PG_D) 103 #define mips_pg_rw_bit() (MIPS3_PG_D) 104 #define mips_pg_ro_bit() (MIPS3_PG_RO) 105 #define mips_pg_ropage_bit() (MIPS3_PG_ROPAGE) 106 #define mips_pg_rwpage_bit() (MIPS3_PG_RWPAGE) 107 #define mips_pg_rwncpage_bit() (MIPS3_PG_RWNCPAGE) 108 #define mips_pg_cwpage_bit() (MIPS3_PG_CWPAGE) 109 #define mips_pg_cwncpage_bit() (MIPS3_PG_CWNCPAGE) 110 #define mips_pg_global_bit() (MIPS3_PG_G) 111 #define mips_pg_wired_bit() (MIPS3_PG_WIRED) 112 113 #define PTE_TO_PADDR(pte) MIPS3_PTE_TO_PADDR((pte)) 114 #define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va)) 115 116 #define mips_tlbpfn_to_paddr(x) mips3_tlbpfn_to_paddr((vaddr_t)(x)) 117 #define mips_paddr_to_tlbpfn(x) mips3_paddr_to_tlbpfn((x)) 118 #endif /* mips3 */ 119 120 /* MIPS1 and MIPS3 (or greater) */ 121 #if defined(MIPS1) && defined(MIPS3_PLUS) 122 123 static __inline bool 124 mips_pg_v(uint32_t entry), 125 mips_pg_wired(uint32_t entry), 126 PAGE_IS_RDONLY(uint32_t pte, vaddr_t va); 127 128 static __inline uint32_t 129 mips_pg_wired_bit(void) __pure, 130 mips_pg_m_bit(void) __pure, 131 mips_pg_ro_bit(void) __pure, 132 mips_pg_rw_bit(void) __pure, 133 mips_pg_ropage_bit(void) __pure, 134 mips_pg_cwpage_bit(void) __pure, 135 mips_pg_rwpage_bit(void) __pure, 136 mips_pg_global_bit(void) __pure; 137 static __inline paddr_t PTE_TO_PADDR(uint32_t pte) __pure; 138 static __inline bool PAGE_IS_RDONLY(uint32_t pte, vaddr_t va) __pure; 139 140 static __inline paddr_t mips_tlbpfn_to_paddr(uint32_t pfn) __pure; 141 static __inline uint32_t mips_paddr_to_tlbpfn(paddr_t pa) __pure; 142 143 144 static __inline bool 145 mips_pg_v(uint32_t entry) 146 { 147 if (MIPS_HAS_R4K_MMU) 148 return (entry & MIPS3_PG_V) != 0; 149 return (entry & MIPS1_PG_V) != 0; 150 } 151 152 static __inline bool 153 mips_pg_wired(uint32_t entry) 154 { 155 if (MIPS_HAS_R4K_MMU) 156 return (entry & MIPS3_PG_WIRED) != 0; 157 return (entry & MIPS1_PG_WIRED) != 0; 158 } 159 160 static __inline uint32_t 161 mips_pg_m_bit(void) 162 { 163 if (MIPS_HAS_R4K_MMU) 164 return (MIPS3_PG_D); 165 return (MIPS1_PG_D); 166 } 167 168 static __inline unsigned int 169 mips_pg_ro_bit(void) 170 { 171 if (MIPS_HAS_R4K_MMU) 172 return (MIPS3_PG_RO); 173 return (MIPS1_PG_RO); 174 } 175 176 static __inline unsigned int 177 mips_pg_rw_bit(void) 178 { 179 if (MIPS_HAS_R4K_MMU) 180 return (MIPS3_PG_D); 181 return (MIPS1_PG_RW); 182 } 183 184 static __inline unsigned int 185 mips_pg_ropage_bit(void) 186 { 187 if (MIPS_HAS_R4K_MMU) 188 return (MIPS3_PG_ROPAGE); 189 return (MIPS1_PG_RO); 190 } 191 192 static __inline unsigned int 193 mips_pg_rwpage_bit(void) 194 { 195 if (MIPS_HAS_R4K_MMU) 196 return (MIPS3_PG_RWPAGE); 197 return (MIPS1_PG_RWPAGE); 198 } 199 200 static __inline unsigned int 201 mips_pg_cwpage_bit(void) 202 { 203 if (MIPS_HAS_R4K_MMU) 204 return (MIPS3_PG_CWPAGE); 205 return (MIPS1_PG_CWPAGE); 206 } 207 208 209 static __inline unsigned int 210 mips_pg_global_bit(void) 211 { 212 if (MIPS_HAS_R4K_MMU) 213 return (MIPS3_PG_G); 214 return (MIPS1_PG_G); 215 } 216 217 static __inline unsigned int 218 mips_pg_wired_bit(void) 219 { 220 if (MIPS_HAS_R4K_MMU) 221 return (MIPS3_PG_WIRED); 222 return (MIPS1_PG_WIRED); 223 } 224 225 static __inline paddr_t 226 PTE_TO_PADDR(uint32_t pte) 227 { 228 if (MIPS_HAS_R4K_MMU) 229 return (MIPS3_PTE_TO_PADDR(pte)); 230 return (MIPS1_PTE_TO_PADDR(pte)); 231 } 232 233 static __inline bool 234 PAGE_IS_RDONLY(uint32_t pte, vaddr_t va) 235 { 236 if (MIPS_HAS_R4K_MMU) 237 return (MIPS3_PAGE_IS_RDONLY(pte, va)); 238 return (MIPS1_PAGE_IS_RDONLY(pte, va)); 239 } 240 241 static __inline paddr_t 242 mips_tlbpfn_to_paddr(uint32_t pfn) 243 { 244 if (MIPS_HAS_R4K_MMU) 245 return (mips3_tlbpfn_to_paddr(pfn)); 246 return (mips1_tlbpfn_to_paddr(pfn)); 247 } 248 249 static __inline uint32_t 250 mips_paddr_to_tlbpfn(paddr_t pa) 251 { 252 if (MIPS_HAS_R4K_MMU) 253 return (mips3_paddr_to_tlbpfn(pa)); 254 return (mips1_paddr_to_tlbpfn(pa)); 255 } 256 #endif 257 258 #endif /* ! _LOCORE */ 259 260 #if defined(_KERNEL) && !defined(_LOCORE) 261 /* 262 * Kernel virtual address to page table entry and visa versa. 263 */ 264 #define kvtopte(va) \ 265 (Sysmap + (((vaddr_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT)) 266 #define ptetokv(pte) \ 267 ((((pt_entry_t *)(pte) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) 268 269 extern pt_entry_t *Sysmap; /* kernel pte table */ 270 extern u_int Sysmapsize; /* number of pte's in Sysmap */ 271 #endif /* defined(_KERNEL) && !defined(_LOCORE) */ 272 #endif /* __MIPS_PTE_H__ */ 273