xref: /netbsd-src/sys/arch/mips/include/mips3_pte.h (revision 76dfffe33547c37f8bdd446e3e4ab0f3c16cea4b)
1 /*	$NetBSD: mips3_pte.h,v 1.5 1996/10/13 09:54:44 jonathan Exp $	*/
2 
3 /*
4  * Copyright (c) 1988 University of Utah.
5  * Copyright (c) 1992, 1993
6  *	The Regents of the University of California.  All rights reserved.
7  *
8  * This code is derived from software contributed to Berkeley by
9  * the Systems Programming Group of the University of Utah Computer
10  * Science Department and Ralph Campbell.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  * 3. All advertising materials mentioning features or use of this software
21  *    must display the following acknowledgement:
22  *	This product includes software developed by the University of
23  *	California, Berkeley and its contributors.
24  * 4. Neither the name of the University nor the names of its contributors
25  *    may be used to endorse or promote products derived from this software
26  *    without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  * from: Utah Hdr: pte.h 1.11 89/09/03
41  *
42  *	from: @(#)pte.h	8.1 (Berkeley) 6/10/93
43  */
44 
45 /*
46  * R4000 hardware page table entry
47  */
48 
49 #ifndef _LOCORE
50 struct pte {
51 #if BYTE_ORDER == BIG_ENDIAN
52 unsigned int	pg_prot:2,		/* SW: access control */
53 		pg_pfnum:24,		/* HW: core page frame number or 0 */
54 		pg_attr:3,		/* HW: cache attribute */
55 		pg_m:1,			/* HW: modified (dirty) bit */
56 		pg_v:1,			/* HW: valid bit */
57 		pg_g:1;			/* HW: ignore pid bit */
58 #endif
59 #if BYTE_ORDER == LITTLE_ENDIAN
60 unsigned int 	pg_g:1,			/* HW: ignore pid bit */
61 		pg_v:1,			/* HW: valid bit */
62 		pg_m:1,			/* HW: modified (dirty) bit */
63 		pg_attr:3,			/* HW: cache attribute */
64 		pg_pfnum:24,		/* HW: core page frame number or 0 */
65 		pg_prot:2;		/* SW: access control */
66 #endif
67 };
68 
69 /*
70  * Structure defining an tlb entry data set.
71  */
72 
73 struct tlb {
74 	int	tlb_mask;
75 	int	tlb_hi;
76 	int	tlb_lo0;
77 	int	tlb_lo1;
78 };
79 
80 typedef union pt_entry {
81 	unsigned int	pt_entry;	/* for copying, etc. */
82 	struct pte	pt_pte;		/* for getting to bits by name */
83 } pt_entry_t;	/* Mach page table entry */
84 #endif /* _LOCORE */
85 
86 #define	PT_ENTRY_NULL	((pt_entry_t *) 0)
87 
88 #define PG_WIRED	0x80000000	/* SW */
89 #define PG_RO		0x40000000	/* SW */
90 
91 #define	PG_SVPN		0xfffff000	/* Software page no mask */
92 #define	PG_HVPN		0xffffe000	/* Hardware page no mask */
93 #define	PG_ODDPG	0x00001000	/* Odd even pte entry */
94 #define	PG_ASID		0x000000ff	/* Address space ID */
95 #define	PG_G		0x00000001	/* HW */
96 #define	PG_V		0x00000002
97 #define	PG_NV		0x00000000
98 #define	PG_M		0x00000004
99 #define	PG_ATTR		0x0000003f
100 #define	PG_UNCACHED	0x00000010
101 #define	PG_CACHED	0x00000018
102 #define	PG_CACHEMODE	0x00000038
103 #define	PG_ROPAGE	(PG_V | PG_RO | PG_CACHED) /* Write protected */
104 #define	PG_RWPAGE	(PG_V | PG_M | PG_CACHED)  /* Not wr-prot not clean */
105 #define	PG_CWPAGE	(PG_V | PG_CACHED)	   /* Not wr-prot but clean */
106 #define	PG_IOPAGE	(PG_G | PG_V | PG_M | PG_UNCACHED)
107 #define	PG_FRAME	0x3fffffc0
108 #define PG_SHIFT	6
109 
110 /* pte accessor macros */
111 
112 #define vad_to_pfn(x) (((unsigned)(x) >> PG_SHIFT) & PG_FRAME)
113 #define pfn_to_vad(x) (((x) & PG_FRAME) << PG_SHIFT)
114 #define vad_to_vpn(x) ((unsigned)(x) & PG_SVPN)
115 #define vpn_to_vad(x) ((x) & PG_SVPN)
116 
117 #define PTE_TO_PADDR(pte) (pfn_to_vad(pte))
118 #define PAGE_IS_RDONLY(pte,va) \
119     (pmap_is_page_ro(pmap_kernel(), mips_trunc_page(va), (pte)))
120 
121 
122 /* User virtual to pte page entry */
123 #define uvtopte(adr) (((adr) >> PGSHIFT) & (NPTEPG -1))
124 
125 #define	PG_SIZE_4K	0x00000000
126 #define	PG_SIZE_16K	0x00006000
127 #define	PG_SIZE_64K	0x0001e000
128 #define	PG_SIZE_256K	0x0007e000
129 #define	PG_SIZE_1M	0x001fe000
130 #define	PG_SIZE_4M	0x007fe000
131 #define	PG_SIZE_16M	0x01ffe000
132 
133