xref: /netbsd-src/sys/arch/mips/include/mips3_pte.h (revision 23c8222edbfb0f0932d88a8351d3a0cf817dfb9e)
1 /*	$NetBSD: mips3_pte.h,v 1.16 2003/08/07 16:28:28 agc Exp $	*/
2 
3 /*
4  * Copyright (c) 1992, 1993
5  *	The Regents of the University of California.  All rights reserved.
6  *
7  * This code is derived from software contributed to Berkeley by
8  * the Systems Programming Group of the University of Utah Computer
9  * Science Department and Ralph Campbell.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. Neither the name of the University nor the names of its contributors
20  *    may be used to endorse or promote products derived from this software
21  *    without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  *
35  * from: Utah Hdr: pte.h 1.11 89/09/03
36  *
37  *	from: @(#)pte.h	8.1 (Berkeley) 6/10/93
38  */
39 /*
40  * Copyright (c) 1988 University of Utah.
41  *
42  * This code is derived from software contributed to Berkeley by
43  * the Systems Programming Group of the University of Utah Computer
44  * Science Department and Ralph Campbell.
45  *
46  * Redistribution and use in source and binary forms, with or without
47  * modification, are permitted provided that the following conditions
48  * are met:
49  * 1. Redistributions of source code must retain the above copyright
50  *    notice, this list of conditions and the following disclaimer.
51  * 2. Redistributions in binary form must reproduce the above copyright
52  *    notice, this list of conditions and the following disclaimer in the
53  *    documentation and/or other materials provided with the distribution.
54  * 3. All advertising materials mentioning features or use of this software
55  *    must display the following acknowledgement:
56  *	This product includes software developed by the University of
57  *	California, Berkeley and its contributors.
58  * 4. Neither the name of the University nor the names of its contributors
59  *    may be used to endorse or promote products derived from this software
60  *    without specific prior written permission.
61  *
62  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
63  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
64  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
65  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
66  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
67  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
68  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
69  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
70  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
71  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72  * SUCH DAMAGE.
73  *
74  * from: Utah Hdr: pte.h 1.11 89/09/03
75  *
76  *	from: @(#)pte.h	8.1 (Berkeley) 6/10/93
77  */
78 
79 /*
80  * R4000 hardware page table entry
81  */
82 
83 #ifndef _LOCORE
84 struct mips3_pte {
85 #if BYTE_ORDER == BIG_ENDIAN
86 unsigned int	pg_prot:2,		/* SW: access control */
87 		pg_pfnum:24,		/* HW: core page frame number or 0 */
88 		pg_attr:3,		/* HW: cache attribute */
89 		pg_m:1,			/* HW: dirty bit */
90 		pg_v:1,			/* HW: valid bit */
91 		pg_g:1;			/* HW: ignore asid bit */
92 #endif
93 #if BYTE_ORDER == LITTLE_ENDIAN
94 unsigned int 	pg_g:1,			/* HW: ignore asid bit */
95 		pg_v:1,			/* HW: valid bit */
96 		pg_m:1,			/* HW: dirty bit */
97 		pg_attr:3,		/* HW: cache attribute */
98 		pg_pfnum:24,		/* HW: core page frame number or 0 */
99 		pg_prot:2;		/* SW: access control */
100 #endif
101 };
102 
103 /*
104  * Structure defining an tlb entry data set.
105  */
106 
107 struct tlb {
108 	int	tlb_mask;
109 	int	tlb_hi;		/* XXX should be 64 bits */
110 	int	tlb_lo0;	/* XXX maybe 64 bits (only 32 really used) */
111 	int	tlb_lo1;	/* XXX maybe 64 bits (only 32 really used) */
112 };
113 #endif /* _LOCORE */
114 
115 #define MIPS3_PG_WIRED	0x80000000	/* SW */
116 #define MIPS3_PG_RO	0x40000000	/* SW */
117 
118 #define	MIPS3_PG_SVPN	0xfffff000	/* Software page no mask */
119 #define	MIPS3_PG_HVPN	0xffffe000	/* Hardware page no mask */
120 #define	MIPS3_PG_ODDPG	0x00001000	/* Odd even pte entry */
121 #define	MIPS3_PG_ASID	0x000000ff	/* Address space ID */
122 #define	MIPS3_PG_G	0x00000001	/* Global; ignore ASID if in lo0 & lo1 */
123 #define	MIPS3_PG_V	0x00000002	/* Valid */
124 #define	MIPS3_PG_NV	0x00000000
125 #define	MIPS3_PG_D	0x00000004	/* Dirty */
126 #define	MIPS3_PG_ATTR	0x0000003f
127 
128 #define	MIPS3_CCA_TO_PG(cca)	((cca) << 3)
129 
130 #define	MIPS3_PG_UNCACHED	MIPS3_CCA_TO_PG(2)
131 #ifdef HPCMIPS_L1CACHE_DISABLE		/* MIPS3_L1CACHE_DISABLE */
132 #define	MIPS3_PG_CACHED		MIPS3_PG_UNCACHED	/* XXX: brain damaged!!! */
133 #else /* HPCMIPS_L1CACHE_DISABLE */
134 #define	MIPS3_PG_CACHED		mips3_pg_cached
135 #define	MIPS3_DEFAULT_PG_CACHED	MIPS3_CCA_TO_PG(3)
136 #endif /* ! HPCMIPS_L1CACHE_DISABLE */
137 #define	MIPS3_PG_CACHEMODE	MIPS3_CCA_TO_PG(7)
138 
139 /* Write protected */
140 #define	MIPS3_PG_ROPAGE	(MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED)
141 
142 /* Not wr-prot not clean */
143 #define	MIPS3_PG_RWPAGE	(MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_CACHED)
144 
145 /* Not wr-prot but clean */
146 #define	MIPS3_PG_CWPAGE	(MIPS3_PG_V | MIPS3_PG_CACHED)
147 #define	MIPS3_PG_IOPAGE(cca) \
148 	(MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_D | MIPS3_CCA_TO_PG(cca))
149 #define	MIPS3_PG_FRAME	0x3fffffc0
150 #ifdef MIPS3_4100			/* VR4100 core */
151 #define MIPS3_PG_SHIFT	4
152 #else
153 #define MIPS3_PG_SHIFT	6
154 #endif
155 
156 /* pte accessor macros */
157 
158 #define mips3_pfn_is_ext(x) ((x) & 0x3c000000)
159 #define mips3_paddr_to_tlbpfn(x) \
160     (((paddr_t)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
161 #define mips3_tlbpfn_to_paddr(x) \
162     ((paddr_t)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
163 #define mips3_vad_to_vpn(x) ((vaddr_t)(x) & MIPS3_PG_SVPN)
164 #define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN)
165 
166 #define MIPS3_PTE_TO_PADDR(pte) (mips3_tlbpfn_to_paddr(pte))
167 #define MIPS3_PAGE_IS_RDONLY(pte,va) \
168     (pmap_is_page_ro(pmap_kernel(), mips_trunc_page(va), (pte)))
169 
170 
171 #define	MIPS3_PG_SIZE_4K	0x00000000
172 #define	MIPS3_PG_SIZE_16K	0x00006000
173 #define	MIPS3_PG_SIZE_64K	0x0001e000
174 #define	MIPS3_PG_SIZE_256K	0x0007e000
175 #define	MIPS3_PG_SIZE_1M	0x001fe000
176 #define	MIPS3_PG_SIZE_4M	0x007fe000
177 #define	MIPS3_PG_SIZE_16M	0x01ffe000
178 #define	MIPS3_PG_SIZE_64M	0x07ffe000
179 #define	MIPS3_PG_SIZE_256M	0x1fffe000
180