1 /* $NetBSD: intr.h,v 1.7 2012/03/11 00:02:05 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _MIPS_INTR_H_ 33 #define _MIPS_INTR_H_ 34 35 #ifdef _KERNEL_OPT 36 #include "opt_multiprocessor.h" 37 #endif 38 39 /* 40 * This is a common <machine/intr.h> for all MIPS platforms. 41 */ 42 43 #define IPL_NONE 0 44 #define IPL_SOFTCLOCK (IPL_NONE+1) 45 #define IPL_SOFTBIO (IPL_SOFTCLOCK) /* shares SWINT with softclock */ 46 #define IPL_SOFTNET (IPL_SOFTBIO+1) 47 #define IPL_SOFTSERIAL (IPL_SOFTNET) /* shares SWINT with softnet */ 48 #define IPL_VM (IPL_SOFTSERIAL+1) 49 #define IPL_SCHED (IPL_VM+1) 50 #define IPL_DDB (IPL_SCHED+1) 51 #define IPL_HIGH (IPL_DDB+1) 52 53 #define IPL_SAFEPRI IPL_SOFTSERIAL 54 55 #define _IPL_N (IPL_HIGH+1) 56 #define _IPL_NAMES(pfx) { pfx"none", pfx"softclock/bio", pfx"softnet/serial", \ 57 pfx"vm", pfx"sched", pfx"ddb", pfx"high" } 58 59 #define IST_UNUSABLE -1 /* interrupt cannot be used */ 60 #define IST_NONE 0 /* none (dummy) */ 61 #define IST_PULSE 1 /* pulsed */ 62 #define IST_EDGE 2 /* edge-triggered */ 63 #define IST_LEVEL 3 /* level-triggered */ 64 #define IST_LEVEL_HIGH 4 /* level triggered, active high */ 65 #define IST_LEVEL_LOW 5 /* level triggered, active low */ 66 67 #define IPI_NOP 0 /* do nothing, interrupt only */ 68 #define IPI_AST 1 /* force ast */ 69 #define IPI_SHOOTDOWN 2 /* do a tlb shootdown */ 70 #define IPI_SYNCICACHE 3 /* sync icache for pages */ 71 #define IPI_KPREEMPT 4 /* schedule a kernel preemption */ 72 #define IPI_SUSPEND 5 /* DDB suspend signaling */ 73 #define IPI_HALT 6 /* halt cpu */ 74 #define IPI_XCALL 7 /* xcall */ 75 #define NIPIS 8 76 77 #ifdef __INTR_PRIVATE 78 struct splsw { 79 int (*splsw_splhigh)(void); 80 int (*splsw_splsched)(void); 81 int (*splsw_splvm)(void); 82 int (*splsw_splsoftserial)(void); 83 int (*splsw_splsoftnet)(void); 84 int (*splsw_splsoftbio)(void); 85 int (*splsw_splsoftclock)(void); 86 int (*splsw_splraise)(int); 87 void (*splsw_spl0)(void); 88 void (*splsw_splx)(int); 89 int (*splsw_splhigh_noprof)(void); 90 void (*splsw_splx_noprof)(int); 91 void (*splsw__setsoftintr)(uint32_t); 92 void (*splsw__clrsoftintr)(uint32_t); 93 int (*splsw_splintr)(uint32_t *); 94 void (*splsw_splcheck)(void); 95 }; 96 97 struct ipl_sr_map { 98 uint32_t sr_bits[_IPL_N]; 99 }; 100 #else 101 struct splsw; 102 #endif /* __INTR_PRIVATE */ 103 104 typedef int ipl_t; 105 typedef struct { 106 ipl_t _spl; 107 } ipl_cookie_t; 108 109 #ifdef _KERNEL 110 111 #if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS) 112 #define __HAVE_PREEMPTION 1 113 #define SOFTINT_KPREEMPT (SOFTINT_COUNT+0) 114 #endif 115 116 #ifdef __INTR_PRIVATE 117 extern struct splsw mips_splsw; 118 extern struct ipl_sr_map ipl_sr_map; 119 #endif /* __INTR_PRIVATE */ 120 121 int splhigh(void); 122 int splhigh_noprof(void); 123 int splsched(void); 124 int splvm(void); 125 int splsoftserial(void); 126 int splsoftnet(void); 127 int splsoftbio(void); 128 int splsoftclock(void); 129 int splraise(int); 130 void splx(int); 131 void splx_noprof(int); 132 void spl0(void); 133 int splintr(uint32_t *); 134 void _setsoftintr(uint32_t); 135 void _clrsoftintr(uint32_t); 136 137 struct cpu_info; 138 139 void ipi_init(struct cpu_info *); 140 void ipi_process(struct cpu_info *, uint64_t); 141 142 /* 143 * These make no sense *NOT* to be inlined. 144 */ 145 static inline ipl_cookie_t 146 makeiplcookie(ipl_t s) 147 { 148 return (ipl_cookie_t){._spl = s}; 149 } 150 151 static inline int 152 splraiseipl(ipl_cookie_t icookie) 153 { 154 return splraise(icookie._spl); 155 } 156 157 #endif /* _KERNEL */ 158 #endif /* _MIPS_INTR_H_ */ 159